1 /* 2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. 3 * Author: Lin Huang <hl@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/arm-smccc.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/devfreq.h> 19 #include <linux/devfreq-event.h> 20 #include <linux/interrupt.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_opp.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/rwsem.h> 27 #include <linux/suspend.h> 28 29 #include <soc/rockchip/rockchip_sip.h> 30 31 struct dram_timing { 32 unsigned int ddr3_speed_bin; 33 unsigned int pd_idle; 34 unsigned int sr_idle; 35 unsigned int sr_mc_gate_idle; 36 unsigned int srpd_lite_idle; 37 unsigned int standby_idle; 38 unsigned int auto_pd_dis_freq; 39 unsigned int dram_dll_dis_freq; 40 unsigned int phy_dll_dis_freq; 41 unsigned int ddr3_odt_dis_freq; 42 unsigned int ddr3_drv; 43 unsigned int ddr3_odt; 44 unsigned int phy_ddr3_ca_drv; 45 unsigned int phy_ddr3_dq_drv; 46 unsigned int phy_ddr3_odt; 47 unsigned int lpddr3_odt_dis_freq; 48 unsigned int lpddr3_drv; 49 unsigned int lpddr3_odt; 50 unsigned int phy_lpddr3_ca_drv; 51 unsigned int phy_lpddr3_dq_drv; 52 unsigned int phy_lpddr3_odt; 53 unsigned int lpddr4_odt_dis_freq; 54 unsigned int lpddr4_drv; 55 unsigned int lpddr4_dq_odt; 56 unsigned int lpddr4_ca_odt; 57 unsigned int phy_lpddr4_ca_drv; 58 unsigned int phy_lpddr4_ck_cs_drv; 59 unsigned int phy_lpddr4_dq_drv; 60 unsigned int phy_lpddr4_odt; 61 }; 62 63 struct rk3399_dmcfreq { 64 struct device *dev; 65 struct devfreq *devfreq; 66 struct devfreq_simple_ondemand_data ondemand_data; 67 struct clk *dmc_clk; 68 struct devfreq_event_dev *edev; 69 struct mutex lock; 70 struct dram_timing timing; 71 struct regulator *vdd_center; 72 unsigned long rate, target_rate; 73 unsigned long volt, target_volt; 74 }; 75 76 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, 77 u32 flags) 78 { 79 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 80 struct dev_pm_opp *opp; 81 unsigned long old_clk_rate = dmcfreq->rate; 82 unsigned long target_volt, target_rate; 83 int err; 84 85 opp = devfreq_recommended_opp(dev, freq, flags); 86 if (IS_ERR(opp)) 87 return PTR_ERR(opp); 88 89 target_rate = dev_pm_opp_get_freq(opp); 90 target_volt = dev_pm_opp_get_voltage(opp); 91 dev_pm_opp_put(opp); 92 93 if (dmcfreq->rate == target_rate) 94 return 0; 95 96 mutex_lock(&dmcfreq->lock); 97 98 /* 99 * If frequency scaling from low to high, adjust voltage first. 100 * If frequency scaling from high to low, adjust frequency first. 101 */ 102 if (old_clk_rate < target_rate) { 103 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 104 target_volt); 105 if (err) { 106 dev_err(dev, "Cannot set voltage %lu uV\n", 107 target_volt); 108 goto out; 109 } 110 } 111 112 err = clk_set_rate(dmcfreq->dmc_clk, target_rate); 113 if (err) { 114 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate, 115 err); 116 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 117 dmcfreq->volt); 118 goto out; 119 } 120 121 /* 122 * Check the dpll rate, 123 * There only two result we will get, 124 * 1. Ddr frequency scaling fail, we still get the old rate. 125 * 2. Ddr frequency scaling sucessful, we get the rate we set. 126 */ 127 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); 128 129 /* If get the incorrect rate, set voltage to old value. */ 130 if (dmcfreq->rate != target_rate) { 131 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n", 132 target_rate, dmcfreq->rate); 133 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 134 dmcfreq->volt); 135 goto out; 136 } else if (old_clk_rate > target_rate) 137 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 138 target_volt); 139 if (err) 140 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt); 141 142 dmcfreq->rate = target_rate; 143 dmcfreq->volt = target_volt; 144 145 out: 146 mutex_unlock(&dmcfreq->lock); 147 return err; 148 } 149 150 static int rk3399_dmcfreq_get_dev_status(struct device *dev, 151 struct devfreq_dev_status *stat) 152 { 153 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 154 struct devfreq_event_data edata; 155 int ret = 0; 156 157 ret = devfreq_event_get_event(dmcfreq->edev, &edata); 158 if (ret < 0) 159 return ret; 160 161 stat->current_frequency = dmcfreq->rate; 162 stat->busy_time = edata.load_count; 163 stat->total_time = edata.total_count; 164 165 return ret; 166 } 167 168 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) 169 { 170 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 171 172 *freq = dmcfreq->rate; 173 174 return 0; 175 } 176 177 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = { 178 .polling_ms = 200, 179 .target = rk3399_dmcfreq_target, 180 .get_dev_status = rk3399_dmcfreq_get_dev_status, 181 .get_cur_freq = rk3399_dmcfreq_get_cur_freq, 182 }; 183 184 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) 185 { 186 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 187 int ret = 0; 188 189 ret = devfreq_event_disable_edev(dmcfreq->edev); 190 if (ret < 0) { 191 dev_err(dev, "failed to disable the devfreq-event devices\n"); 192 return ret; 193 } 194 195 ret = devfreq_suspend_device(dmcfreq->devfreq); 196 if (ret < 0) { 197 dev_err(dev, "failed to suspend the devfreq devices\n"); 198 return ret; 199 } 200 201 return 0; 202 } 203 204 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) 205 { 206 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 207 int ret = 0; 208 209 ret = devfreq_event_enable_edev(dmcfreq->edev); 210 if (ret < 0) { 211 dev_err(dev, "failed to enable the devfreq-event devices\n"); 212 return ret; 213 } 214 215 ret = devfreq_resume_device(dmcfreq->devfreq); 216 if (ret < 0) { 217 dev_err(dev, "failed to resume the devfreq devices\n"); 218 return ret; 219 } 220 return ret; 221 } 222 223 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, 224 rk3399_dmcfreq_resume); 225 226 static int of_get_ddr_timings(struct dram_timing *timing, 227 struct device_node *np) 228 { 229 int ret = 0; 230 231 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin", 232 &timing->ddr3_speed_bin); 233 ret |= of_property_read_u32(np, "rockchip,pd_idle", 234 &timing->pd_idle); 235 ret |= of_property_read_u32(np, "rockchip,sr_idle", 236 &timing->sr_idle); 237 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle", 238 &timing->sr_mc_gate_idle); 239 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle", 240 &timing->srpd_lite_idle); 241 ret |= of_property_read_u32(np, "rockchip,standby_idle", 242 &timing->standby_idle); 243 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq", 244 &timing->auto_pd_dis_freq); 245 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq", 246 &timing->dram_dll_dis_freq); 247 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq", 248 &timing->phy_dll_dis_freq); 249 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", 250 &timing->ddr3_odt_dis_freq); 251 ret |= of_property_read_u32(np, "rockchip,ddr3_drv", 252 &timing->ddr3_drv); 253 ret |= of_property_read_u32(np, "rockchip,ddr3_odt", 254 &timing->ddr3_odt); 255 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", 256 &timing->phy_ddr3_ca_drv); 257 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", 258 &timing->phy_ddr3_dq_drv); 259 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt", 260 &timing->phy_ddr3_odt); 261 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", 262 &timing->lpddr3_odt_dis_freq); 263 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv", 264 &timing->lpddr3_drv); 265 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt", 266 &timing->lpddr3_odt); 267 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", 268 &timing->phy_lpddr3_ca_drv); 269 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", 270 &timing->phy_lpddr3_dq_drv); 271 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt", 272 &timing->phy_lpddr3_odt); 273 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", 274 &timing->lpddr4_odt_dis_freq); 275 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv", 276 &timing->lpddr4_drv); 277 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt", 278 &timing->lpddr4_dq_odt); 279 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt", 280 &timing->lpddr4_ca_odt); 281 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", 282 &timing->phy_lpddr4_ca_drv); 283 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", 284 &timing->phy_lpddr4_ck_cs_drv); 285 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", 286 &timing->phy_lpddr4_dq_drv); 287 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt", 288 &timing->phy_lpddr4_odt); 289 290 return ret; 291 } 292 293 static int rk3399_dmcfreq_probe(struct platform_device *pdev) 294 { 295 struct arm_smccc_res res; 296 struct device *dev = &pdev->dev; 297 struct device_node *np = pdev->dev.of_node; 298 struct rk3399_dmcfreq *data; 299 int ret, index, size; 300 uint32_t *timing; 301 struct dev_pm_opp *opp; 302 303 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); 304 if (!data) 305 return -ENOMEM; 306 307 mutex_init(&data->lock); 308 309 data->vdd_center = devm_regulator_get(dev, "center"); 310 if (IS_ERR(data->vdd_center)) { 311 if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER) 312 return -EPROBE_DEFER; 313 314 dev_err(dev, "Cannot get the regulator \"center\"\n"); 315 return PTR_ERR(data->vdd_center); 316 } 317 318 data->dmc_clk = devm_clk_get(dev, "dmc_clk"); 319 if (IS_ERR(data->dmc_clk)) { 320 if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) 321 return -EPROBE_DEFER; 322 323 dev_err(dev, "Cannot get the clk dmc_clk\n"); 324 return PTR_ERR(data->dmc_clk); 325 }; 326 327 data->edev = devfreq_event_get_edev_by_phandle(dev, 0); 328 if (IS_ERR(data->edev)) 329 return -EPROBE_DEFER; 330 331 ret = devfreq_event_enable_edev(data->edev); 332 if (ret < 0) { 333 dev_err(dev, "failed to enable devfreq-event devices\n"); 334 return ret; 335 } 336 337 /* 338 * Get dram timing and pass it to arm trust firmware, 339 * the dram drvier in arm trust firmware will get these 340 * timing and to do dram initial. 341 */ 342 if (!of_get_ddr_timings(&data->timing, np)) { 343 timing = &data->timing.ddr3_speed_bin; 344 size = sizeof(struct dram_timing) / 4; 345 for (index = 0; index < size; index++) { 346 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, 347 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, 348 0, 0, 0, 0, &res); 349 if (res.a0) { 350 dev_err(dev, "Failed to set dram param: %ld\n", 351 res.a0); 352 return -EINVAL; 353 } 354 } 355 } 356 357 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, 358 ROCKCHIP_SIP_CONFIG_DRAM_INIT, 359 0, 0, 0, 0, &res); 360 361 /* 362 * We add a devfreq driver to our parent since it has a device tree node 363 * with operating points. 364 */ 365 if (dev_pm_opp_of_add_table(dev)) { 366 dev_err(dev, "Invalid operating-points in device tree.\n"); 367 return -EINVAL; 368 } 369 370 of_property_read_u32(np, "upthreshold", 371 &data->ondemand_data.upthreshold); 372 of_property_read_u32(np, "downdifferential", 373 &data->ondemand_data.downdifferential); 374 375 data->rate = clk_get_rate(data->dmc_clk); 376 377 opp = devfreq_recommended_opp(dev, &data->rate, 0); 378 if (IS_ERR(opp)) { 379 ret = PTR_ERR(opp); 380 goto err_free_opp; 381 } 382 383 data->rate = dev_pm_opp_get_freq(opp); 384 data->volt = dev_pm_opp_get_voltage(opp); 385 dev_pm_opp_put(opp); 386 387 rk3399_devfreq_dmc_profile.initial_freq = data->rate; 388 389 data->devfreq = devm_devfreq_add_device(dev, 390 &rk3399_devfreq_dmc_profile, 391 DEVFREQ_GOV_SIMPLE_ONDEMAND, 392 &data->ondemand_data); 393 if (IS_ERR(data->devfreq)) { 394 ret = PTR_ERR(data->devfreq); 395 goto err_free_opp; 396 } 397 398 devm_devfreq_register_opp_notifier(dev, data->devfreq); 399 400 data->dev = dev; 401 platform_set_drvdata(pdev, data); 402 403 return 0; 404 405 err_free_opp: 406 dev_pm_opp_of_remove_table(&pdev->dev); 407 return ret; 408 } 409 410 static int rk3399_dmcfreq_remove(struct platform_device *pdev) 411 { 412 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); 413 414 /* 415 * Before remove the opp table we need to unregister the opp notifier. 416 */ 417 devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); 418 dev_pm_opp_of_remove_table(dmcfreq->dev); 419 420 return 0; 421 } 422 423 static const struct of_device_id rk3399dmc_devfreq_of_match[] = { 424 { .compatible = "rockchip,rk3399-dmc" }, 425 { }, 426 }; 427 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match); 428 429 static struct platform_driver rk3399_dmcfreq_driver = { 430 .probe = rk3399_dmcfreq_probe, 431 .remove = rk3399_dmcfreq_remove, 432 .driver = { 433 .name = "rk3399-dmc-freq", 434 .pm = &rk3399_dmcfreq_pm, 435 .of_match_table = rk3399dmc_devfreq_of_match, 436 }, 437 }; 438 module_platform_driver(rk3399_dmcfreq_driver); 439 440 MODULE_LICENSE("GPL v2"); 441 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>"); 442 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); 443