1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f262f28cSChanwoo Choi /* 3f262f28cSChanwoo Choi * exynos_ppmu.c - EXYNOS PPMU (Platform Performance Monitoring Unit) support 4f262f28cSChanwoo Choi * 577fe46a3SChanwoo Choi * Copyright (c) 2014-2015 Samsung Electronics Co., Ltd. 6f262f28cSChanwoo Choi * Author : Chanwoo Choi <cw00.choi@samsung.com> 7f262f28cSChanwoo Choi * 8f262f28cSChanwoo Choi * This driver is based on drivers/devfreq/exynos/exynos_ppmu.c 9f262f28cSChanwoo Choi */ 10f262f28cSChanwoo Choi 11f262f28cSChanwoo Choi #include <linux/clk.h> 12f262f28cSChanwoo Choi #include <linux/io.h> 13f262f28cSChanwoo Choi #include <linux/kernel.h> 14f262f28cSChanwoo Choi #include <linux/module.h> 15f262f28cSChanwoo Choi #include <linux/of_address.h> 160ae9c321SLukasz Luba #include <linux/of_device.h> 17f262f28cSChanwoo Choi #include <linux/platform_device.h> 182a3ea647SChanwoo Choi #include <linux/regmap.h> 19f262f28cSChanwoo Choi #include <linux/suspend.h> 20f262f28cSChanwoo Choi #include <linux/devfreq-event.h> 21f262f28cSChanwoo Choi 22f262f28cSChanwoo Choi #include "exynos-ppmu.h" 23f262f28cSChanwoo Choi 240ae9c321SLukasz Luba enum exynos_ppmu_type { 250ae9c321SLukasz Luba EXYNOS_TYPE_PPMU, 260ae9c321SLukasz Luba EXYNOS_TYPE_PPMU_V2, 270ae9c321SLukasz Luba }; 280ae9c321SLukasz Luba 29f262f28cSChanwoo Choi struct exynos_ppmu_data { 30f262f28cSChanwoo Choi struct clk *clk; 31f262f28cSChanwoo Choi }; 32f262f28cSChanwoo Choi 33f262f28cSChanwoo Choi struct exynos_ppmu { 34f262f28cSChanwoo Choi struct devfreq_event_dev **edev; 35f262f28cSChanwoo Choi struct devfreq_event_desc *desc; 36f262f28cSChanwoo Choi unsigned int num_events; 37f262f28cSChanwoo Choi 38f262f28cSChanwoo Choi struct device *dev; 392a3ea647SChanwoo Choi struct regmap *regmap; 40f262f28cSChanwoo Choi 41f262f28cSChanwoo Choi struct exynos_ppmu_data ppmu; 420ae9c321SLukasz Luba enum exynos_ppmu_type ppmu_type; 43f262f28cSChanwoo Choi }; 44f262f28cSChanwoo Choi 45f262f28cSChanwoo Choi #define PPMU_EVENT(name) \ 46f262f28cSChanwoo Choi { "ppmu-event0-"#name, PPMU_PMNCNT0 }, \ 47f262f28cSChanwoo Choi { "ppmu-event1-"#name, PPMU_PMNCNT1 }, \ 48f262f28cSChanwoo Choi { "ppmu-event2-"#name, PPMU_PMNCNT2 }, \ 49f262f28cSChanwoo Choi { "ppmu-event3-"#name, PPMU_PMNCNT3 } 50f262f28cSChanwoo Choi 516b1355f9SKrzysztof Kozlowski static struct __exynos_ppmu_events { 52f262f28cSChanwoo Choi char *name; 53f262f28cSChanwoo Choi int id; 54f262f28cSChanwoo Choi } ppmu_events[] = { 55f262f28cSChanwoo Choi /* For Exynos3250, Exynos4 and Exynos5260 */ 56f262f28cSChanwoo Choi PPMU_EVENT(g3d), 57f262f28cSChanwoo Choi PPMU_EVENT(fsys), 58f262f28cSChanwoo Choi 59f262f28cSChanwoo Choi /* For Exynos4 SoCs and Exynos3250 */ 60f262f28cSChanwoo Choi PPMU_EVENT(dmc0), 61f262f28cSChanwoo Choi PPMU_EVENT(dmc1), 62f262f28cSChanwoo Choi PPMU_EVENT(cpu), 63f262f28cSChanwoo Choi PPMU_EVENT(rightbus), 64f262f28cSChanwoo Choi PPMU_EVENT(leftbus), 65f262f28cSChanwoo Choi PPMU_EVENT(lcd0), 66f262f28cSChanwoo Choi PPMU_EVENT(camif), 67f262f28cSChanwoo Choi 68f262f28cSChanwoo Choi /* Only for Exynos3250 and Exynos5260 */ 69f262f28cSChanwoo Choi PPMU_EVENT(mfc), 70f262f28cSChanwoo Choi 71f262f28cSChanwoo Choi /* Only for Exynos4 SoCs */ 72f262f28cSChanwoo Choi PPMU_EVENT(mfc-left), 73f262f28cSChanwoo Choi PPMU_EVENT(mfc-right), 74f262f28cSChanwoo Choi 75f262f28cSChanwoo Choi /* Only for Exynos5260 SoCs */ 76f262f28cSChanwoo Choi PPMU_EVENT(drex0-s0), 77f262f28cSChanwoo Choi PPMU_EVENT(drex0-s1), 78f262f28cSChanwoo Choi PPMU_EVENT(drex1-s0), 79f262f28cSChanwoo Choi PPMU_EVENT(drex1-s1), 80f262f28cSChanwoo Choi PPMU_EVENT(eagle), 81f262f28cSChanwoo Choi PPMU_EVENT(kfc), 82f262f28cSChanwoo Choi PPMU_EVENT(isp), 83f262f28cSChanwoo Choi PPMU_EVENT(fimc), 84f262f28cSChanwoo Choi PPMU_EVENT(gscl), 85f262f28cSChanwoo Choi PPMU_EVENT(mscl), 86f262f28cSChanwoo Choi PPMU_EVENT(fimd0x), 87f262f28cSChanwoo Choi PPMU_EVENT(fimd1x), 8877fe46a3SChanwoo Choi 8977fe46a3SChanwoo Choi /* Only for Exynos5433 SoCs */ 9077fe46a3SChanwoo Choi PPMU_EVENT(d0-cpu), 9177fe46a3SChanwoo Choi PPMU_EVENT(d0-general), 9277fe46a3SChanwoo Choi PPMU_EVENT(d0-rt), 9377fe46a3SChanwoo Choi PPMU_EVENT(d1-cpu), 9477fe46a3SChanwoo Choi PPMU_EVENT(d1-general), 9577fe46a3SChanwoo Choi PPMU_EVENT(d1-rt), 965f866963SLukasz Luba 975f866963SLukasz Luba /* For Exynos5422 SoC */ 985f866963SLukasz Luba PPMU_EVENT(dmc0_0), 995f866963SLukasz Luba PPMU_EVENT(dmc0_1), 1005f866963SLukasz Luba PPMU_EVENT(dmc1_0), 1015f866963SLukasz Luba PPMU_EVENT(dmc1_1), 102f262f28cSChanwoo Choi }; 103f262f28cSChanwoo Choi 104d4556f5eSArnd Bergmann static int __exynos_ppmu_find_ppmu_id(const char *edev_name) 105f262f28cSChanwoo Choi { 106f262f28cSChanwoo Choi int i; 107f262f28cSChanwoo Choi 108f262f28cSChanwoo Choi for (i = 0; i < ARRAY_SIZE(ppmu_events); i++) 109d4556f5eSArnd Bergmann if (!strcmp(edev_name, ppmu_events[i].name)) 110f262f28cSChanwoo Choi return ppmu_events[i].id; 111f262f28cSChanwoo Choi 112f262f28cSChanwoo Choi return -EINVAL; 113f262f28cSChanwoo Choi } 114f262f28cSChanwoo Choi 115d4556f5eSArnd Bergmann static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) 116d4556f5eSArnd Bergmann { 117d4556f5eSArnd Bergmann return __exynos_ppmu_find_ppmu_id(edev->desc->name); 118d4556f5eSArnd Bergmann } 119d4556f5eSArnd Bergmann 12077fe46a3SChanwoo Choi /* 12177fe46a3SChanwoo Choi * The devfreq-event ops structure for PPMU v1.1 12277fe46a3SChanwoo Choi */ 123f262f28cSChanwoo Choi static int exynos_ppmu_disable(struct devfreq_event_dev *edev) 124f262f28cSChanwoo Choi { 125f262f28cSChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 1262a3ea647SChanwoo Choi int ret; 127f262f28cSChanwoo Choi u32 pmnc; 128f262f28cSChanwoo Choi 129f262f28cSChanwoo Choi /* Disable all counters */ 1302a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_CNTENC, 1312a3ea647SChanwoo Choi PPMU_CCNT_MASK | 132f262f28cSChanwoo Choi PPMU_PMCNT0_MASK | 133f262f28cSChanwoo Choi PPMU_PMCNT1_MASK | 134f262f28cSChanwoo Choi PPMU_PMCNT2_MASK | 1352a3ea647SChanwoo Choi PPMU_PMCNT3_MASK); 1362a3ea647SChanwoo Choi if (ret < 0) 1372a3ea647SChanwoo Choi return ret; 138f262f28cSChanwoo Choi 139f262f28cSChanwoo Choi /* Disable PPMU */ 1402a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); 1412a3ea647SChanwoo Choi if (ret < 0) 1422a3ea647SChanwoo Choi return ret; 1432a3ea647SChanwoo Choi 144f262f28cSChanwoo Choi pmnc &= ~PPMU_PMNC_ENABLE_MASK; 1452a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); 1462a3ea647SChanwoo Choi if (ret < 0) 1472a3ea647SChanwoo Choi return ret; 148f262f28cSChanwoo Choi 149f262f28cSChanwoo Choi return 0; 150f262f28cSChanwoo Choi } 151f262f28cSChanwoo Choi 152f262f28cSChanwoo Choi static int exynos_ppmu_set_event(struct devfreq_event_dev *edev) 153f262f28cSChanwoo Choi { 154f262f28cSChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 155f262f28cSChanwoo Choi int id = exynos_ppmu_find_ppmu_id(edev); 1562a3ea647SChanwoo Choi int ret; 157f262f28cSChanwoo Choi u32 pmnc, cntens; 158f262f28cSChanwoo Choi 159f262f28cSChanwoo Choi if (id < 0) 160f262f28cSChanwoo Choi return id; 161f262f28cSChanwoo Choi 162f262f28cSChanwoo Choi /* Enable specific counter */ 1632a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_CNTENS, &cntens); 1642a3ea647SChanwoo Choi if (ret < 0) 1652a3ea647SChanwoo Choi return ret; 1662a3ea647SChanwoo Choi 167f262f28cSChanwoo Choi cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); 1682a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_CNTENS, cntens); 1692a3ea647SChanwoo Choi if (ret < 0) 1702a3ea647SChanwoo Choi return ret; 171f262f28cSChanwoo Choi 1721dd62c66SLukasz Luba /* Set the event of proper data type monitoring */ 1732a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_BEVTxSEL(id), 1741dd62c66SLukasz Luba edev->desc->event_type); 1752a3ea647SChanwoo Choi if (ret < 0) 1762a3ea647SChanwoo Choi return ret; 177f262f28cSChanwoo Choi 178f262f28cSChanwoo Choi /* Reset cycle counter/performance counter and enable PPMU */ 1792a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); 1802a3ea647SChanwoo Choi if (ret < 0) 1812a3ea647SChanwoo Choi return ret; 1822a3ea647SChanwoo Choi 183f262f28cSChanwoo Choi pmnc &= ~(PPMU_PMNC_ENABLE_MASK 184f262f28cSChanwoo Choi | PPMU_PMNC_COUNTER_RESET_MASK 185f262f28cSChanwoo Choi | PPMU_PMNC_CC_RESET_MASK); 186f262f28cSChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT); 187f262f28cSChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT); 188f262f28cSChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT); 1892a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); 1902a3ea647SChanwoo Choi if (ret < 0) 1912a3ea647SChanwoo Choi return ret; 192f262f28cSChanwoo Choi 193f262f28cSChanwoo Choi return 0; 194f262f28cSChanwoo Choi } 195f262f28cSChanwoo Choi 196f262f28cSChanwoo Choi static int exynos_ppmu_get_event(struct devfreq_event_dev *edev, 197f262f28cSChanwoo Choi struct devfreq_event_data *edata) 198f262f28cSChanwoo Choi { 199f262f28cSChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 200f262f28cSChanwoo Choi int id = exynos_ppmu_find_ppmu_id(edev); 2012a3ea647SChanwoo Choi unsigned int total_count, load_count; 2022a3ea647SChanwoo Choi unsigned int pmcnt3_high, pmcnt3_low; 2032a3ea647SChanwoo Choi unsigned int pmnc, cntenc; 2042a3ea647SChanwoo Choi int ret; 205f262f28cSChanwoo Choi 206f262f28cSChanwoo Choi if (id < 0) 207f262f28cSChanwoo Choi return -EINVAL; 208f262f28cSChanwoo Choi 209f262f28cSChanwoo Choi /* Disable PPMU */ 2102a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); 2112a3ea647SChanwoo Choi if (ret < 0) 2122a3ea647SChanwoo Choi return ret; 2132a3ea647SChanwoo Choi 214f262f28cSChanwoo Choi pmnc &= ~PPMU_PMNC_ENABLE_MASK; 2152a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); 2162a3ea647SChanwoo Choi if (ret < 0) 2172a3ea647SChanwoo Choi return ret; 218f262f28cSChanwoo Choi 219f262f28cSChanwoo Choi /* Read cycle count */ 2202a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_CCNT, &total_count); 2212a3ea647SChanwoo Choi if (ret < 0) 2222a3ea647SChanwoo Choi return ret; 2232a3ea647SChanwoo Choi edata->total_count = total_count; 224f262f28cSChanwoo Choi 225f262f28cSChanwoo Choi /* Read performance count */ 226f262f28cSChanwoo Choi switch (id) { 227f262f28cSChanwoo Choi case PPMU_PMNCNT0: 228f262f28cSChanwoo Choi case PPMU_PMNCNT1: 229f262f28cSChanwoo Choi case PPMU_PMNCNT2: 2302a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMNCT(id), &load_count); 2312a3ea647SChanwoo Choi if (ret < 0) 2322a3ea647SChanwoo Choi return ret; 2332a3ea647SChanwoo Choi edata->load_count = load_count; 234f262f28cSChanwoo Choi break; 235f262f28cSChanwoo Choi case PPMU_PMNCNT3: 2362a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMCNT3_HIGH, &pmcnt3_high); 2372a3ea647SChanwoo Choi if (ret < 0) 2382a3ea647SChanwoo Choi return ret; 2392a3ea647SChanwoo Choi 2402a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_PMCNT3_LOW, &pmcnt3_low); 2412a3ea647SChanwoo Choi if (ret < 0) 2422a3ea647SChanwoo Choi return ret; 2432a3ea647SChanwoo Choi 2442a3ea647SChanwoo Choi edata->load_count = ((pmcnt3_high << 8) | pmcnt3_low); 245f262f28cSChanwoo Choi break; 246f262f28cSChanwoo Choi default: 247f262f28cSChanwoo Choi return -EINVAL; 248f262f28cSChanwoo Choi } 249f262f28cSChanwoo Choi 250f262f28cSChanwoo Choi /* Disable specific counter */ 2512a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_CNTENC, &cntenc); 2522a3ea647SChanwoo Choi if (ret < 0) 2532a3ea647SChanwoo Choi return ret; 2542a3ea647SChanwoo Choi 255f262f28cSChanwoo Choi cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); 2562a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_CNTENC, cntenc); 2572a3ea647SChanwoo Choi if (ret < 0) 2582a3ea647SChanwoo Choi return ret; 259f262f28cSChanwoo Choi 260f262f28cSChanwoo Choi dev_dbg(&edev->dev, "%s (event: %ld/%ld)\n", edev->desc->name, 261f262f28cSChanwoo Choi edata->load_count, edata->total_count); 262f262f28cSChanwoo Choi 263f262f28cSChanwoo Choi return 0; 264f262f28cSChanwoo Choi } 265f262f28cSChanwoo Choi 2666f240fbcSChanwoo Choi static const struct devfreq_event_ops exynos_ppmu_ops = { 267f262f28cSChanwoo Choi .disable = exynos_ppmu_disable, 268f262f28cSChanwoo Choi .set_event = exynos_ppmu_set_event, 269f262f28cSChanwoo Choi .get_event = exynos_ppmu_get_event, 270f262f28cSChanwoo Choi }; 271f262f28cSChanwoo Choi 27277fe46a3SChanwoo Choi /* 27377fe46a3SChanwoo Choi * The devfreq-event ops structure for PPMU v2.0 27477fe46a3SChanwoo Choi */ 27577fe46a3SChanwoo Choi static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev) 27677fe46a3SChanwoo Choi { 27777fe46a3SChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 2782a3ea647SChanwoo Choi int ret; 27977fe46a3SChanwoo Choi u32 pmnc, clear; 28077fe46a3SChanwoo Choi 28177fe46a3SChanwoo Choi /* Disable all counters */ 28277fe46a3SChanwoo Choi clear = (PPMU_CCNT_MASK | PPMU_PMCNT0_MASK | PPMU_PMCNT1_MASK 28377fe46a3SChanwoo Choi | PPMU_PMCNT2_MASK | PPMU_PMCNT3_MASK); 2842a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_FLAG, clear); 2852a3ea647SChanwoo Choi if (ret < 0) 2862a3ea647SChanwoo Choi return ret; 28777fe46a3SChanwoo Choi 2882a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_INTENC, clear); 2892a3ea647SChanwoo Choi if (ret < 0) 2902a3ea647SChanwoo Choi return ret; 29177fe46a3SChanwoo Choi 2922a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CNTENC, clear); 2932a3ea647SChanwoo Choi if (ret < 0) 2942a3ea647SChanwoo Choi return ret; 2952a3ea647SChanwoo Choi 2962a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CNT_RESET, clear); 2972a3ea647SChanwoo Choi if (ret < 0) 2982a3ea647SChanwoo Choi return ret; 2992a3ea647SChanwoo Choi 3002a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG0, 0x0); 3012a3ea647SChanwoo Choi if (ret < 0) 3022a3ea647SChanwoo Choi return ret; 3032a3ea647SChanwoo Choi 3042a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG1, 0x0); 3052a3ea647SChanwoo Choi if (ret < 0) 3062a3ea647SChanwoo Choi return ret; 3072a3ea647SChanwoo Choi 3082a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG2, 0x0); 3092a3ea647SChanwoo Choi if (ret < 0) 3102a3ea647SChanwoo Choi return ret; 3112a3ea647SChanwoo Choi 3122a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CIG_RESULT, 0x0); 3132a3ea647SChanwoo Choi if (ret < 0) 3142a3ea647SChanwoo Choi return ret; 3152a3ea647SChanwoo Choi 3162a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CNT_AUTO, 0x0); 3172a3ea647SChanwoo Choi if (ret < 0) 3182a3ea647SChanwoo Choi return ret; 3192a3ea647SChanwoo Choi 3202a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CH_EV0_TYPE, 0x0); 3212a3ea647SChanwoo Choi if (ret < 0) 3222a3ea647SChanwoo Choi return ret; 3232a3ea647SChanwoo Choi 3242a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CH_EV1_TYPE, 0x0); 3252a3ea647SChanwoo Choi if (ret < 0) 3262a3ea647SChanwoo Choi return ret; 3272a3ea647SChanwoo Choi 3282a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CH_EV2_TYPE, 0x0); 3292a3ea647SChanwoo Choi if (ret < 0) 3302a3ea647SChanwoo Choi return ret; 3312a3ea647SChanwoo Choi 3322a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CH_EV3_TYPE, 0x0); 3332a3ea647SChanwoo Choi if (ret < 0) 3342a3ea647SChanwoo Choi return ret; 3352a3ea647SChanwoo Choi 3362a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_SM_ID_V, 0x0); 3372a3ea647SChanwoo Choi if (ret < 0) 3382a3ea647SChanwoo Choi return ret; 3392a3ea647SChanwoo Choi 3402a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_SM_ID_A, 0x0); 3412a3ea647SChanwoo Choi if (ret < 0) 3422a3ea647SChanwoo Choi return ret; 3432a3ea647SChanwoo Choi 3442a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_V, 0x0); 3452a3ea647SChanwoo Choi if (ret < 0) 3462a3ea647SChanwoo Choi return ret; 3472a3ea647SChanwoo Choi 3482a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_A, 0x0); 3492a3ea647SChanwoo Choi if (ret < 0) 3502a3ea647SChanwoo Choi return ret; 3512a3ea647SChanwoo Choi 3522a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_INTERRUPT_RESET, 0x0); 3532a3ea647SChanwoo Choi if (ret < 0) 3542a3ea647SChanwoo Choi return ret; 35577fe46a3SChanwoo Choi 35677fe46a3SChanwoo Choi /* Disable PPMU */ 3572a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); 3582a3ea647SChanwoo Choi if (ret < 0) 3592a3ea647SChanwoo Choi return ret; 3602a3ea647SChanwoo Choi 36177fe46a3SChanwoo Choi pmnc &= ~PPMU_PMNC_ENABLE_MASK; 3622a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); 3632a3ea647SChanwoo Choi if (ret < 0) 3642a3ea647SChanwoo Choi return ret; 36577fe46a3SChanwoo Choi 36677fe46a3SChanwoo Choi return 0; 36777fe46a3SChanwoo Choi } 36877fe46a3SChanwoo Choi 36977fe46a3SChanwoo Choi static int exynos_ppmu_v2_set_event(struct devfreq_event_dev *edev) 37077fe46a3SChanwoo Choi { 37177fe46a3SChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 3722a3ea647SChanwoo Choi unsigned int pmnc, cntens; 37377fe46a3SChanwoo Choi int id = exynos_ppmu_find_ppmu_id(edev); 3742a3ea647SChanwoo Choi int ret; 37577fe46a3SChanwoo Choi 37677fe46a3SChanwoo Choi /* Enable all counters */ 3772a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_CNTENS, &cntens); 3782a3ea647SChanwoo Choi if (ret < 0) 3792a3ea647SChanwoo Choi return ret; 3802a3ea647SChanwoo Choi 38177fe46a3SChanwoo Choi cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); 3822a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CNTENS, cntens); 3832a3ea647SChanwoo Choi if (ret < 0) 3842a3ea647SChanwoo Choi return ret; 38577fe46a3SChanwoo Choi 3861dd62c66SLukasz Luba /* Set the event of proper data type monitoring */ 3872a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CH_EVx_TYPE(id), 3881dd62c66SLukasz Luba edev->desc->event_type); 3892a3ea647SChanwoo Choi if (ret < 0) 3902a3ea647SChanwoo Choi return ret; 39177fe46a3SChanwoo Choi 39277fe46a3SChanwoo Choi /* Reset cycle counter/performance counter and enable PPMU */ 3932a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); 3942a3ea647SChanwoo Choi if (ret < 0) 3952a3ea647SChanwoo Choi return ret; 3962a3ea647SChanwoo Choi 39777fe46a3SChanwoo Choi pmnc &= ~(PPMU_PMNC_ENABLE_MASK 39877fe46a3SChanwoo Choi | PPMU_PMNC_COUNTER_RESET_MASK 39977fe46a3SChanwoo Choi | PPMU_PMNC_CC_RESET_MASK 40077fe46a3SChanwoo Choi | PPMU_PMNC_CC_DIVIDER_MASK 40177fe46a3SChanwoo Choi | PPMU_V2_PMNC_START_MODE_MASK); 40277fe46a3SChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT); 40377fe46a3SChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT); 40477fe46a3SChanwoo Choi pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT); 40577fe46a3SChanwoo Choi pmnc |= (PPMU_V2_MODE_MANUAL << PPMU_V2_PMNC_START_MODE_SHIFT); 4062a3ea647SChanwoo Choi 4072a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); 4082a3ea647SChanwoo Choi if (ret < 0) 4092a3ea647SChanwoo Choi return ret; 41077fe46a3SChanwoo Choi 41177fe46a3SChanwoo Choi return 0; 41277fe46a3SChanwoo Choi } 41377fe46a3SChanwoo Choi 41477fe46a3SChanwoo Choi static int exynos_ppmu_v2_get_event(struct devfreq_event_dev *edev, 41577fe46a3SChanwoo Choi struct devfreq_event_data *edata) 41677fe46a3SChanwoo Choi { 41777fe46a3SChanwoo Choi struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); 41877fe46a3SChanwoo Choi int id = exynos_ppmu_find_ppmu_id(edev); 4192a3ea647SChanwoo Choi int ret; 4202a3ea647SChanwoo Choi unsigned int pmnc, cntenc; 4212a3ea647SChanwoo Choi unsigned int pmcnt_high, pmcnt_low; 4222a3ea647SChanwoo Choi unsigned int total_count, count; 4232a3ea647SChanwoo Choi unsigned long load_count = 0; 42477fe46a3SChanwoo Choi 42577fe46a3SChanwoo Choi /* Disable PPMU */ 4262a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); 4272a3ea647SChanwoo Choi if (ret < 0) 4282a3ea647SChanwoo Choi return ret; 4292a3ea647SChanwoo Choi 43077fe46a3SChanwoo Choi pmnc &= ~PPMU_PMNC_ENABLE_MASK; 4312a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); 4322a3ea647SChanwoo Choi if (ret < 0) 4332a3ea647SChanwoo Choi return ret; 43477fe46a3SChanwoo Choi 43577fe46a3SChanwoo Choi /* Read cycle count and performance count */ 4362a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_CCNT, &total_count); 4372a3ea647SChanwoo Choi if (ret < 0) 4382a3ea647SChanwoo Choi return ret; 4392a3ea647SChanwoo Choi edata->total_count = total_count; 44077fe46a3SChanwoo Choi 44177fe46a3SChanwoo Choi switch (id) { 44277fe46a3SChanwoo Choi case PPMU_PMNCNT0: 44377fe46a3SChanwoo Choi case PPMU_PMNCNT1: 44477fe46a3SChanwoo Choi case PPMU_PMNCNT2: 4452a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMNCT(id), &count); 4462a3ea647SChanwoo Choi if (ret < 0) 4472a3ea647SChanwoo Choi return ret; 4482a3ea647SChanwoo Choi load_count = count; 44977fe46a3SChanwoo Choi break; 45077fe46a3SChanwoo Choi case PPMU_PMNCNT3: 4512a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_HIGH, 4522a3ea647SChanwoo Choi &pmcnt_high); 4532a3ea647SChanwoo Choi if (ret < 0) 4542a3ea647SChanwoo Choi return ret; 4552a3ea647SChanwoo Choi 4562a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_LOW, &pmcnt_low); 4572a3ea647SChanwoo Choi if (ret < 0) 4582a3ea647SChanwoo Choi return ret; 4592a3ea647SChanwoo Choi 4602a3ea647SChanwoo Choi load_count = ((u64)((pmcnt_high & 0xff)) << 32)+ (u64)pmcnt_low; 46177fe46a3SChanwoo Choi break; 46277fe46a3SChanwoo Choi } 46377fe46a3SChanwoo Choi edata->load_count = load_count; 46477fe46a3SChanwoo Choi 46577fe46a3SChanwoo Choi /* Disable all counters */ 4662a3ea647SChanwoo Choi ret = regmap_read(info->regmap, PPMU_V2_CNTENC, &cntenc); 4672a3ea647SChanwoo Choi if (ret < 0) 4682a3ea647SChanwoo Choi return 0; 4692a3ea647SChanwoo Choi 47077fe46a3SChanwoo Choi cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); 4712a3ea647SChanwoo Choi ret = regmap_write(info->regmap, PPMU_V2_CNTENC, cntenc); 4722a3ea647SChanwoo Choi if (ret < 0) 4732a3ea647SChanwoo Choi return ret; 47477fe46a3SChanwoo Choi 47577fe46a3SChanwoo Choi dev_dbg(&edev->dev, "%25s (load: %ld / %ld)\n", edev->desc->name, 47677fe46a3SChanwoo Choi edata->load_count, edata->total_count); 47777fe46a3SChanwoo Choi return 0; 47877fe46a3SChanwoo Choi } 47977fe46a3SChanwoo Choi 48077fe46a3SChanwoo Choi static const struct devfreq_event_ops exynos_ppmu_v2_ops = { 48177fe46a3SChanwoo Choi .disable = exynos_ppmu_v2_disable, 48277fe46a3SChanwoo Choi .set_event = exynos_ppmu_v2_set_event, 48377fe46a3SChanwoo Choi .get_event = exynos_ppmu_v2_get_event, 48477fe46a3SChanwoo Choi }; 48577fe46a3SChanwoo Choi 48677fe46a3SChanwoo Choi static const struct of_device_id exynos_ppmu_id_match[] = { 48777fe46a3SChanwoo Choi { 48877fe46a3SChanwoo Choi .compatible = "samsung,exynos-ppmu", 4890ae9c321SLukasz Luba .data = (void *)EXYNOS_TYPE_PPMU, 49077fe46a3SChanwoo Choi }, { 49177fe46a3SChanwoo Choi .compatible = "samsung,exynos-ppmu-v2", 4920ae9c321SLukasz Luba .data = (void *)EXYNOS_TYPE_PPMU_V2, 49377fe46a3SChanwoo Choi }, 49477fe46a3SChanwoo Choi { /* sentinel */ }, 49577fe46a3SChanwoo Choi }; 49629e477f2SJavier Martinez Canillas MODULE_DEVICE_TABLE(of, exynos_ppmu_id_match); 49777fe46a3SChanwoo Choi 498f262f28cSChanwoo Choi static int of_get_devfreq_events(struct device_node *np, 499f262f28cSChanwoo Choi struct exynos_ppmu *info) 500f262f28cSChanwoo Choi { 501f262f28cSChanwoo Choi struct devfreq_event_desc *desc; 502f262f28cSChanwoo Choi struct device *dev = info->dev; 503f262f28cSChanwoo Choi struct device_node *events_np, *node; 504f262f28cSChanwoo Choi int i, j, count; 5050ae9c321SLukasz Luba const struct of_device_id *of_id; 5061dd62c66SLukasz Luba int ret; 507f262f28cSChanwoo Choi 508f262f28cSChanwoo Choi events_np = of_get_child_by_name(np, "events"); 509f262f28cSChanwoo Choi if (!events_np) { 510f262f28cSChanwoo Choi dev_err(dev, 511f262f28cSChanwoo Choi "failed to get child node of devfreq-event devices\n"); 512f262f28cSChanwoo Choi return -EINVAL; 513f262f28cSChanwoo Choi } 514f262f28cSChanwoo Choi 515f262f28cSChanwoo Choi count = of_get_child_count(events_np); 516a86854d0SKees Cook desc = devm_kcalloc(dev, count, sizeof(*desc), GFP_KERNEL); 517f262f28cSChanwoo Choi if (!desc) 518f262f28cSChanwoo Choi return -ENOMEM; 519f262f28cSChanwoo Choi info->num_events = count; 520f262f28cSChanwoo Choi 5210ae9c321SLukasz Luba of_id = of_match_device(exynos_ppmu_id_match, dev); 5220ae9c321SLukasz Luba if (of_id) 5230ae9c321SLukasz Luba info->ppmu_type = (enum exynos_ppmu_type)of_id->data; 5240ae9c321SLukasz Luba else 5250ae9c321SLukasz Luba return -EINVAL; 5260ae9c321SLukasz Luba 527f262f28cSChanwoo Choi j = 0; 528f262f28cSChanwoo Choi for_each_child_of_node(events_np, node) { 529f262f28cSChanwoo Choi for (i = 0; i < ARRAY_SIZE(ppmu_events); i++) { 530f262f28cSChanwoo Choi if (!ppmu_events[i].name) 531f262f28cSChanwoo Choi continue; 532f262f28cSChanwoo Choi 5330d00a239SRob Herring if (of_node_name_eq(node, ppmu_events[i].name)) 534f262f28cSChanwoo Choi break; 535f262f28cSChanwoo Choi } 536f262f28cSChanwoo Choi 537f262f28cSChanwoo Choi if (i == ARRAY_SIZE(ppmu_events)) { 538f262f28cSChanwoo Choi dev_warn(dev, 539f037eb8cSRob Herring "don't know how to configure events : %pOFn\n", 540f037eb8cSRob Herring node); 541f262f28cSChanwoo Choi continue; 542f262f28cSChanwoo Choi } 543f262f28cSChanwoo Choi 5440ae9c321SLukasz Luba switch (info->ppmu_type) { 5450ae9c321SLukasz Luba case EXYNOS_TYPE_PPMU: 5460ae9c321SLukasz Luba desc[j].ops = &exynos_ppmu_ops; 5470ae9c321SLukasz Luba break; 5480ae9c321SLukasz Luba case EXYNOS_TYPE_PPMU_V2: 5490ae9c321SLukasz Luba desc[j].ops = &exynos_ppmu_v2_ops; 5500ae9c321SLukasz Luba break; 5510ae9c321SLukasz Luba } 5520ae9c321SLukasz Luba 553f262f28cSChanwoo Choi desc[j].driver_data = info; 554f262f28cSChanwoo Choi 555f262f28cSChanwoo Choi of_property_read_string(node, "event-name", &desc[j].name); 5561dd62c66SLukasz Luba ret = of_property_read_u32(node, "event-data-type", 5571dd62c66SLukasz Luba &desc[j].event_type); 5581dd62c66SLukasz Luba if (ret) { 5591dd62c66SLukasz Luba /* Set the event of proper data type counting. 5601dd62c66SLukasz Luba * Check if the data type has been defined in DT, 5611dd62c66SLukasz Luba * use default if not. 5621dd62c66SLukasz Luba */ 5631dd62c66SLukasz Luba if (info->ppmu_type == EXYNOS_TYPE_PPMU_V2) { 5641dd62c66SLukasz Luba int id; 5651dd62c66SLukasz Luba /* Not all registers take the same value for 5661dd62c66SLukasz Luba * read+write data count. 5671dd62c66SLukasz Luba */ 568d4556f5eSArnd Bergmann id = __exynos_ppmu_find_ppmu_id(desc[j].name); 5691dd62c66SLukasz Luba 5701dd62c66SLukasz Luba switch (id) { 5711dd62c66SLukasz Luba case PPMU_PMNCNT0: 5721dd62c66SLukasz Luba case PPMU_PMNCNT1: 5731dd62c66SLukasz Luba case PPMU_PMNCNT2: 5741dd62c66SLukasz Luba desc[j].event_type = PPMU_V2_RO_DATA_CNT 5751dd62c66SLukasz Luba | PPMU_V2_WO_DATA_CNT; 5761dd62c66SLukasz Luba break; 5771dd62c66SLukasz Luba case PPMU_PMNCNT3: 5781dd62c66SLukasz Luba desc[j].event_type = 5791dd62c66SLukasz Luba PPMU_V2_EVT3_RW_DATA_CNT; 5801dd62c66SLukasz Luba break; 5811dd62c66SLukasz Luba } 5821dd62c66SLukasz Luba } else { 5831dd62c66SLukasz Luba desc[j].event_type = PPMU_RO_DATA_CNT | 5841dd62c66SLukasz Luba PPMU_WO_DATA_CNT; 5851dd62c66SLukasz Luba } 5861dd62c66SLukasz Luba } 587f262f28cSChanwoo Choi 588f262f28cSChanwoo Choi j++; 589f262f28cSChanwoo Choi } 590f262f28cSChanwoo Choi info->desc = desc; 591f262f28cSChanwoo Choi 592f262f28cSChanwoo Choi of_node_put(events_np); 593f262f28cSChanwoo Choi 594f262f28cSChanwoo Choi return 0; 595f262f28cSChanwoo Choi } 596f262f28cSChanwoo Choi 5972a3ea647SChanwoo Choi static struct regmap_config exynos_ppmu_regmap_config = { 5982a3ea647SChanwoo Choi .reg_bits = 32, 5992a3ea647SChanwoo Choi .val_bits = 32, 6002a3ea647SChanwoo Choi .reg_stride = 4, 6012a3ea647SChanwoo Choi }; 6022a3ea647SChanwoo Choi 6032a3ea647SChanwoo Choi static int exynos_ppmu_parse_dt(struct platform_device *pdev, 6042a3ea647SChanwoo Choi struct exynos_ppmu *info) 605f262f28cSChanwoo Choi { 606f262f28cSChanwoo Choi struct device *dev = info->dev; 607f262f28cSChanwoo Choi struct device_node *np = dev->of_node; 6082a3ea647SChanwoo Choi struct resource *res; 6092a3ea647SChanwoo Choi void __iomem *base; 610f262f28cSChanwoo Choi int ret = 0; 611f262f28cSChanwoo Choi 612f262f28cSChanwoo Choi if (!np) { 613f262f28cSChanwoo Choi dev_err(dev, "failed to find devicetree node\n"); 614f262f28cSChanwoo Choi return -EINVAL; 615f262f28cSChanwoo Choi } 616f262f28cSChanwoo Choi 617f262f28cSChanwoo Choi /* Maps the memory mapped IO to control PPMU register */ 6182a3ea647SChanwoo Choi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 6192a3ea647SChanwoo Choi base = devm_ioremap_resource(dev, res); 6202a3ea647SChanwoo Choi if (IS_ERR(base)) 6212a3ea647SChanwoo Choi return PTR_ERR(base); 6222a3ea647SChanwoo Choi 6232a3ea647SChanwoo Choi exynos_ppmu_regmap_config.max_register = resource_size(res) - 4; 6242a3ea647SChanwoo Choi info->regmap = devm_regmap_init_mmio(dev, base, 6252a3ea647SChanwoo Choi &exynos_ppmu_regmap_config); 6262a3ea647SChanwoo Choi if (IS_ERR(info->regmap)) { 6272a3ea647SChanwoo Choi dev_err(dev, "failed to initialize regmap\n"); 6282a3ea647SChanwoo Choi return PTR_ERR(info->regmap); 629f262f28cSChanwoo Choi } 630f262f28cSChanwoo Choi 631f262f28cSChanwoo Choi info->ppmu.clk = devm_clk_get(dev, "ppmu"); 632f262f28cSChanwoo Choi if (IS_ERR(info->ppmu.clk)) { 633f262f28cSChanwoo Choi info->ppmu.clk = NULL; 634f262f28cSChanwoo Choi dev_warn(dev, "cannot get PPMU clock\n"); 635f262f28cSChanwoo Choi } 636f262f28cSChanwoo Choi 637f262f28cSChanwoo Choi ret = of_get_devfreq_events(np, info); 638f262f28cSChanwoo Choi if (ret < 0) { 639f262f28cSChanwoo Choi dev_err(dev, "failed to parse exynos ppmu dt node\n"); 6402a3ea647SChanwoo Choi return ret; 641f262f28cSChanwoo Choi } 642f262f28cSChanwoo Choi 643f262f28cSChanwoo Choi return 0; 644f262f28cSChanwoo Choi } 645f262f28cSChanwoo Choi 646f262f28cSChanwoo Choi static int exynos_ppmu_probe(struct platform_device *pdev) 647f262f28cSChanwoo Choi { 648f262f28cSChanwoo Choi struct exynos_ppmu *info; 649f262f28cSChanwoo Choi struct devfreq_event_dev **edev; 650f262f28cSChanwoo Choi struct devfreq_event_desc *desc; 651f262f28cSChanwoo Choi int i, ret = 0, size; 652f262f28cSChanwoo Choi 653f262f28cSChanwoo Choi info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 654f262f28cSChanwoo Choi if (!info) 655f262f28cSChanwoo Choi return -ENOMEM; 656f262f28cSChanwoo Choi 657f262f28cSChanwoo Choi info->dev = &pdev->dev; 658f262f28cSChanwoo Choi 659f262f28cSChanwoo Choi /* Parse dt data to get resource */ 6602a3ea647SChanwoo Choi ret = exynos_ppmu_parse_dt(pdev, info); 661f262f28cSChanwoo Choi if (ret < 0) { 662f262f28cSChanwoo Choi dev_err(&pdev->dev, 663f262f28cSChanwoo Choi "failed to parse devicetree for resource\n"); 664f262f28cSChanwoo Choi return ret; 665f262f28cSChanwoo Choi } 666f262f28cSChanwoo Choi desc = info->desc; 667f262f28cSChanwoo Choi 668f262f28cSChanwoo Choi size = sizeof(struct devfreq_event_dev *) * info->num_events; 669f262f28cSChanwoo Choi info->edev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); 67012ba2c65SMarkus Elfring if (!info->edev) 6712a3ea647SChanwoo Choi return -ENOMEM; 67212ba2c65SMarkus Elfring 673f262f28cSChanwoo Choi edev = info->edev; 674f262f28cSChanwoo Choi platform_set_drvdata(pdev, info); 675f262f28cSChanwoo Choi 676f262f28cSChanwoo Choi for (i = 0; i < info->num_events; i++) { 677f262f28cSChanwoo Choi edev[i] = devm_devfreq_event_add_edev(&pdev->dev, &desc[i]); 67804a695edSDan Carpenter if (IS_ERR(edev[i])) { 679f262f28cSChanwoo Choi dev_err(&pdev->dev, 680f262f28cSChanwoo Choi "failed to add devfreq-event device\n"); 6812a3ea647SChanwoo Choi return PTR_ERR(edev[i]); 682f262f28cSChanwoo Choi } 683b0d75c08SChanwoo Choi 684b0d75c08SChanwoo Choi pr_info("exynos-ppmu: new PPMU device registered %s (%s)\n", 685b0d75c08SChanwoo Choi dev_name(&pdev->dev), desc[i].name); 686f262f28cSChanwoo Choi } 687f262f28cSChanwoo Choi 68897a6ba5bSArvind Yadav ret = clk_prepare_enable(info->ppmu.clk); 68997a6ba5bSArvind Yadav if (ret) { 69097a6ba5bSArvind Yadav dev_err(&pdev->dev, "failed to prepare ppmu clock\n"); 69197a6ba5bSArvind Yadav return ret; 69297a6ba5bSArvind Yadav } 693f262f28cSChanwoo Choi 694f262f28cSChanwoo Choi return 0; 695f262f28cSChanwoo Choi } 696f262f28cSChanwoo Choi 697f262f28cSChanwoo Choi static int exynos_ppmu_remove(struct platform_device *pdev) 698f262f28cSChanwoo Choi { 699f262f28cSChanwoo Choi struct exynos_ppmu *info = platform_get_drvdata(pdev); 700f262f28cSChanwoo Choi 701f262f28cSChanwoo Choi clk_disable_unprepare(info->ppmu.clk); 702f262f28cSChanwoo Choi 703f262f28cSChanwoo Choi return 0; 704f262f28cSChanwoo Choi } 705f262f28cSChanwoo Choi 706f262f28cSChanwoo Choi static struct platform_driver exynos_ppmu_driver = { 707f262f28cSChanwoo Choi .probe = exynos_ppmu_probe, 708f262f28cSChanwoo Choi .remove = exynos_ppmu_remove, 709f262f28cSChanwoo Choi .driver = { 710f262f28cSChanwoo Choi .name = "exynos-ppmu", 711f262f28cSChanwoo Choi .of_match_table = exynos_ppmu_id_match, 712f262f28cSChanwoo Choi }, 713f262f28cSChanwoo Choi }; 714f262f28cSChanwoo Choi module_platform_driver(exynos_ppmu_driver); 715f262f28cSChanwoo Choi 716f262f28cSChanwoo Choi MODULE_DESCRIPTION("Exynos PPMU(Platform Performance Monitoring Unit) driver"); 717f262f28cSChanwoo Choi MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>"); 718f262f28cSChanwoo Choi MODULE_LICENSE("GPL"); 719