121e9f767SBen Widawsky // SPDX-License-Identifier: GPL-2.0-only 221e9f767SBen Widawsky /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 34faf31b4SDan Williams #include <linux/io-64-nonatomic-lo-hi.h> 4229e8828SBen Widawsky #include <linux/moduleparam.h> 521e9f767SBen Widawsky #include <linux/module.h> 6229e8828SBen Widawsky #include <linux/delay.h> 721e9f767SBen Widawsky #include <linux/sizes.h> 821e9f767SBen Widawsky #include <linux/mutex.h> 930af9729SIra Weiny #include <linux/list.h> 1021e9f767SBen Widawsky #include <linux/pci.h> 112905cb52SDan Williams #include <linux/aer.h> 1221e9f767SBen Widawsky #include <linux/io.h> 135161a55cSBen Widawsky #include "cxlmem.h" 14af9cae9fSDan Williams #include "cxlpci.h" 1521e9f767SBen Widawsky #include "cxl.h" 1621e9f767SBen Widawsky 1721e9f767SBen Widawsky /** 1821e9f767SBen Widawsky * DOC: cxl pci 1921e9f767SBen Widawsky * 2021e9f767SBen Widawsky * This implements the PCI exclusive functionality for a CXL device as it is 2121e9f767SBen Widawsky * defined by the Compute Express Link specification. CXL devices may surface 22ed97afb5SBen Widawsky * certain functionality even if it isn't CXL enabled. While this driver is 23ed97afb5SBen Widawsky * focused around the PCI specific aspects of a CXL device, it binds to the 24ed97afb5SBen Widawsky * specific CXL memory device class code, and therefore the implementation of 25ed97afb5SBen Widawsky * cxl_pci is focused around CXL memory devices. 2621e9f767SBen Widawsky * 2721e9f767SBen Widawsky * The driver has several responsibilities, mainly: 2821e9f767SBen Widawsky * - Create the memX device and register on the CXL bus. 2921e9f767SBen Widawsky * - Enumerate device's register interface and map them. 30ed97afb5SBen Widawsky * - Registers nvdimm bridge device with cxl_core. 31ed97afb5SBen Widawsky * - Registers a CXL mailbox with cxl_core. 3221e9f767SBen Widawsky */ 3321e9f767SBen Widawsky 345e2411aeSIra Weiny #define cxl_doorbell_busy(cxlds) \ 355e2411aeSIra Weiny (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 3621e9f767SBen Widawsky CXLDEV_MBOX_CTRL_DOORBELL) 3721e9f767SBen Widawsky 3821e9f767SBen Widawsky /* CXL 2.0 - 8.2.8.4 */ 3921e9f767SBen Widawsky #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 4021e9f767SBen Widawsky 41229e8828SBen Widawsky /* 42229e8828SBen Widawsky * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 43229e8828SBen Widawsky * dictate how long to wait for the mailbox to become ready. The new 44229e8828SBen Widawsky * field allows the device to tell software the amount of time to wait 45229e8828SBen Widawsky * before mailbox ready. This field per the spec theoretically allows 46229e8828SBen Widawsky * for up to 255 seconds. 255 seconds is unreasonably long, its longer 47229e8828SBen Widawsky * than the maximum SATA port link recovery wait. Default to 60 seconds 48229e8828SBen Widawsky * until someone builds a CXL device that needs more time in practice. 49229e8828SBen Widawsky */ 50229e8828SBen Widawsky static unsigned short mbox_ready_timeout = 60; 51229e8828SBen Widawsky module_param(mbox_ready_timeout, ushort, 0644); 522e4ba0ecSDan Williams MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 53229e8828SBen Widawsky 545e2411aeSIra Weiny static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 5521e9f767SBen Widawsky { 5621e9f767SBen Widawsky const unsigned long start = jiffies; 5721e9f767SBen Widawsky unsigned long end = start; 5821e9f767SBen Widawsky 595e2411aeSIra Weiny while (cxl_doorbell_busy(cxlds)) { 6021e9f767SBen Widawsky end = jiffies; 6121e9f767SBen Widawsky 6221e9f767SBen Widawsky if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 6321e9f767SBen Widawsky /* Check again in case preempted before timeout test */ 645e2411aeSIra Weiny if (!cxl_doorbell_busy(cxlds)) 6521e9f767SBen Widawsky break; 6621e9f767SBen Widawsky return -ETIMEDOUT; 6721e9f767SBen Widawsky } 6821e9f767SBen Widawsky cpu_relax(); 6921e9f767SBen Widawsky } 7021e9f767SBen Widawsky 715e2411aeSIra Weiny dev_dbg(cxlds->dev, "Doorbell wait took %dms", 7221e9f767SBen Widawsky jiffies_to_msecs(end) - jiffies_to_msecs(start)); 7321e9f767SBen Widawsky return 0; 7421e9f767SBen Widawsky } 7521e9f767SBen Widawsky 764f195ee7SDan Williams #define cxl_err(dev, status, msg) \ 774f195ee7SDan Williams dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 784f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 794f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8021e9f767SBen Widawsky 814f195ee7SDan Williams #define cxl_cmd_err(dev, cmd, status, msg) \ 824f195ee7SDan Williams dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 834f195ee7SDan Williams (cmd)->opcode, \ 844f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 854f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8621e9f767SBen Widawsky 879f7a320dSDavidlohr Bueso struct cxl_dev_id { 889f7a320dSDavidlohr Bueso struct cxl_dev_state *cxlds; 899f7a320dSDavidlohr Bueso }; 909f7a320dSDavidlohr Bueso 919f7a320dSDavidlohr Bueso static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 929f7a320dSDavidlohr Bueso irq_handler_t handler, irq_handler_t thread_fn) 939f7a320dSDavidlohr Bueso { 949f7a320dSDavidlohr Bueso struct device *dev = cxlds->dev; 959f7a320dSDavidlohr Bueso struct cxl_dev_id *dev_id; 969f7a320dSDavidlohr Bueso 979f7a320dSDavidlohr Bueso /* dev_id must be globally unique and must contain the cxlds */ 989f7a320dSDavidlohr Bueso dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 999f7a320dSDavidlohr Bueso if (!dev_id) 1009f7a320dSDavidlohr Bueso return -ENOMEM; 1019f7a320dSDavidlohr Bueso dev_id->cxlds = cxlds; 1029f7a320dSDavidlohr Bueso 1039f7a320dSDavidlohr Bueso return devm_request_threaded_irq(dev, irq, handler, thread_fn, 1049f7a320dSDavidlohr Bueso IRQF_SHARED | IRQF_ONESHOT, 1059f7a320dSDavidlohr Bueso NULL, dev_id); 1069f7a320dSDavidlohr Bueso } 1079f7a320dSDavidlohr Bueso 108*ccadf131SDavidlohr Bueso static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 109*ccadf131SDavidlohr Bueso { 110*ccadf131SDavidlohr Bueso u64 reg; 111*ccadf131SDavidlohr Bueso 112*ccadf131SDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 113*ccadf131SDavidlohr Bueso return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 114*ccadf131SDavidlohr Bueso } 115*ccadf131SDavidlohr Bueso 116*ccadf131SDavidlohr Bueso static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 117*ccadf131SDavidlohr Bueso { 118*ccadf131SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 119*ccadf131SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 120*ccadf131SDavidlohr Bueso 121*ccadf131SDavidlohr Bueso /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 122*ccadf131SDavidlohr Bueso if (cxl_mbox_background_complete(cxlds)) 123*ccadf131SDavidlohr Bueso rcuwait_wake_up(&cxlds->mbox_wait); 124*ccadf131SDavidlohr Bueso 125*ccadf131SDavidlohr Bueso return IRQ_HANDLED; 126*ccadf131SDavidlohr Bueso } 127*ccadf131SDavidlohr Bueso 12821e9f767SBen Widawsky /** 129ed97afb5SBen Widawsky * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 1305e2411aeSIra Weiny * @cxlds: The device state to communicate with. 13121e9f767SBen Widawsky * @mbox_cmd: Command to send to the memory device. 13221e9f767SBen Widawsky * 13321e9f767SBen Widawsky * Context: Any context. Expects mbox_mutex to be held. 13421e9f767SBen Widawsky * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 13521e9f767SBen Widawsky * Caller should check the return code in @mbox_cmd to make sure it 13621e9f767SBen Widawsky * succeeded. 13721e9f767SBen Widawsky * 13821e9f767SBen Widawsky * This is a generic form of the CXL mailbox send command thus only using the 13921e9f767SBen Widawsky * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 14021e9f767SBen Widawsky * devices, and perhaps other types of CXL devices may have further information 14121e9f767SBen Widawsky * available upon error conditions. Driver facilities wishing to send mailbox 14221e9f767SBen Widawsky * commands should use the wrapper command. 14321e9f767SBen Widawsky * 14421e9f767SBen Widawsky * The CXL spec allows for up to two mailboxes. The intention is for the primary 14521e9f767SBen Widawsky * mailbox to be OS controlled and the secondary mailbox to be used by system 14621e9f767SBen Widawsky * firmware. This allows the OS and firmware to communicate with the device and 14721e9f767SBen Widawsky * not need to coordinate with each other. The driver only uses the primary 14821e9f767SBen Widawsky * mailbox. 14921e9f767SBen Widawsky */ 1505e2411aeSIra Weiny static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds, 151b64955a9SDan Williams struct cxl_mbox_cmd *mbox_cmd) 15221e9f767SBen Widawsky { 1535e2411aeSIra Weiny void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 1545e2411aeSIra Weiny struct device *dev = cxlds->dev; 15521e9f767SBen Widawsky u64 cmd_reg, status_reg; 15621e9f767SBen Widawsky size_t out_len; 15721e9f767SBen Widawsky int rc; 15821e9f767SBen Widawsky 1595e2411aeSIra Weiny lockdep_assert_held(&cxlds->mbox_mutex); 16021e9f767SBen Widawsky 16121e9f767SBen Widawsky /* 16221e9f767SBen Widawsky * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 16321e9f767SBen Widawsky * 1. Caller reads MB Control Register to verify doorbell is clear 16421e9f767SBen Widawsky * 2. Caller writes Command Register 16521e9f767SBen Widawsky * 3. Caller writes Command Payload Registers if input payload is non-empty 16621e9f767SBen Widawsky * 4. Caller writes MB Control Register to set doorbell 16721e9f767SBen Widawsky * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 16821e9f767SBen Widawsky * 6. Caller reads MB Status Register to fetch Return code 16921e9f767SBen Widawsky * 7. If command successful, Caller reads Command Register to get Payload Length 17021e9f767SBen Widawsky * 8. If output payload is non-empty, host reads Command Payload Registers 17121e9f767SBen Widawsky * 17221e9f767SBen Widawsky * Hardware is free to do whatever it wants before the doorbell is rung, 17321e9f767SBen Widawsky * and isn't allowed to change anything after it clears the doorbell. As 17421e9f767SBen Widawsky * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 17521e9f767SBen Widawsky * also happen in any order (though some orders might not make sense). 17621e9f767SBen Widawsky */ 17721e9f767SBen Widawsky 17821e9f767SBen Widawsky /* #1 */ 1795e2411aeSIra Weiny if (cxl_doorbell_busy(cxlds)) { 1804f195ee7SDan Williams u64 md_status = 1814f195ee7SDan Williams readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 1824f195ee7SDan Williams 1834f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 1844f195ee7SDan Williams "mailbox queue busy"); 18521e9f767SBen Widawsky return -EBUSY; 18621e9f767SBen Widawsky } 18721e9f767SBen Widawsky 18821e9f767SBen Widawsky cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 18921e9f767SBen Widawsky mbox_cmd->opcode); 19021e9f767SBen Widawsky if (mbox_cmd->size_in) { 19121e9f767SBen Widawsky if (WARN_ON(!mbox_cmd->payload_in)) 19221e9f767SBen Widawsky return -EINVAL; 19321e9f767SBen Widawsky 19421e9f767SBen Widawsky cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 19521e9f767SBen Widawsky mbox_cmd->size_in); 19621e9f767SBen Widawsky memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 19721e9f767SBen Widawsky } 19821e9f767SBen Widawsky 19921e9f767SBen Widawsky /* #2, #3 */ 2005e2411aeSIra Weiny writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 20121e9f767SBen Widawsky 20221e9f767SBen Widawsky /* #4 */ 203852db33cSRobert Richter dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 20421e9f767SBen Widawsky writel(CXLDEV_MBOX_CTRL_DOORBELL, 2055e2411aeSIra Weiny cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 20621e9f767SBen Widawsky 20721e9f767SBen Widawsky /* #5 */ 2085e2411aeSIra Weiny rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 20921e9f767SBen Widawsky if (rc == -ETIMEDOUT) { 2104f195ee7SDan Williams u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2114f195ee7SDan Williams 2124f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 21321e9f767SBen Widawsky return rc; 21421e9f767SBen Widawsky } 21521e9f767SBen Widawsky 21621e9f767SBen Widawsky /* #6 */ 2175e2411aeSIra Weiny status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 21821e9f767SBen Widawsky mbox_cmd->return_code = 21921e9f767SBen Widawsky FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 22021e9f767SBen Widawsky 221*ccadf131SDavidlohr Bueso /* 222*ccadf131SDavidlohr Bueso * Handle the background command in a synchronous manner. 223*ccadf131SDavidlohr Bueso * 224*ccadf131SDavidlohr Bueso * All other mailbox commands will serialize/queue on the mbox_mutex, 225*ccadf131SDavidlohr Bueso * which we currently hold. Furthermore this also guarantees that 226*ccadf131SDavidlohr Bueso * cxl_mbox_background_complete() checks are safe amongst each other, 227*ccadf131SDavidlohr Bueso * in that no new bg operation can occur in between. 228*ccadf131SDavidlohr Bueso * 229*ccadf131SDavidlohr Bueso * Background operations are timesliced in accordance with the nature 230*ccadf131SDavidlohr Bueso * of the command. In the event of timeout, the mailbox state is 231*ccadf131SDavidlohr Bueso * indeterminate until the next successful command submission and the 232*ccadf131SDavidlohr Bueso * driver can get back in sync with the hardware state. 233*ccadf131SDavidlohr Bueso */ 234*ccadf131SDavidlohr Bueso if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 235*ccadf131SDavidlohr Bueso u64 bg_status_reg; 236*ccadf131SDavidlohr Bueso int i, timeout = mbox_cmd->poll_interval_ms; 237*ccadf131SDavidlohr Bueso 238*ccadf131SDavidlohr Bueso dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 239*ccadf131SDavidlohr Bueso mbox_cmd->opcode); 240*ccadf131SDavidlohr Bueso 241*ccadf131SDavidlohr Bueso for (i = 0; i < mbox_cmd->poll_count; i++) { 242*ccadf131SDavidlohr Bueso if (rcuwait_wait_event_timeout(&cxlds->mbox_wait, 243*ccadf131SDavidlohr Bueso cxl_mbox_background_complete(cxlds), 244*ccadf131SDavidlohr Bueso TASK_UNINTERRUPTIBLE, 245*ccadf131SDavidlohr Bueso msecs_to_jiffies(timeout)) > 0) 246*ccadf131SDavidlohr Bueso break; 247*ccadf131SDavidlohr Bueso } 248*ccadf131SDavidlohr Bueso 249*ccadf131SDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) { 250*ccadf131SDavidlohr Bueso dev_err(dev, "timeout waiting for background (%d ms)\n", 251*ccadf131SDavidlohr Bueso timeout * mbox_cmd->poll_count); 252*ccadf131SDavidlohr Bueso return -ETIMEDOUT; 253*ccadf131SDavidlohr Bueso } 254*ccadf131SDavidlohr Bueso 255*ccadf131SDavidlohr Bueso bg_status_reg = readq(cxlds->regs.mbox + 256*ccadf131SDavidlohr Bueso CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 257*ccadf131SDavidlohr Bueso mbox_cmd->return_code = 258*ccadf131SDavidlohr Bueso FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 259*ccadf131SDavidlohr Bueso bg_status_reg); 260*ccadf131SDavidlohr Bueso dev_dbg(dev, 261*ccadf131SDavidlohr Bueso "Mailbox background operation (0x%04x) completed\n", 262*ccadf131SDavidlohr Bueso mbox_cmd->opcode); 263*ccadf131SDavidlohr Bueso } 264*ccadf131SDavidlohr Bueso 26592fcc1abSDavidlohr Bueso if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 266c43e036dSDavidlohr Bueso dev_dbg(dev, "Mailbox operation had an error: %s\n", 267c43e036dSDavidlohr Bueso cxl_mbox_cmd_rc2str(mbox_cmd)); 268cbe83a20SDavidlohr Bueso return 0; /* completed but caller must check return_code */ 26921e9f767SBen Widawsky } 27021e9f767SBen Widawsky 27121e9f767SBen Widawsky /* #7 */ 2725e2411aeSIra Weiny cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 27321e9f767SBen Widawsky out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 27421e9f767SBen Widawsky 27521e9f767SBen Widawsky /* #8 */ 27621e9f767SBen Widawsky if (out_len && mbox_cmd->payload_out) { 27721e9f767SBen Widawsky /* 27821e9f767SBen Widawsky * Sanitize the copy. If hardware misbehaves, out_len per the 27921e9f767SBen Widawsky * spec can actually be greater than the max allowed size (21 28021e9f767SBen Widawsky * bits available but spec defined 1M max). The caller also may 28121e9f767SBen Widawsky * have requested less data than the hardware supplied even 28221e9f767SBen Widawsky * within spec. 28321e9f767SBen Widawsky */ 2845e2411aeSIra Weiny size_t n = min3(mbox_cmd->size_out, cxlds->payload_size, out_len); 28521e9f767SBen Widawsky 28621e9f767SBen Widawsky memcpy_fromio(mbox_cmd->payload_out, payload, n); 28721e9f767SBen Widawsky mbox_cmd->size_out = n; 28821e9f767SBen Widawsky } else { 28921e9f767SBen Widawsky mbox_cmd->size_out = 0; 29021e9f767SBen Widawsky } 29121e9f767SBen Widawsky 29221e9f767SBen Widawsky return 0; 29321e9f767SBen Widawsky } 29421e9f767SBen Widawsky 2955e2411aeSIra Weiny static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) 296b64955a9SDan Williams { 297b64955a9SDan Williams int rc; 298b64955a9SDan Williams 2994f195ee7SDan Williams mutex_lock_io(&cxlds->mbox_mutex); 3005e2411aeSIra Weiny rc = __cxl_pci_mbox_send_cmd(cxlds, cmd); 3014f195ee7SDan Williams mutex_unlock(&cxlds->mbox_mutex); 302b64955a9SDan Williams 303b64955a9SDan Williams return rc; 304b64955a9SDan Williams } 305b64955a9SDan Williams 3065e2411aeSIra Weiny static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) 30721e9f767SBen Widawsky { 3085e2411aeSIra Weiny const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 309229e8828SBen Widawsky unsigned long timeout; 310229e8828SBen Widawsky u64 md_status; 311229e8828SBen Widawsky 312229e8828SBen Widawsky timeout = jiffies + mbox_ready_timeout * HZ; 313229e8828SBen Widawsky do { 314229e8828SBen Widawsky md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 315229e8828SBen Widawsky if (md_status & CXLMDEV_MBOX_IF_READY) 316229e8828SBen Widawsky break; 317229e8828SBen Widawsky if (msleep_interruptible(100)) 318229e8828SBen Widawsky break; 319229e8828SBen Widawsky } while (!time_after(jiffies, timeout)); 320229e8828SBen Widawsky 321229e8828SBen Widawsky if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 3224f195ee7SDan Williams cxl_err(cxlds->dev, md_status, 3234f195ee7SDan Williams "timeout awaiting mailbox ready"); 3244f195ee7SDan Williams return -ETIMEDOUT; 3254f195ee7SDan Williams } 3264f195ee7SDan Williams 3274f195ee7SDan Williams /* 3284f195ee7SDan Williams * A command may be in flight from a previous driver instance, 3294f195ee7SDan Williams * think kexec, do one doorbell wait so that 3304f195ee7SDan Williams * __cxl_pci_mbox_send_cmd() can assume that it is the only 3314f195ee7SDan Williams * source for future doorbell busy events. 3324f195ee7SDan Williams */ 3334f195ee7SDan Williams if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 3344f195ee7SDan Williams cxl_err(cxlds->dev, md_status, "timeout awaiting mailbox idle"); 3354f195ee7SDan Williams return -ETIMEDOUT; 336229e8828SBen Widawsky } 33721e9f767SBen Widawsky 3385e2411aeSIra Weiny cxlds->mbox_send = cxl_pci_mbox_send; 3395e2411aeSIra Weiny cxlds->payload_size = 34021e9f767SBen Widawsky 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 34121e9f767SBen Widawsky 34221e9f767SBen Widawsky /* 34321e9f767SBen Widawsky * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 34421e9f767SBen Widawsky * 34521e9f767SBen Widawsky * If the size is too small, mandatory commands will not work and so 34621e9f767SBen Widawsky * there's no point in going forward. If the size is too large, there's 34721e9f767SBen Widawsky * no harm is soft limiting it. 34821e9f767SBen Widawsky */ 3495e2411aeSIra Weiny cxlds->payload_size = min_t(size_t, cxlds->payload_size, SZ_1M); 3505e2411aeSIra Weiny if (cxlds->payload_size < 256) { 3515e2411aeSIra Weiny dev_err(cxlds->dev, "Mailbox is too small (%zub)", 3525e2411aeSIra Weiny cxlds->payload_size); 35321e9f767SBen Widawsky return -ENXIO; 35421e9f767SBen Widawsky } 35521e9f767SBen Widawsky 3565e2411aeSIra Weiny dev_dbg(cxlds->dev, "Mailbox payload sized %zu", 3575e2411aeSIra Weiny cxlds->payload_size); 35821e9f767SBen Widawsky 359*ccadf131SDavidlohr Bueso rcuwait_init(&cxlds->mbox_wait); 360*ccadf131SDavidlohr Bueso 361*ccadf131SDavidlohr Bueso if (cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) { 362*ccadf131SDavidlohr Bueso u32 ctrl; 363*ccadf131SDavidlohr Bueso int irq, msgnum; 364*ccadf131SDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 365*ccadf131SDavidlohr Bueso 366*ccadf131SDavidlohr Bueso msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 367*ccadf131SDavidlohr Bueso irq = pci_irq_vector(pdev, msgnum); 368*ccadf131SDavidlohr Bueso if (irq < 0) 369*ccadf131SDavidlohr Bueso goto mbox_poll; 370*ccadf131SDavidlohr Bueso 371*ccadf131SDavidlohr Bueso if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq, NULL)) 372*ccadf131SDavidlohr Bueso goto mbox_poll; 373*ccadf131SDavidlohr Bueso 374*ccadf131SDavidlohr Bueso /* enable background command mbox irq support */ 375*ccadf131SDavidlohr Bueso ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 376*ccadf131SDavidlohr Bueso ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 377*ccadf131SDavidlohr Bueso writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 378*ccadf131SDavidlohr Bueso 379*ccadf131SDavidlohr Bueso return 0; 380*ccadf131SDavidlohr Bueso } 381*ccadf131SDavidlohr Bueso 382*ccadf131SDavidlohr Bueso mbox_poll: 383*ccadf131SDavidlohr Bueso dev_dbg(cxlds->dev, "Mailbox interrupts are unsupported"); 38421e9f767SBen Widawsky return 0; 38521e9f767SBen Widawsky } 38621e9f767SBen Widawsky 387a261e9a1SDan Williams static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) 3881b0a1a2aSBen Widawsky { 3897dc7a64dSBen Widawsky struct device *dev = &pdev->dev; 3901b0a1a2aSBen Widawsky 3916c7f4f1eSDan Williams map->base = ioremap(map->resource, map->max_size); 3926c7f4f1eSDan Williams if (!map->base) { 39321e9f767SBen Widawsky dev_err(dev, "failed to map registers\n"); 394a261e9a1SDan Williams return -ENOMEM; 39521e9f767SBen Widawsky } 39621e9f767SBen Widawsky 3976c7f4f1eSDan Williams dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource); 398a261e9a1SDan Williams return 0; 39930af9729SIra Weiny } 40030af9729SIra Weiny 401a261e9a1SDan Williams static void cxl_unmap_regblock(struct pci_dev *pdev, 402a261e9a1SDan Williams struct cxl_register_map *map) 40330af9729SIra Weiny { 4046c7f4f1eSDan Williams iounmap(map->base); 405a261e9a1SDan Williams map->base = NULL; 40621e9f767SBen Widawsky } 40721e9f767SBen Widawsky 408a261e9a1SDan Williams static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map) 40930af9729SIra Weiny { 41008422378SBen Widawsky struct cxl_component_reg_map *comp_map; 41130af9729SIra Weiny struct cxl_device_reg_map *dev_map; 4127dc7a64dSBen Widawsky struct device *dev = &pdev->dev; 413a261e9a1SDan Williams void __iomem *base = map->base; 41430af9729SIra Weiny 41530af9729SIra Weiny switch (map->reg_type) { 41608422378SBen Widawsky case CXL_REGLOC_RBI_COMPONENT: 41708422378SBen Widawsky comp_map = &map->component_map; 41808422378SBen Widawsky cxl_probe_component_regs(dev, base, comp_map); 41908422378SBen Widawsky if (!comp_map->hdm_decoder.valid) { 42008422378SBen Widawsky dev_err(dev, "HDM decoder registers not found\n"); 42108422378SBen Widawsky return -ENXIO; 42208422378SBen Widawsky } 42308422378SBen Widawsky 424bd09626bSDan Williams if (!comp_map->ras.valid) 425bd09626bSDan Williams dev_dbg(dev, "RAS registers not found\n"); 426bd09626bSDan Williams 42708422378SBen Widawsky dev_dbg(dev, "Set up component registers\n"); 42808422378SBen Widawsky break; 42930af9729SIra Weiny case CXL_REGLOC_RBI_MEMDEV: 43030af9729SIra Weiny dev_map = &map->device_map; 43130af9729SIra Weiny cxl_probe_device_regs(dev, base, dev_map); 43230af9729SIra Weiny if (!dev_map->status.valid || !dev_map->mbox.valid || 43330af9729SIra Weiny !dev_map->memdev.valid) { 43430af9729SIra Weiny dev_err(dev, "registers not found: %s%s%s\n", 43530af9729SIra Weiny !dev_map->status.valid ? "status " : "", 436da582aa5SLi Qiang (Johnny Li) !dev_map->mbox.valid ? "mbox " : "", 437da582aa5SLi Qiang (Johnny Li) !dev_map->memdev.valid ? "memdev " : ""); 43830af9729SIra Weiny return -ENXIO; 43930af9729SIra Weiny } 44030af9729SIra Weiny 44130af9729SIra Weiny dev_dbg(dev, "Probing device registers...\n"); 44230af9729SIra Weiny break; 44330af9729SIra Weiny default: 44430af9729SIra Weiny break; 44530af9729SIra Weiny } 44630af9729SIra Weiny 44730af9729SIra Weiny return 0; 44830af9729SIra Weiny } 44930af9729SIra Weiny 45085afc317SBen Widawsky static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 45185afc317SBen Widawsky struct cxl_register_map *map) 45285afc317SBen Widawsky { 45385afc317SBen Widawsky int rc; 45485afc317SBen Widawsky 45585afc317SBen Widawsky rc = cxl_find_regblock(pdev, type, map); 45685afc317SBen Widawsky if (rc) 45785afc317SBen Widawsky return rc; 45885afc317SBen Widawsky 45985afc317SBen Widawsky rc = cxl_map_regblock(pdev, map); 46085afc317SBen Widawsky if (rc) 46185afc317SBen Widawsky return rc; 46285afc317SBen Widawsky 46385afc317SBen Widawsky rc = cxl_probe_regs(pdev, map); 464a261e9a1SDan Williams cxl_unmap_regblock(pdev, map); 4655b68705dSBen Widawsky 46685afc317SBen Widawsky return rc; 4671d5a4159SBen Widawsky } 4681d5a4159SBen Widawsky 4690a19bfc8SDan Williams /* 4700a19bfc8SDan Williams * Assume that any RCIEP that emits the CXL memory expander class code 4710a19bfc8SDan Williams * is an RCD 4720a19bfc8SDan Williams */ 4730a19bfc8SDan Williams static bool is_cxl_restricted(struct pci_dev *pdev) 4740a19bfc8SDan Williams { 4750a19bfc8SDan Williams return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 4760a19bfc8SDan Williams } 4770a19bfc8SDan Williams 478248529edSDave Jiang /* 479248529edSDave Jiang * CXL v3.0 6.2.3 Table 6-4 480248529edSDave Jiang * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits 481248529edSDave Jiang * mode, otherwise it's 68B flits mode. 482248529edSDave Jiang */ 483248529edSDave Jiang static bool cxl_pci_flit_256(struct pci_dev *pdev) 4842905cb52SDan Williams { 485248529edSDave Jiang u16 lnksta2; 486248529edSDave Jiang 487248529edSDave Jiang pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2); 488248529edSDave Jiang return lnksta2 & PCI_EXP_LNKSTA2_FLIT; 489248529edSDave Jiang } 490248529edSDave Jiang 491248529edSDave Jiang static int cxl_pci_ras_unmask(struct pci_dev *pdev) 492248529edSDave Jiang { 493248529edSDave Jiang struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 494248529edSDave Jiang struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 495248529edSDave Jiang void __iomem *addr; 496248529edSDave Jiang u32 orig_val, val, mask; 497248529edSDave Jiang u16 cap; 498248529edSDave Jiang int rc; 499248529edSDave Jiang 500248529edSDave Jiang if (!cxlds->regs.ras) { 501248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS registers.\n"); 502248529edSDave Jiang return 0; 503248529edSDave Jiang } 504248529edSDave Jiang 505248529edSDave Jiang /* BIOS has CXL error control */ 506248529edSDave Jiang if (!host_bridge->native_cxl_error) 507248529edSDave Jiang return -ENXIO; 508248529edSDave Jiang 509248529edSDave Jiang rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 510248529edSDave Jiang if (rc) 511248529edSDave Jiang return rc; 512248529edSDave Jiang 513248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_URRE) { 514248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 515248529edSDave Jiang orig_val = readl(addr); 516248529edSDave Jiang 517248529edSDave Jiang mask = CXL_RAS_UNCORRECTABLE_MASK_MASK; 518248529edSDave Jiang if (!cxl_pci_flit_256(pdev)) 519248529edSDave Jiang mask &= ~CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 520248529edSDave Jiang val = orig_val & ~mask; 521248529edSDave Jiang writel(val, addr); 522248529edSDave Jiang dev_dbg(&pdev->dev, 523248529edSDave Jiang "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 524248529edSDave Jiang orig_val, val); 525248529edSDave Jiang } 526248529edSDave Jiang 527248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_CERE) { 528248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 529248529edSDave Jiang orig_val = readl(addr); 530248529edSDave Jiang val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 531248529edSDave Jiang writel(val, addr); 532248529edSDave Jiang dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 533248529edSDave Jiang orig_val, val); 534248529edSDave Jiang } 535248529edSDave Jiang 536248529edSDave Jiang return 0; 5372905cb52SDan Williams } 5382905cb52SDan Williams 5396ebe28f9SIra Weiny static void free_event_buf(void *buf) 5406ebe28f9SIra Weiny { 5416ebe28f9SIra Weiny kvfree(buf); 5426ebe28f9SIra Weiny } 5436ebe28f9SIra Weiny 5446ebe28f9SIra Weiny /* 5456ebe28f9SIra Weiny * There is a single buffer for reading event logs from the mailbox. All logs 5466ebe28f9SIra Weiny * share this buffer protected by the cxlds->event_log_lock. 5476ebe28f9SIra Weiny */ 5486ebe28f9SIra Weiny static int cxl_mem_alloc_event_buf(struct cxl_dev_state *cxlds) 5496ebe28f9SIra Weiny { 5506ebe28f9SIra Weiny struct cxl_get_event_payload *buf; 5516ebe28f9SIra Weiny 5526ebe28f9SIra Weiny buf = kvmalloc(cxlds->payload_size, GFP_KERNEL); 5536ebe28f9SIra Weiny if (!buf) 5546ebe28f9SIra Weiny return -ENOMEM; 5556ebe28f9SIra Weiny cxlds->event.buf = buf; 5566ebe28f9SIra Weiny 5576ebe28f9SIra Weiny return devm_add_action_or_reset(cxlds->dev, free_event_buf, buf); 5586ebe28f9SIra Weiny } 5596ebe28f9SIra Weiny 560a49aa814SDavidlohr Bueso static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 561a49aa814SDavidlohr Bueso { 562a49aa814SDavidlohr Bueso int nvecs; 563a49aa814SDavidlohr Bueso 564a49aa814SDavidlohr Bueso /* 565a49aa814SDavidlohr Bueso * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 566a49aa814SDavidlohr Bueso * not generate INTx messages if that function participates in 567a49aa814SDavidlohr Bueso * CXL.cache or CXL.mem. 568a49aa814SDavidlohr Bueso * 569a49aa814SDavidlohr Bueso * Additionally pci_alloc_irq_vectors() handles calling 570a49aa814SDavidlohr Bueso * pci_free_irq_vectors() automatically despite not being called 571a49aa814SDavidlohr Bueso * pcim_*. See pci_setup_msi_context(). 572a49aa814SDavidlohr Bueso */ 573a49aa814SDavidlohr Bueso nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 574a49aa814SDavidlohr Bueso PCI_IRQ_MSIX | PCI_IRQ_MSI); 575a49aa814SDavidlohr Bueso if (nvecs < 1) { 576a49aa814SDavidlohr Bueso dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 577a49aa814SDavidlohr Bueso return -ENXIO; 578a49aa814SDavidlohr Bueso } 579a49aa814SDavidlohr Bueso return 0; 580a49aa814SDavidlohr Bueso } 581a49aa814SDavidlohr Bueso 582a49aa814SDavidlohr Bueso static irqreturn_t cxl_event_thread(int irq, void *id) 583a49aa814SDavidlohr Bueso { 584a49aa814SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 585a49aa814SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 586a49aa814SDavidlohr Bueso u32 status; 587a49aa814SDavidlohr Bueso 588a49aa814SDavidlohr Bueso do { 589a49aa814SDavidlohr Bueso /* 590a49aa814SDavidlohr Bueso * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 591a49aa814SDavidlohr Bueso * ignore the reserved upper 32 bits 592a49aa814SDavidlohr Bueso */ 593a49aa814SDavidlohr Bueso status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 594a49aa814SDavidlohr Bueso /* Ignore logs unknown to the driver */ 595a49aa814SDavidlohr Bueso status &= CXLDEV_EVENT_STATUS_ALL; 596a49aa814SDavidlohr Bueso if (!status) 597a49aa814SDavidlohr Bueso break; 598a49aa814SDavidlohr Bueso cxl_mem_get_event_records(cxlds, status); 599a49aa814SDavidlohr Bueso cond_resched(); 600a49aa814SDavidlohr Bueso } while (status); 601a49aa814SDavidlohr Bueso 602a49aa814SDavidlohr Bueso return IRQ_HANDLED; 603a49aa814SDavidlohr Bueso } 604a49aa814SDavidlohr Bueso 605a49aa814SDavidlohr Bueso static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 606a49aa814SDavidlohr Bueso { 6079f7a320dSDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 608a49aa814SDavidlohr Bueso int irq; 609a49aa814SDavidlohr Bueso 610a49aa814SDavidlohr Bueso if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 611a49aa814SDavidlohr Bueso return -ENXIO; 612a49aa814SDavidlohr Bueso 613a49aa814SDavidlohr Bueso irq = pci_irq_vector(pdev, 614a49aa814SDavidlohr Bueso FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 615a49aa814SDavidlohr Bueso if (irq < 0) 616a49aa814SDavidlohr Bueso return irq; 617a49aa814SDavidlohr Bueso 6189f7a320dSDavidlohr Bueso return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 619a49aa814SDavidlohr Bueso } 620a49aa814SDavidlohr Bueso 621a49aa814SDavidlohr Bueso static int cxl_event_get_int_policy(struct cxl_dev_state *cxlds, 622a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 623a49aa814SDavidlohr Bueso { 624a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd = { 625a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 626a49aa814SDavidlohr Bueso .payload_out = policy, 627a49aa814SDavidlohr Bueso .size_out = sizeof(*policy), 628a49aa814SDavidlohr Bueso }; 629a49aa814SDavidlohr Bueso int rc; 630a49aa814SDavidlohr Bueso 631a49aa814SDavidlohr Bueso rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); 632a49aa814SDavidlohr Bueso if (rc < 0) 633a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get event interrupt policy : %d", 634a49aa814SDavidlohr Bueso rc); 635a49aa814SDavidlohr Bueso 636a49aa814SDavidlohr Bueso return rc; 637a49aa814SDavidlohr Bueso } 638a49aa814SDavidlohr Bueso 639a49aa814SDavidlohr Bueso static int cxl_event_config_msgnums(struct cxl_dev_state *cxlds, 640a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 641a49aa814SDavidlohr Bueso { 642a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd; 643a49aa814SDavidlohr Bueso int rc; 644a49aa814SDavidlohr Bueso 645a49aa814SDavidlohr Bueso *policy = (struct cxl_event_interrupt_policy) { 646a49aa814SDavidlohr Bueso .info_settings = CXL_INT_MSI_MSIX, 647a49aa814SDavidlohr Bueso .warn_settings = CXL_INT_MSI_MSIX, 648a49aa814SDavidlohr Bueso .failure_settings = CXL_INT_MSI_MSIX, 649a49aa814SDavidlohr Bueso .fatal_settings = CXL_INT_MSI_MSIX, 650a49aa814SDavidlohr Bueso }; 651a49aa814SDavidlohr Bueso 652a49aa814SDavidlohr Bueso mbox_cmd = (struct cxl_mbox_cmd) { 653a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 654a49aa814SDavidlohr Bueso .payload_in = policy, 655a49aa814SDavidlohr Bueso .size_in = sizeof(*policy), 656a49aa814SDavidlohr Bueso }; 657a49aa814SDavidlohr Bueso 658a49aa814SDavidlohr Bueso rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); 659a49aa814SDavidlohr Bueso if (rc < 0) { 660a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to set event interrupt policy : %d", 661a49aa814SDavidlohr Bueso rc); 662a49aa814SDavidlohr Bueso return rc; 663a49aa814SDavidlohr Bueso } 664a49aa814SDavidlohr Bueso 665a49aa814SDavidlohr Bueso /* Retrieve final interrupt settings */ 666a49aa814SDavidlohr Bueso return cxl_event_get_int_policy(cxlds, policy); 667a49aa814SDavidlohr Bueso } 668a49aa814SDavidlohr Bueso 669a49aa814SDavidlohr Bueso static int cxl_event_irqsetup(struct cxl_dev_state *cxlds) 670a49aa814SDavidlohr Bueso { 671a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 672a49aa814SDavidlohr Bueso int rc; 673a49aa814SDavidlohr Bueso 674a49aa814SDavidlohr Bueso rc = cxl_event_config_msgnums(cxlds, &policy); 675a49aa814SDavidlohr Bueso if (rc) 676a49aa814SDavidlohr Bueso return rc; 677a49aa814SDavidlohr Bueso 678a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.info_settings); 679a49aa814SDavidlohr Bueso if (rc) { 680a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 681a49aa814SDavidlohr Bueso return rc; 682a49aa814SDavidlohr Bueso } 683a49aa814SDavidlohr Bueso 684a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.warn_settings); 685a49aa814SDavidlohr Bueso if (rc) { 686a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 687a49aa814SDavidlohr Bueso return rc; 688a49aa814SDavidlohr Bueso } 689a49aa814SDavidlohr Bueso 690a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.failure_settings); 691a49aa814SDavidlohr Bueso if (rc) { 692a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 693a49aa814SDavidlohr Bueso return rc; 694a49aa814SDavidlohr Bueso } 695a49aa814SDavidlohr Bueso 696a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 697a49aa814SDavidlohr Bueso if (rc) { 698a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 699a49aa814SDavidlohr Bueso return rc; 700a49aa814SDavidlohr Bueso } 701a49aa814SDavidlohr Bueso 702a49aa814SDavidlohr Bueso return 0; 703a49aa814SDavidlohr Bueso } 704a49aa814SDavidlohr Bueso 705a49aa814SDavidlohr Bueso static bool cxl_event_int_is_fw(u8 setting) 706a49aa814SDavidlohr Bueso { 707a49aa814SDavidlohr Bueso u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 708a49aa814SDavidlohr Bueso 709a49aa814SDavidlohr Bueso return mode == CXL_INT_FW; 710a49aa814SDavidlohr Bueso } 711a49aa814SDavidlohr Bueso 712a49aa814SDavidlohr Bueso static int cxl_event_config(struct pci_host_bridge *host_bridge, 713a49aa814SDavidlohr Bueso struct cxl_dev_state *cxlds) 714a49aa814SDavidlohr Bueso { 715a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 716a49aa814SDavidlohr Bueso int rc; 717a49aa814SDavidlohr Bueso 718a49aa814SDavidlohr Bueso /* 719a49aa814SDavidlohr Bueso * When BIOS maintains CXL error reporting control, it will process 720a49aa814SDavidlohr Bueso * event records. Only one agent can do so. 721a49aa814SDavidlohr Bueso */ 722a49aa814SDavidlohr Bueso if (!host_bridge->native_cxl_error) 723a49aa814SDavidlohr Bueso return 0; 724a49aa814SDavidlohr Bueso 725a49aa814SDavidlohr Bueso rc = cxl_mem_alloc_event_buf(cxlds); 726a49aa814SDavidlohr Bueso if (rc) 727a49aa814SDavidlohr Bueso return rc; 728a49aa814SDavidlohr Bueso 729a49aa814SDavidlohr Bueso rc = cxl_event_get_int_policy(cxlds, &policy); 730a49aa814SDavidlohr Bueso if (rc) 731a49aa814SDavidlohr Bueso return rc; 732a49aa814SDavidlohr Bueso 733a49aa814SDavidlohr Bueso if (cxl_event_int_is_fw(policy.info_settings) || 734a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.warn_settings) || 735a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.failure_settings) || 736a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.fatal_settings)) { 737a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "FW still in control of Event Logs despite _OSC settings\n"); 738a49aa814SDavidlohr Bueso return -EBUSY; 739a49aa814SDavidlohr Bueso } 740a49aa814SDavidlohr Bueso 741a49aa814SDavidlohr Bueso rc = cxl_event_irqsetup(cxlds); 742a49aa814SDavidlohr Bueso if (rc) 743a49aa814SDavidlohr Bueso return rc; 744a49aa814SDavidlohr Bueso 745a49aa814SDavidlohr Bueso cxl_mem_get_event_records(cxlds, CXLDEV_EVENT_STATUS_ALL); 746a49aa814SDavidlohr Bueso 747a49aa814SDavidlohr Bueso return 0; 748a49aa814SDavidlohr Bueso } 749a49aa814SDavidlohr Bueso 750ed97afb5SBen Widawsky static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 75121e9f767SBen Widawsky { 7526ebe28f9SIra Weiny struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 75385afc317SBen Widawsky struct cxl_register_map map; 75421083f51SDan Williams struct cxl_memdev *cxlmd; 7555e2411aeSIra Weiny struct cxl_dev_state *cxlds; 7561d5a4159SBen Widawsky int rc; 75721e9f767SBen Widawsky 7585a2328f4SDan Williams /* 7595a2328f4SDan Williams * Double check the anonymous union trickery in struct cxl_regs 7605a2328f4SDan Williams * FIXME switch to struct_group() 7615a2328f4SDan Williams */ 7625a2328f4SDan Williams BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 7635a2328f4SDan Williams offsetof(struct cxl_regs, device_regs.memdev)); 7645a2328f4SDan Williams 76521e9f767SBen Widawsky rc = pcim_enable_device(pdev); 76621e9f767SBen Widawsky if (rc) 76721e9f767SBen Widawsky return rc; 768a49aa814SDavidlohr Bueso pci_set_master(pdev); 76921e9f767SBen Widawsky 7705e2411aeSIra Weiny cxlds = cxl_dev_state_create(&pdev->dev); 7715e2411aeSIra Weiny if (IS_ERR(cxlds)) 7725e2411aeSIra Weiny return PTR_ERR(cxlds); 7732905cb52SDan Williams pci_set_drvdata(pdev, cxlds); 7741b0a1a2aSBen Widawsky 7750a19bfc8SDan Williams cxlds->rcd = is_cxl_restricted(pdev); 776bcc79ea3SDan Williams cxlds->serial = pci_get_dsn(pdev); 77706e279e5SBen Widawsky cxlds->cxl_dvsec = pci_find_dvsec_capability( 77806e279e5SBen Widawsky pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 77906e279e5SBen Widawsky if (!cxlds->cxl_dvsec) 78006e279e5SBen Widawsky dev_warn(&pdev->dev, 78106e279e5SBen Widawsky "Device DVSEC not present, skip CXL.mem init\n"); 78206e279e5SBen Widawsky 78385afc317SBen Widawsky rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 78485afc317SBen Widawsky if (rc) 78585afc317SBen Widawsky return rc; 78685afc317SBen Widawsky 7876c7f4f1eSDan Williams rc = cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map); 78821e9f767SBen Widawsky if (rc) 78921e9f767SBen Widawsky return rc; 79021e9f767SBen Widawsky 7914112a08dSBen Widawsky /* 7924112a08dSBen Widawsky * If the component registers can't be found, the cxl_pci driver may 7934112a08dSBen Widawsky * still be useful for management functions so don't return an error. 7944112a08dSBen Widawsky */ 7954112a08dSBen Widawsky cxlds->component_reg_phys = CXL_RESOURCE_NONE; 7964112a08dSBen Widawsky rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 7974112a08dSBen Widawsky if (rc) 7984112a08dSBen Widawsky dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 7994112a08dSBen Widawsky 8006c7f4f1eSDan Williams cxlds->component_reg_phys = map.resource; 8014112a08dSBen Widawsky 802bd09626bSDan Williams rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, 803bd09626bSDan Williams &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); 804bd09626bSDan Williams if (rc) 805bd09626bSDan Williams dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 806bd09626bSDan Williams 807e764f122SDave Jiang rc = cxl_await_media_ready(cxlds); 808e764f122SDave Jiang if (rc == 0) 809e764f122SDave Jiang cxlds->media_ready = true; 810e764f122SDave Jiang else 811e764f122SDave Jiang dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 812e764f122SDave Jiang 813f279d0bcSDavidlohr Bueso rc = cxl_alloc_irq_vectors(pdev); 814f279d0bcSDavidlohr Bueso if (rc) 815f279d0bcSDavidlohr Bueso return rc; 816f279d0bcSDavidlohr Bueso 8175e2411aeSIra Weiny rc = cxl_pci_setup_mailbox(cxlds); 81821e9f767SBen Widawsky if (rc) 81921e9f767SBen Widawsky return rc; 82021e9f767SBen Widawsky 8215e2411aeSIra Weiny rc = cxl_enumerate_cmds(cxlds); 82221e9f767SBen Widawsky if (rc) 82321e9f767SBen Widawsky return rc; 82421e9f767SBen Widawsky 825fa884345SJonathan Cameron rc = cxl_set_timestamp(cxlds); 826fa884345SJonathan Cameron if (rc) 827fa884345SJonathan Cameron return rc; 828fa884345SJonathan Cameron 829d0abf578SAlison Schofield rc = cxl_poison_state_init(cxlds); 830d0abf578SAlison Schofield if (rc) 831d0abf578SAlison Schofield return rc; 832d0abf578SAlison Schofield 8335e2411aeSIra Weiny rc = cxl_dev_state_identify(cxlds); 83421e9f767SBen Widawsky if (rc) 83521e9f767SBen Widawsky return rc; 83621e9f767SBen Widawsky 8375e2411aeSIra Weiny rc = cxl_mem_create_range_info(cxlds); 838f847502aSIra Weiny if (rc) 839f847502aSIra Weiny return rc; 840f847502aSIra Weiny 8415e2411aeSIra Weiny cxlmd = devm_cxl_add_memdev(cxlds); 84221083f51SDan Williams if (IS_ERR(cxlmd)) 84321083f51SDan Williams return PTR_ERR(cxlmd); 84421083f51SDan Williams 845a49aa814SDavidlohr Bueso rc = cxl_event_config(host_bridge, cxlds); 8466ebe28f9SIra Weiny if (rc) 8476ebe28f9SIra Weiny return rc; 8486ebe28f9SIra Weiny 849248529edSDave Jiang rc = cxl_pci_ras_unmask(pdev); 8502905cb52SDan Williams if (rc) 851248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 852248529edSDave Jiang 8532905cb52SDan Williams pci_save_state(pdev); 8542905cb52SDan Williams 85521083f51SDan Williams return rc; 85621e9f767SBen Widawsky } 85721e9f767SBen Widawsky 85821e9f767SBen Widawsky static const struct pci_device_id cxl_mem_pci_tbl[] = { 85921e9f767SBen Widawsky /* PCI class code for CXL.mem Type-3 Devices */ 86021e9f767SBen Widawsky { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 86121e9f767SBen Widawsky { /* terminate list */ }, 86221e9f767SBen Widawsky }; 86321e9f767SBen Widawsky MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 86421e9f767SBen Widawsky 8652905cb52SDan Williams static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 8662905cb52SDan Williams { 8672905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 8682905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 8692905cb52SDan Williams struct device *dev = &cxlmd->dev; 8702905cb52SDan Williams 8712905cb52SDan Williams dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 8722905cb52SDan Williams dev_name(dev)); 8732905cb52SDan Williams pci_restore_state(pdev); 8742905cb52SDan Williams if (device_attach(dev) <= 0) 8752905cb52SDan Williams return PCI_ERS_RESULT_DISCONNECT; 8762905cb52SDan Williams return PCI_ERS_RESULT_RECOVERED; 8772905cb52SDan Williams } 8782905cb52SDan Williams 8792905cb52SDan Williams static void cxl_error_resume(struct pci_dev *pdev) 8802905cb52SDan Williams { 8812905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 8822905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 8832905cb52SDan Williams struct device *dev = &cxlmd->dev; 8842905cb52SDan Williams 8852905cb52SDan Williams dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 8862905cb52SDan Williams dev->driver ? "successful" : "failed"); 8872905cb52SDan Williams } 8882905cb52SDan Williams 8892905cb52SDan Williams static const struct pci_error_handlers cxl_error_handlers = { 8902905cb52SDan Williams .error_detected = cxl_error_detected, 8912905cb52SDan Williams .slot_reset = cxl_slot_reset, 8922905cb52SDan Williams .resume = cxl_error_resume, 8936155ccc9SDave Jiang .cor_error_detected = cxl_cor_error_detected, 8942905cb52SDan Williams }; 8952905cb52SDan Williams 896ed97afb5SBen Widawsky static struct pci_driver cxl_pci_driver = { 89721e9f767SBen Widawsky .name = KBUILD_MODNAME, 89821e9f767SBen Widawsky .id_table = cxl_mem_pci_tbl, 899ed97afb5SBen Widawsky .probe = cxl_pci_probe, 9002905cb52SDan Williams .err_handler = &cxl_error_handlers, 90121e9f767SBen Widawsky .driver = { 90221e9f767SBen Widawsky .probe_type = PROBE_PREFER_ASYNCHRONOUS, 90321e9f767SBen Widawsky }, 90421e9f767SBen Widawsky }; 90521e9f767SBen Widawsky 90621e9f767SBen Widawsky MODULE_LICENSE("GPL v2"); 907ed97afb5SBen Widawsky module_pci_driver(cxl_pci_driver); 90821e9f767SBen Widawsky MODULE_IMPORT_NS(CXL); 909