121e9f767SBen Widawsky // SPDX-License-Identifier: GPL-2.0-only 221e9f767SBen Widawsky /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 34faf31b4SDan Williams #include <linux/io-64-nonatomic-lo-hi.h> 4229e8828SBen Widawsky #include <linux/moduleparam.h> 521e9f767SBen Widawsky #include <linux/module.h> 6229e8828SBen Widawsky #include <linux/delay.h> 721e9f767SBen Widawsky #include <linux/sizes.h> 821e9f767SBen Widawsky #include <linux/mutex.h> 930af9729SIra Weiny #include <linux/list.h> 1021e9f767SBen Widawsky #include <linux/pci.h> 112905cb52SDan Williams #include <linux/aer.h> 1221e9f767SBen Widawsky #include <linux/io.h> 135161a55cSBen Widawsky #include "cxlmem.h" 14af9cae9fSDan Williams #include "cxlpci.h" 1521e9f767SBen Widawsky #include "cxl.h" 1621e9f767SBen Widawsky 1721e9f767SBen Widawsky /** 1821e9f767SBen Widawsky * DOC: cxl pci 1921e9f767SBen Widawsky * 2021e9f767SBen Widawsky * This implements the PCI exclusive functionality for a CXL device as it is 2121e9f767SBen Widawsky * defined by the Compute Express Link specification. CXL devices may surface 22ed97afb5SBen Widawsky * certain functionality even if it isn't CXL enabled. While this driver is 23ed97afb5SBen Widawsky * focused around the PCI specific aspects of a CXL device, it binds to the 24ed97afb5SBen Widawsky * specific CXL memory device class code, and therefore the implementation of 25ed97afb5SBen Widawsky * cxl_pci is focused around CXL memory devices. 2621e9f767SBen Widawsky * 2721e9f767SBen Widawsky * The driver has several responsibilities, mainly: 2821e9f767SBen Widawsky * - Create the memX device and register on the CXL bus. 2921e9f767SBen Widawsky * - Enumerate device's register interface and map them. 30ed97afb5SBen Widawsky * - Registers nvdimm bridge device with cxl_core. 31ed97afb5SBen Widawsky * - Registers a CXL mailbox with cxl_core. 3221e9f767SBen Widawsky */ 3321e9f767SBen Widawsky 345e2411aeSIra Weiny #define cxl_doorbell_busy(cxlds) \ 355e2411aeSIra Weiny (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 3621e9f767SBen Widawsky CXLDEV_MBOX_CTRL_DOORBELL) 3721e9f767SBen Widawsky 3821e9f767SBen Widawsky /* CXL 2.0 - 8.2.8.4 */ 3921e9f767SBen Widawsky #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 4021e9f767SBen Widawsky 41229e8828SBen Widawsky /* 42229e8828SBen Widawsky * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 43229e8828SBen Widawsky * dictate how long to wait for the mailbox to become ready. The new 44229e8828SBen Widawsky * field allows the device to tell software the amount of time to wait 45229e8828SBen Widawsky * before mailbox ready. This field per the spec theoretically allows 46229e8828SBen Widawsky * for up to 255 seconds. 255 seconds is unreasonably long, its longer 47229e8828SBen Widawsky * than the maximum SATA port link recovery wait. Default to 60 seconds 48229e8828SBen Widawsky * until someone builds a CXL device that needs more time in practice. 49229e8828SBen Widawsky */ 50229e8828SBen Widawsky static unsigned short mbox_ready_timeout = 60; 51229e8828SBen Widawsky module_param(mbox_ready_timeout, ushort, 0644); 522e4ba0ecSDan Williams MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 53229e8828SBen Widawsky 545e2411aeSIra Weiny static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 5521e9f767SBen Widawsky { 5621e9f767SBen Widawsky const unsigned long start = jiffies; 5721e9f767SBen Widawsky unsigned long end = start; 5821e9f767SBen Widawsky 595e2411aeSIra Weiny while (cxl_doorbell_busy(cxlds)) { 6021e9f767SBen Widawsky end = jiffies; 6121e9f767SBen Widawsky 6221e9f767SBen Widawsky if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 6321e9f767SBen Widawsky /* Check again in case preempted before timeout test */ 645e2411aeSIra Weiny if (!cxl_doorbell_busy(cxlds)) 6521e9f767SBen Widawsky break; 6621e9f767SBen Widawsky return -ETIMEDOUT; 6721e9f767SBen Widawsky } 6821e9f767SBen Widawsky cpu_relax(); 6921e9f767SBen Widawsky } 7021e9f767SBen Widawsky 715e2411aeSIra Weiny dev_dbg(cxlds->dev, "Doorbell wait took %dms", 7221e9f767SBen Widawsky jiffies_to_msecs(end) - jiffies_to_msecs(start)); 7321e9f767SBen Widawsky return 0; 7421e9f767SBen Widawsky } 7521e9f767SBen Widawsky 764f195ee7SDan Williams #define cxl_err(dev, status, msg) \ 774f195ee7SDan Williams dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 784f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 794f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8021e9f767SBen Widawsky 814f195ee7SDan Williams #define cxl_cmd_err(dev, cmd, status, msg) \ 824f195ee7SDan Williams dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 834f195ee7SDan Williams (cmd)->opcode, \ 844f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 854f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8621e9f767SBen Widawsky 879f7a320dSDavidlohr Bueso struct cxl_dev_id { 889f7a320dSDavidlohr Bueso struct cxl_dev_state *cxlds; 899f7a320dSDavidlohr Bueso }; 909f7a320dSDavidlohr Bueso 919f7a320dSDavidlohr Bueso static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 929f7a320dSDavidlohr Bueso irq_handler_t handler, irq_handler_t thread_fn) 939f7a320dSDavidlohr Bueso { 949f7a320dSDavidlohr Bueso struct device *dev = cxlds->dev; 959f7a320dSDavidlohr Bueso struct cxl_dev_id *dev_id; 969f7a320dSDavidlohr Bueso 979f7a320dSDavidlohr Bueso /* dev_id must be globally unique and must contain the cxlds */ 989f7a320dSDavidlohr Bueso dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 999f7a320dSDavidlohr Bueso if (!dev_id) 1009f7a320dSDavidlohr Bueso return -ENOMEM; 1019f7a320dSDavidlohr Bueso dev_id->cxlds = cxlds; 1029f7a320dSDavidlohr Bueso 1039f7a320dSDavidlohr Bueso return devm_request_threaded_irq(dev, irq, handler, thread_fn, 1049f7a320dSDavidlohr Bueso IRQF_SHARED | IRQF_ONESHOT, 1059f7a320dSDavidlohr Bueso NULL, dev_id); 1069f7a320dSDavidlohr Bueso } 1079f7a320dSDavidlohr Bueso 108ccadf131SDavidlohr Bueso static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 109ccadf131SDavidlohr Bueso { 110ccadf131SDavidlohr Bueso u64 reg; 111ccadf131SDavidlohr Bueso 112ccadf131SDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 113ccadf131SDavidlohr Bueso return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 114ccadf131SDavidlohr Bueso } 115ccadf131SDavidlohr Bueso 116ccadf131SDavidlohr Bueso static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 117ccadf131SDavidlohr Bueso { 1180c36b6adSDavidlohr Bueso u64 reg; 1190c36b6adSDavidlohr Bueso u16 opcode; 120ccadf131SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 121ccadf131SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 122aeaefabcSDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 123ccadf131SDavidlohr Bueso 1248ea9c33dSDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) 1258ea9c33dSDavidlohr Bueso return IRQ_NONE; 1268ea9c33dSDavidlohr Bueso 1270c36b6adSDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 1280c36b6adSDavidlohr Bueso opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 1290c36b6adSDavidlohr Bueso if (opcode == CXL_MBOX_OP_SANITIZE) { 130aeaefabcSDan Williams if (mds->security.sanitize_node) 131aeaefabcSDan Williams sysfs_notify_dirent(mds->security.sanitize_node); 13248dcdbb1SDavidlohr Bueso 1330c36b6adSDavidlohr Bueso dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 1340c36b6adSDavidlohr Bueso } else { 135ccadf131SDavidlohr Bueso /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 136aeaefabcSDan Williams rcuwait_wake_up(&mds->mbox_wait); 1370c36b6adSDavidlohr Bueso } 138ccadf131SDavidlohr Bueso 139ccadf131SDavidlohr Bueso return IRQ_HANDLED; 140ccadf131SDavidlohr Bueso } 141ccadf131SDavidlohr Bueso 1420c36b6adSDavidlohr Bueso /* 1430c36b6adSDavidlohr Bueso * Sanitization operation polling mode. 1440c36b6adSDavidlohr Bueso */ 1450c36b6adSDavidlohr Bueso static void cxl_mbox_sanitize_work(struct work_struct *work) 1460c36b6adSDavidlohr Bueso { 147aeaefabcSDan Williams struct cxl_memdev_state *mds = 148aeaefabcSDan Williams container_of(work, typeof(*mds), security.poll_dwork.work); 149aeaefabcSDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1500c36b6adSDavidlohr Bueso 151aeaefabcSDan Williams mutex_lock(&mds->mbox_mutex); 1520c36b6adSDavidlohr Bueso if (cxl_mbox_background_complete(cxlds)) { 153aeaefabcSDan Williams mds->security.poll_tmo_secs = 0; 1540c36b6adSDavidlohr Bueso put_device(cxlds->dev); 1550c36b6adSDavidlohr Bueso 156aeaefabcSDan Williams if (mds->security.sanitize_node) 157aeaefabcSDan Williams sysfs_notify_dirent(mds->security.sanitize_node); 15848dcdbb1SDavidlohr Bueso 1590c36b6adSDavidlohr Bueso dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 1600c36b6adSDavidlohr Bueso } else { 161aeaefabcSDan Williams int timeout = mds->security.poll_tmo_secs + 10; 1620c36b6adSDavidlohr Bueso 163aeaefabcSDan Williams mds->security.poll_tmo_secs = min(15 * 60, timeout); 164aeaefabcSDan Williams queue_delayed_work(system_wq, &mds->security.poll_dwork, 1650c36b6adSDavidlohr Bueso timeout * HZ); 1660c36b6adSDavidlohr Bueso } 167aeaefabcSDan Williams mutex_unlock(&mds->mbox_mutex); 1680c36b6adSDavidlohr Bueso } 1690c36b6adSDavidlohr Bueso 17021e9f767SBen Widawsky /** 171ed97afb5SBen Widawsky * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 17259f8d151SDan Williams * @mds: The memory device driver data 17321e9f767SBen Widawsky * @mbox_cmd: Command to send to the memory device. 17421e9f767SBen Widawsky * 17521e9f767SBen Widawsky * Context: Any context. Expects mbox_mutex to be held. 17621e9f767SBen Widawsky * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 17721e9f767SBen Widawsky * Caller should check the return code in @mbox_cmd to make sure it 17821e9f767SBen Widawsky * succeeded. 17921e9f767SBen Widawsky * 18021e9f767SBen Widawsky * This is a generic form of the CXL mailbox send command thus only using the 18121e9f767SBen Widawsky * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 18221e9f767SBen Widawsky * devices, and perhaps other types of CXL devices may have further information 18321e9f767SBen Widawsky * available upon error conditions. Driver facilities wishing to send mailbox 18421e9f767SBen Widawsky * commands should use the wrapper command. 18521e9f767SBen Widawsky * 18621e9f767SBen Widawsky * The CXL spec allows for up to two mailboxes. The intention is for the primary 18721e9f767SBen Widawsky * mailbox to be OS controlled and the secondary mailbox to be used by system 18821e9f767SBen Widawsky * firmware. This allows the OS and firmware to communicate with the device and 18921e9f767SBen Widawsky * not need to coordinate with each other. The driver only uses the primary 19021e9f767SBen Widawsky * mailbox. 19121e9f767SBen Widawsky */ 19259f8d151SDan Williams static int __cxl_pci_mbox_send_cmd(struct cxl_memdev_state *mds, 193b64955a9SDan Williams struct cxl_mbox_cmd *mbox_cmd) 19421e9f767SBen Widawsky { 19559f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1965e2411aeSIra Weiny void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 1975e2411aeSIra Weiny struct device *dev = cxlds->dev; 19821e9f767SBen Widawsky u64 cmd_reg, status_reg; 19921e9f767SBen Widawsky size_t out_len; 20021e9f767SBen Widawsky int rc; 20121e9f767SBen Widawsky 20259f8d151SDan Williams lockdep_assert_held(&mds->mbox_mutex); 20321e9f767SBen Widawsky 20421e9f767SBen Widawsky /* 20521e9f767SBen Widawsky * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 20621e9f767SBen Widawsky * 1. Caller reads MB Control Register to verify doorbell is clear 20721e9f767SBen Widawsky * 2. Caller writes Command Register 20821e9f767SBen Widawsky * 3. Caller writes Command Payload Registers if input payload is non-empty 20921e9f767SBen Widawsky * 4. Caller writes MB Control Register to set doorbell 21021e9f767SBen Widawsky * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 21121e9f767SBen Widawsky * 6. Caller reads MB Status Register to fetch Return code 21221e9f767SBen Widawsky * 7. If command successful, Caller reads Command Register to get Payload Length 21321e9f767SBen Widawsky * 8. If output payload is non-empty, host reads Command Payload Registers 21421e9f767SBen Widawsky * 21521e9f767SBen Widawsky * Hardware is free to do whatever it wants before the doorbell is rung, 21621e9f767SBen Widawsky * and isn't allowed to change anything after it clears the doorbell. As 21721e9f767SBen Widawsky * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 21821e9f767SBen Widawsky * also happen in any order (though some orders might not make sense). 21921e9f767SBen Widawsky */ 22021e9f767SBen Widawsky 22121e9f767SBen Widawsky /* #1 */ 2225e2411aeSIra Weiny if (cxl_doorbell_busy(cxlds)) { 2234f195ee7SDan Williams u64 md_status = 2244f195ee7SDan Williams readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2254f195ee7SDan Williams 2264f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 2274f195ee7SDan Williams "mailbox queue busy"); 22821e9f767SBen Widawsky return -EBUSY; 22921e9f767SBen Widawsky } 23021e9f767SBen Widawsky 2310c36b6adSDavidlohr Bueso /* 2320c36b6adSDavidlohr Bueso * With sanitize polling, hardware might be done and the poller still 2330c36b6adSDavidlohr Bueso * not be in sync. Ensure no new command comes in until so. Keep the 2340c36b6adSDavidlohr Bueso * hardware semantics and only allow device health status. 2350c36b6adSDavidlohr Bueso */ 236aeaefabcSDan Williams if (mds->security.poll_tmo_secs > 0) { 2370c36b6adSDavidlohr Bueso if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 2380c36b6adSDavidlohr Bueso return -EBUSY; 2390c36b6adSDavidlohr Bueso } 2400c36b6adSDavidlohr Bueso 24121e9f767SBen Widawsky cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 24221e9f767SBen Widawsky mbox_cmd->opcode); 24321e9f767SBen Widawsky if (mbox_cmd->size_in) { 24421e9f767SBen Widawsky if (WARN_ON(!mbox_cmd->payload_in)) 24521e9f767SBen Widawsky return -EINVAL; 24621e9f767SBen Widawsky 24721e9f767SBen Widawsky cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 24821e9f767SBen Widawsky mbox_cmd->size_in); 24921e9f767SBen Widawsky memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 25021e9f767SBen Widawsky } 25121e9f767SBen Widawsky 25221e9f767SBen Widawsky /* #2, #3 */ 2535e2411aeSIra Weiny writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 25421e9f767SBen Widawsky 25521e9f767SBen Widawsky /* #4 */ 256852db33cSRobert Richter dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 25721e9f767SBen Widawsky writel(CXLDEV_MBOX_CTRL_DOORBELL, 2585e2411aeSIra Weiny cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 25921e9f767SBen Widawsky 26021e9f767SBen Widawsky /* #5 */ 2615e2411aeSIra Weiny rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 26221e9f767SBen Widawsky if (rc == -ETIMEDOUT) { 2634f195ee7SDan Williams u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2644f195ee7SDan Williams 2654f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 26621e9f767SBen Widawsky return rc; 26721e9f767SBen Widawsky } 26821e9f767SBen Widawsky 26921e9f767SBen Widawsky /* #6 */ 2705e2411aeSIra Weiny status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 27121e9f767SBen Widawsky mbox_cmd->return_code = 27221e9f767SBen Widawsky FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 27321e9f767SBen Widawsky 274ccadf131SDavidlohr Bueso /* 275ccadf131SDavidlohr Bueso * Handle the background command in a synchronous manner. 276ccadf131SDavidlohr Bueso * 277ccadf131SDavidlohr Bueso * All other mailbox commands will serialize/queue on the mbox_mutex, 278ccadf131SDavidlohr Bueso * which we currently hold. Furthermore this also guarantees that 279ccadf131SDavidlohr Bueso * cxl_mbox_background_complete() checks are safe amongst each other, 280ccadf131SDavidlohr Bueso * in that no new bg operation can occur in between. 281ccadf131SDavidlohr Bueso * 282ccadf131SDavidlohr Bueso * Background operations are timesliced in accordance with the nature 283ccadf131SDavidlohr Bueso * of the command. In the event of timeout, the mailbox state is 284ccadf131SDavidlohr Bueso * indeterminate until the next successful command submission and the 285ccadf131SDavidlohr Bueso * driver can get back in sync with the hardware state. 286ccadf131SDavidlohr Bueso */ 287ccadf131SDavidlohr Bueso if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 288ccadf131SDavidlohr Bueso u64 bg_status_reg; 2890c36b6adSDavidlohr Bueso int i, timeout; 2900c36b6adSDavidlohr Bueso 2910c36b6adSDavidlohr Bueso /* 2920c36b6adSDavidlohr Bueso * Sanitization is a special case which monopolizes the device 2930c36b6adSDavidlohr Bueso * and cannot be timesliced. Handle asynchronously instead, 2940c36b6adSDavidlohr Bueso * and allow userspace to poll(2) for completion. 2950c36b6adSDavidlohr Bueso */ 2960c36b6adSDavidlohr Bueso if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 297aeaefabcSDan Williams if (mds->security.poll_tmo_secs != -1) { 2980c36b6adSDavidlohr Bueso /* hold the device throughout */ 2990c36b6adSDavidlohr Bueso get_device(cxlds->dev); 3000c36b6adSDavidlohr Bueso 3010c36b6adSDavidlohr Bueso /* give first timeout a second */ 3020c36b6adSDavidlohr Bueso timeout = 1; 303aeaefabcSDan Williams mds->security.poll_tmo_secs = timeout; 3040c36b6adSDavidlohr Bueso queue_delayed_work(system_wq, 305aeaefabcSDan Williams &mds->security.poll_dwork, 3060c36b6adSDavidlohr Bueso timeout * HZ); 3070c36b6adSDavidlohr Bueso } 3080c36b6adSDavidlohr Bueso 3090c36b6adSDavidlohr Bueso dev_dbg(dev, "Sanitization operation started\n"); 3100c36b6adSDavidlohr Bueso goto success; 3110c36b6adSDavidlohr Bueso } 312ccadf131SDavidlohr Bueso 313ccadf131SDavidlohr Bueso dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 314ccadf131SDavidlohr Bueso mbox_cmd->opcode); 315ccadf131SDavidlohr Bueso 3160c36b6adSDavidlohr Bueso timeout = mbox_cmd->poll_interval_ms; 317ccadf131SDavidlohr Bueso for (i = 0; i < mbox_cmd->poll_count; i++) { 318aeaefabcSDan Williams if (rcuwait_wait_event_timeout(&mds->mbox_wait, 319ccadf131SDavidlohr Bueso cxl_mbox_background_complete(cxlds), 320ccadf131SDavidlohr Bueso TASK_UNINTERRUPTIBLE, 321ccadf131SDavidlohr Bueso msecs_to_jiffies(timeout)) > 0) 322ccadf131SDavidlohr Bueso break; 323ccadf131SDavidlohr Bueso } 324ccadf131SDavidlohr Bueso 325ccadf131SDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) { 326ccadf131SDavidlohr Bueso dev_err(dev, "timeout waiting for background (%d ms)\n", 327ccadf131SDavidlohr Bueso timeout * mbox_cmd->poll_count); 328ccadf131SDavidlohr Bueso return -ETIMEDOUT; 329ccadf131SDavidlohr Bueso } 330ccadf131SDavidlohr Bueso 331ccadf131SDavidlohr Bueso bg_status_reg = readq(cxlds->regs.mbox + 332ccadf131SDavidlohr Bueso CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 333ccadf131SDavidlohr Bueso mbox_cmd->return_code = 334ccadf131SDavidlohr Bueso FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 335ccadf131SDavidlohr Bueso bg_status_reg); 336ccadf131SDavidlohr Bueso dev_dbg(dev, 337ccadf131SDavidlohr Bueso "Mailbox background operation (0x%04x) completed\n", 338ccadf131SDavidlohr Bueso mbox_cmd->opcode); 339ccadf131SDavidlohr Bueso } 340ccadf131SDavidlohr Bueso 34192fcc1abSDavidlohr Bueso if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 342c43e036dSDavidlohr Bueso dev_dbg(dev, "Mailbox operation had an error: %s\n", 343c43e036dSDavidlohr Bueso cxl_mbox_cmd_rc2str(mbox_cmd)); 344cbe83a20SDavidlohr Bueso return 0; /* completed but caller must check return_code */ 34521e9f767SBen Widawsky } 34621e9f767SBen Widawsky 3470c36b6adSDavidlohr Bueso success: 34821e9f767SBen Widawsky /* #7 */ 3495e2411aeSIra Weiny cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 35021e9f767SBen Widawsky out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 35121e9f767SBen Widawsky 35221e9f767SBen Widawsky /* #8 */ 35321e9f767SBen Widawsky if (out_len && mbox_cmd->payload_out) { 35421e9f767SBen Widawsky /* 35521e9f767SBen Widawsky * Sanitize the copy. If hardware misbehaves, out_len per the 35621e9f767SBen Widawsky * spec can actually be greater than the max allowed size (21 35721e9f767SBen Widawsky * bits available but spec defined 1M max). The caller also may 35821e9f767SBen Widawsky * have requested less data than the hardware supplied even 35921e9f767SBen Widawsky * within spec. 36021e9f767SBen Widawsky */ 36159f8d151SDan Williams size_t n; 36221e9f767SBen Widawsky 36359f8d151SDan Williams n = min3(mbox_cmd->size_out, mds->payload_size, out_len); 36421e9f767SBen Widawsky memcpy_fromio(mbox_cmd->payload_out, payload, n); 36521e9f767SBen Widawsky mbox_cmd->size_out = n; 36621e9f767SBen Widawsky } else { 36721e9f767SBen Widawsky mbox_cmd->size_out = 0; 36821e9f767SBen Widawsky } 36921e9f767SBen Widawsky 37021e9f767SBen Widawsky return 0; 37121e9f767SBen Widawsky } 37221e9f767SBen Widawsky 37359f8d151SDan Williams static int cxl_pci_mbox_send(struct cxl_memdev_state *mds, 37459f8d151SDan Williams struct cxl_mbox_cmd *cmd) 375b64955a9SDan Williams { 376b64955a9SDan Williams int rc; 377b64955a9SDan Williams 37859f8d151SDan Williams mutex_lock_io(&mds->mbox_mutex); 37959f8d151SDan Williams rc = __cxl_pci_mbox_send_cmd(mds, cmd); 38059f8d151SDan Williams mutex_unlock(&mds->mbox_mutex); 381b64955a9SDan Williams 382b64955a9SDan Williams return rc; 383b64955a9SDan Williams } 384b64955a9SDan Williams 38559f8d151SDan Williams static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) 38621e9f767SBen Widawsky { 38759f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 3885e2411aeSIra Weiny const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 38959f8d151SDan Williams struct device *dev = cxlds->dev; 390229e8828SBen Widawsky unsigned long timeout; 391229e8828SBen Widawsky u64 md_status; 392229e8828SBen Widawsky 393229e8828SBen Widawsky timeout = jiffies + mbox_ready_timeout * HZ; 394229e8828SBen Widawsky do { 395229e8828SBen Widawsky md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 396229e8828SBen Widawsky if (md_status & CXLMDEV_MBOX_IF_READY) 397229e8828SBen Widawsky break; 398229e8828SBen Widawsky if (msleep_interruptible(100)) 399229e8828SBen Widawsky break; 400229e8828SBen Widawsky } while (!time_after(jiffies, timeout)); 401229e8828SBen Widawsky 402229e8828SBen Widawsky if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 40359f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox ready"); 4044f195ee7SDan Williams return -ETIMEDOUT; 4054f195ee7SDan Williams } 4064f195ee7SDan Williams 4074f195ee7SDan Williams /* 4084f195ee7SDan Williams * A command may be in flight from a previous driver instance, 4094f195ee7SDan Williams * think kexec, do one doorbell wait so that 4104f195ee7SDan Williams * __cxl_pci_mbox_send_cmd() can assume that it is the only 4114f195ee7SDan Williams * source for future doorbell busy events. 4124f195ee7SDan Williams */ 4134f195ee7SDan Williams if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 41459f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox idle"); 4154f195ee7SDan Williams return -ETIMEDOUT; 416229e8828SBen Widawsky } 41721e9f767SBen Widawsky 41859f8d151SDan Williams mds->mbox_send = cxl_pci_mbox_send; 41959f8d151SDan Williams mds->payload_size = 42021e9f767SBen Widawsky 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 42121e9f767SBen Widawsky 42221e9f767SBen Widawsky /* 42321e9f767SBen Widawsky * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 42421e9f767SBen Widawsky * 42521e9f767SBen Widawsky * If the size is too small, mandatory commands will not work and so 42621e9f767SBen Widawsky * there's no point in going forward. If the size is too large, there's 42721e9f767SBen Widawsky * no harm is soft limiting it. 42821e9f767SBen Widawsky */ 42959f8d151SDan Williams mds->payload_size = min_t(size_t, mds->payload_size, SZ_1M); 43059f8d151SDan Williams if (mds->payload_size < 256) { 43159f8d151SDan Williams dev_err(dev, "Mailbox is too small (%zub)", 43259f8d151SDan Williams mds->payload_size); 43321e9f767SBen Widawsky return -ENXIO; 43421e9f767SBen Widawsky } 43521e9f767SBen Widawsky 43659f8d151SDan Williams dev_dbg(dev, "Mailbox payload sized %zu", mds->payload_size); 43721e9f767SBen Widawsky 438aeaefabcSDan Williams rcuwait_init(&mds->mbox_wait); 439ccadf131SDavidlohr Bueso 440ccadf131SDavidlohr Bueso if (cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) { 441ccadf131SDavidlohr Bueso u32 ctrl; 442ccadf131SDavidlohr Bueso int irq, msgnum; 443ccadf131SDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 444ccadf131SDavidlohr Bueso 445ccadf131SDavidlohr Bueso msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 446ccadf131SDavidlohr Bueso irq = pci_irq_vector(pdev, msgnum); 447ccadf131SDavidlohr Bueso if (irq < 0) 448ccadf131SDavidlohr Bueso goto mbox_poll; 449ccadf131SDavidlohr Bueso 450ccadf131SDavidlohr Bueso if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq, NULL)) 451ccadf131SDavidlohr Bueso goto mbox_poll; 452ccadf131SDavidlohr Bueso 453ccadf131SDavidlohr Bueso /* enable background command mbox irq support */ 454ccadf131SDavidlohr Bueso ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 455ccadf131SDavidlohr Bueso ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 456ccadf131SDavidlohr Bueso writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 457ccadf131SDavidlohr Bueso 458ccadf131SDavidlohr Bueso return 0; 459ccadf131SDavidlohr Bueso } 460ccadf131SDavidlohr Bueso 461ccadf131SDavidlohr Bueso mbox_poll: 462aeaefabcSDan Williams mds->security.poll = true; 463aeaefabcSDan Williams INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); 4640c36b6adSDavidlohr Bueso 465ccadf131SDavidlohr Bueso dev_dbg(cxlds->dev, "Mailbox interrupts are unsupported"); 46621e9f767SBen Widawsky return 0; 46721e9f767SBen Widawsky } 46821e9f767SBen Widawsky 469a261e9a1SDan Williams static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) 4701b0a1a2aSBen Widawsky { 4717dc7a64dSBen Widawsky struct device *dev = &pdev->dev; 4721b0a1a2aSBen Widawsky 4736c7f4f1eSDan Williams map->base = ioremap(map->resource, map->max_size); 4746c7f4f1eSDan Williams if (!map->base) { 47521e9f767SBen Widawsky dev_err(dev, "failed to map registers\n"); 476a261e9a1SDan Williams return -ENOMEM; 47721e9f767SBen Widawsky } 47821e9f767SBen Widawsky 4796c7f4f1eSDan Williams dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource); 480a261e9a1SDan Williams return 0; 48130af9729SIra Weiny } 48230af9729SIra Weiny 483a261e9a1SDan Williams static void cxl_unmap_regblock(struct pci_dev *pdev, 484a261e9a1SDan Williams struct cxl_register_map *map) 48530af9729SIra Weiny { 4866c7f4f1eSDan Williams iounmap(map->base); 487a261e9a1SDan Williams map->base = NULL; 48821e9f767SBen Widawsky } 48921e9f767SBen Widawsky 490a261e9a1SDan Williams static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map) 49130af9729SIra Weiny { 49208422378SBen Widawsky struct cxl_component_reg_map *comp_map; 49330af9729SIra Weiny struct cxl_device_reg_map *dev_map; 4947dc7a64dSBen Widawsky struct device *dev = &pdev->dev; 495a261e9a1SDan Williams void __iomem *base = map->base; 49630af9729SIra Weiny 49730af9729SIra Weiny switch (map->reg_type) { 49808422378SBen Widawsky case CXL_REGLOC_RBI_COMPONENT: 49908422378SBen Widawsky comp_map = &map->component_map; 50008422378SBen Widawsky cxl_probe_component_regs(dev, base, comp_map); 50108422378SBen Widawsky if (!comp_map->hdm_decoder.valid) { 50208422378SBen Widawsky dev_err(dev, "HDM decoder registers not found\n"); 50308422378SBen Widawsky return -ENXIO; 50408422378SBen Widawsky } 50508422378SBen Widawsky 506bd09626bSDan Williams if (!comp_map->ras.valid) 507bd09626bSDan Williams dev_dbg(dev, "RAS registers not found\n"); 508bd09626bSDan Williams 50908422378SBen Widawsky dev_dbg(dev, "Set up component registers\n"); 51008422378SBen Widawsky break; 51130af9729SIra Weiny case CXL_REGLOC_RBI_MEMDEV: 51230af9729SIra Weiny dev_map = &map->device_map; 51330af9729SIra Weiny cxl_probe_device_regs(dev, base, dev_map); 51430af9729SIra Weiny if (!dev_map->status.valid || !dev_map->mbox.valid || 51530af9729SIra Weiny !dev_map->memdev.valid) { 51630af9729SIra Weiny dev_err(dev, "registers not found: %s%s%s\n", 51730af9729SIra Weiny !dev_map->status.valid ? "status " : "", 518da582aa5SLi Qiang (Johnny Li) !dev_map->mbox.valid ? "mbox " : "", 519da582aa5SLi Qiang (Johnny Li) !dev_map->memdev.valid ? "memdev " : ""); 52030af9729SIra Weiny return -ENXIO; 52130af9729SIra Weiny } 52230af9729SIra Weiny 52330af9729SIra Weiny dev_dbg(dev, "Probing device registers...\n"); 52430af9729SIra Weiny break; 52530af9729SIra Weiny default: 52630af9729SIra Weiny break; 52730af9729SIra Weiny } 52830af9729SIra Weiny 52930af9729SIra Weiny return 0; 53030af9729SIra Weiny } 53130af9729SIra Weiny 53285afc317SBen Widawsky static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 53385afc317SBen Widawsky struct cxl_register_map *map) 53485afc317SBen Widawsky { 53585afc317SBen Widawsky int rc; 53685afc317SBen Widawsky 53785afc317SBen Widawsky rc = cxl_find_regblock(pdev, type, map); 53885afc317SBen Widawsky if (rc) 53985afc317SBen Widawsky return rc; 54085afc317SBen Widawsky 54185afc317SBen Widawsky rc = cxl_map_regblock(pdev, map); 54285afc317SBen Widawsky if (rc) 54385afc317SBen Widawsky return rc; 54485afc317SBen Widawsky 54585afc317SBen Widawsky rc = cxl_probe_regs(pdev, map); 546a261e9a1SDan Williams cxl_unmap_regblock(pdev, map); 5475b68705dSBen Widawsky 54885afc317SBen Widawsky return rc; 5491d5a4159SBen Widawsky } 5501d5a4159SBen Widawsky 5510a19bfc8SDan Williams /* 5520a19bfc8SDan Williams * Assume that any RCIEP that emits the CXL memory expander class code 5530a19bfc8SDan Williams * is an RCD 5540a19bfc8SDan Williams */ 5550a19bfc8SDan Williams static bool is_cxl_restricted(struct pci_dev *pdev) 5560a19bfc8SDan Williams { 5570a19bfc8SDan Williams return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 5580a19bfc8SDan Williams } 5590a19bfc8SDan Williams 560248529edSDave Jiang static int cxl_pci_ras_unmask(struct pci_dev *pdev) 561248529edSDave Jiang { 562248529edSDave Jiang struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 563248529edSDave Jiang struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 564248529edSDave Jiang void __iomem *addr; 565248529edSDave Jiang u32 orig_val, val, mask; 566248529edSDave Jiang u16 cap; 567248529edSDave Jiang int rc; 568248529edSDave Jiang 569248529edSDave Jiang if (!cxlds->regs.ras) { 570248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS registers.\n"); 571248529edSDave Jiang return 0; 572248529edSDave Jiang } 573248529edSDave Jiang 574248529edSDave Jiang /* BIOS has CXL error control */ 575248529edSDave Jiang if (!host_bridge->native_cxl_error) 576248529edSDave Jiang return -ENXIO; 577248529edSDave Jiang 578248529edSDave Jiang rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 579248529edSDave Jiang if (rc) 580248529edSDave Jiang return rc; 581248529edSDave Jiang 582248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_URRE) { 583248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 584248529edSDave Jiang orig_val = readl(addr); 585248529edSDave Jiang 586f3c8a37aSDan Williams mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | 587f3c8a37aSDan Williams CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 588248529edSDave Jiang val = orig_val & ~mask; 589248529edSDave Jiang writel(val, addr); 590248529edSDave Jiang dev_dbg(&pdev->dev, 591248529edSDave Jiang "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 592248529edSDave Jiang orig_val, val); 593248529edSDave Jiang } 594248529edSDave Jiang 595248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_CERE) { 596248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 597248529edSDave Jiang orig_val = readl(addr); 598248529edSDave Jiang val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 599248529edSDave Jiang writel(val, addr); 600248529edSDave Jiang dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 601248529edSDave Jiang orig_val, val); 602248529edSDave Jiang } 603248529edSDave Jiang 604248529edSDave Jiang return 0; 6052905cb52SDan Williams } 6062905cb52SDan Williams 6076ebe28f9SIra Weiny static void free_event_buf(void *buf) 6086ebe28f9SIra Weiny { 6096ebe28f9SIra Weiny kvfree(buf); 6106ebe28f9SIra Weiny } 6116ebe28f9SIra Weiny 6126ebe28f9SIra Weiny /* 6136ebe28f9SIra Weiny * There is a single buffer for reading event logs from the mailbox. All logs 61459f8d151SDan Williams * share this buffer protected by the mds->event_log_lock. 6156ebe28f9SIra Weiny */ 61659f8d151SDan Williams static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) 6176ebe28f9SIra Weiny { 6186ebe28f9SIra Weiny struct cxl_get_event_payload *buf; 6196ebe28f9SIra Weiny 62059f8d151SDan Williams buf = kvmalloc(mds->payload_size, GFP_KERNEL); 6216ebe28f9SIra Weiny if (!buf) 6226ebe28f9SIra Weiny return -ENOMEM; 62359f8d151SDan Williams mds->event.buf = buf; 6246ebe28f9SIra Weiny 62559f8d151SDan Williams return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); 6266ebe28f9SIra Weiny } 6276ebe28f9SIra Weiny 628a49aa814SDavidlohr Bueso static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 629a49aa814SDavidlohr Bueso { 630a49aa814SDavidlohr Bueso int nvecs; 631a49aa814SDavidlohr Bueso 632a49aa814SDavidlohr Bueso /* 633a49aa814SDavidlohr Bueso * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 634a49aa814SDavidlohr Bueso * not generate INTx messages if that function participates in 635a49aa814SDavidlohr Bueso * CXL.cache or CXL.mem. 636a49aa814SDavidlohr Bueso * 637a49aa814SDavidlohr Bueso * Additionally pci_alloc_irq_vectors() handles calling 638a49aa814SDavidlohr Bueso * pci_free_irq_vectors() automatically despite not being called 639a49aa814SDavidlohr Bueso * pcim_*. See pci_setup_msi_context(). 640a49aa814SDavidlohr Bueso */ 641a49aa814SDavidlohr Bueso nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 642a49aa814SDavidlohr Bueso PCI_IRQ_MSIX | PCI_IRQ_MSI); 643a49aa814SDavidlohr Bueso if (nvecs < 1) { 644a49aa814SDavidlohr Bueso dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 645a49aa814SDavidlohr Bueso return -ENXIO; 646a49aa814SDavidlohr Bueso } 647a49aa814SDavidlohr Bueso return 0; 648a49aa814SDavidlohr Bueso } 649a49aa814SDavidlohr Bueso 650a49aa814SDavidlohr Bueso static irqreturn_t cxl_event_thread(int irq, void *id) 651a49aa814SDavidlohr Bueso { 652a49aa814SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 653a49aa814SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 65459f8d151SDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 655a49aa814SDavidlohr Bueso u32 status; 656a49aa814SDavidlohr Bueso 657a49aa814SDavidlohr Bueso do { 658a49aa814SDavidlohr Bueso /* 659a49aa814SDavidlohr Bueso * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 660a49aa814SDavidlohr Bueso * ignore the reserved upper 32 bits 661a49aa814SDavidlohr Bueso */ 662a49aa814SDavidlohr Bueso status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 663a49aa814SDavidlohr Bueso /* Ignore logs unknown to the driver */ 664a49aa814SDavidlohr Bueso status &= CXLDEV_EVENT_STATUS_ALL; 665a49aa814SDavidlohr Bueso if (!status) 666a49aa814SDavidlohr Bueso break; 66759f8d151SDan Williams cxl_mem_get_event_records(mds, status); 668a49aa814SDavidlohr Bueso cond_resched(); 669a49aa814SDavidlohr Bueso } while (status); 670a49aa814SDavidlohr Bueso 671a49aa814SDavidlohr Bueso return IRQ_HANDLED; 672a49aa814SDavidlohr Bueso } 673a49aa814SDavidlohr Bueso 674a49aa814SDavidlohr Bueso static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 675a49aa814SDavidlohr Bueso { 6769f7a320dSDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 677a49aa814SDavidlohr Bueso int irq; 678a49aa814SDavidlohr Bueso 679a49aa814SDavidlohr Bueso if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 680a49aa814SDavidlohr Bueso return -ENXIO; 681a49aa814SDavidlohr Bueso 682a49aa814SDavidlohr Bueso irq = pci_irq_vector(pdev, 683a49aa814SDavidlohr Bueso FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 684a49aa814SDavidlohr Bueso if (irq < 0) 685a49aa814SDavidlohr Bueso return irq; 686a49aa814SDavidlohr Bueso 6879f7a320dSDavidlohr Bueso return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 688a49aa814SDavidlohr Bueso } 689a49aa814SDavidlohr Bueso 69059f8d151SDan Williams static int cxl_event_get_int_policy(struct cxl_memdev_state *mds, 691a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 692a49aa814SDavidlohr Bueso { 693a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd = { 694a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 695a49aa814SDavidlohr Bueso .payload_out = policy, 696a49aa814SDavidlohr Bueso .size_out = sizeof(*policy), 697a49aa814SDavidlohr Bueso }; 698a49aa814SDavidlohr Bueso int rc; 699a49aa814SDavidlohr Bueso 70059f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 701a49aa814SDavidlohr Bueso if (rc < 0) 70259f8d151SDan Williams dev_err(mds->cxlds.dev, 70359f8d151SDan Williams "Failed to get event interrupt policy : %d", rc); 704a49aa814SDavidlohr Bueso 705a49aa814SDavidlohr Bueso return rc; 706a49aa814SDavidlohr Bueso } 707a49aa814SDavidlohr Bueso 70859f8d151SDan Williams static int cxl_event_config_msgnums(struct cxl_memdev_state *mds, 709a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 710a49aa814SDavidlohr Bueso { 711a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd; 712a49aa814SDavidlohr Bueso int rc; 713a49aa814SDavidlohr Bueso 714a49aa814SDavidlohr Bueso *policy = (struct cxl_event_interrupt_policy) { 715a49aa814SDavidlohr Bueso .info_settings = CXL_INT_MSI_MSIX, 716a49aa814SDavidlohr Bueso .warn_settings = CXL_INT_MSI_MSIX, 717a49aa814SDavidlohr Bueso .failure_settings = CXL_INT_MSI_MSIX, 718a49aa814SDavidlohr Bueso .fatal_settings = CXL_INT_MSI_MSIX, 719a49aa814SDavidlohr Bueso }; 720a49aa814SDavidlohr Bueso 721a49aa814SDavidlohr Bueso mbox_cmd = (struct cxl_mbox_cmd) { 722a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 723a49aa814SDavidlohr Bueso .payload_in = policy, 724a49aa814SDavidlohr Bueso .size_in = sizeof(*policy), 725a49aa814SDavidlohr Bueso }; 726a49aa814SDavidlohr Bueso 72759f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 728a49aa814SDavidlohr Bueso if (rc < 0) { 72959f8d151SDan Williams dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d", 730a49aa814SDavidlohr Bueso rc); 731a49aa814SDavidlohr Bueso return rc; 732a49aa814SDavidlohr Bueso } 733a49aa814SDavidlohr Bueso 734a49aa814SDavidlohr Bueso /* Retrieve final interrupt settings */ 73559f8d151SDan Williams return cxl_event_get_int_policy(mds, policy); 736a49aa814SDavidlohr Bueso } 737a49aa814SDavidlohr Bueso 73859f8d151SDan Williams static int cxl_event_irqsetup(struct cxl_memdev_state *mds) 739a49aa814SDavidlohr Bueso { 74059f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 741a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 742a49aa814SDavidlohr Bueso int rc; 743a49aa814SDavidlohr Bueso 74459f8d151SDan Williams rc = cxl_event_config_msgnums(mds, &policy); 745a49aa814SDavidlohr Bueso if (rc) 746a49aa814SDavidlohr Bueso return rc; 747a49aa814SDavidlohr Bueso 748a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.info_settings); 749a49aa814SDavidlohr Bueso if (rc) { 750a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 751a49aa814SDavidlohr Bueso return rc; 752a49aa814SDavidlohr Bueso } 753a49aa814SDavidlohr Bueso 754a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.warn_settings); 755a49aa814SDavidlohr Bueso if (rc) { 756a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 757a49aa814SDavidlohr Bueso return rc; 758a49aa814SDavidlohr Bueso } 759a49aa814SDavidlohr Bueso 760a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.failure_settings); 761a49aa814SDavidlohr Bueso if (rc) { 762a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 763a49aa814SDavidlohr Bueso return rc; 764a49aa814SDavidlohr Bueso } 765a49aa814SDavidlohr Bueso 766a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 767a49aa814SDavidlohr Bueso if (rc) { 768a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 769a49aa814SDavidlohr Bueso return rc; 770a49aa814SDavidlohr Bueso } 771a49aa814SDavidlohr Bueso 772a49aa814SDavidlohr Bueso return 0; 773a49aa814SDavidlohr Bueso } 774a49aa814SDavidlohr Bueso 775a49aa814SDavidlohr Bueso static bool cxl_event_int_is_fw(u8 setting) 776a49aa814SDavidlohr Bueso { 777a49aa814SDavidlohr Bueso u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 778a49aa814SDavidlohr Bueso 779a49aa814SDavidlohr Bueso return mode == CXL_INT_FW; 780a49aa814SDavidlohr Bueso } 781a49aa814SDavidlohr Bueso 782a49aa814SDavidlohr Bueso static int cxl_event_config(struct pci_host_bridge *host_bridge, 78359f8d151SDan Williams struct cxl_memdev_state *mds) 784a49aa814SDavidlohr Bueso { 785a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 786a49aa814SDavidlohr Bueso int rc; 787a49aa814SDavidlohr Bueso 788a49aa814SDavidlohr Bueso /* 789a49aa814SDavidlohr Bueso * When BIOS maintains CXL error reporting control, it will process 790a49aa814SDavidlohr Bueso * event records. Only one agent can do so. 791a49aa814SDavidlohr Bueso */ 792a49aa814SDavidlohr Bueso if (!host_bridge->native_cxl_error) 793a49aa814SDavidlohr Bueso return 0; 794a49aa814SDavidlohr Bueso 79559f8d151SDan Williams rc = cxl_mem_alloc_event_buf(mds); 796a49aa814SDavidlohr Bueso if (rc) 797a49aa814SDavidlohr Bueso return rc; 798a49aa814SDavidlohr Bueso 79959f8d151SDan Williams rc = cxl_event_get_int_policy(mds, &policy); 800a49aa814SDavidlohr Bueso if (rc) 801a49aa814SDavidlohr Bueso return rc; 802a49aa814SDavidlohr Bueso 803a49aa814SDavidlohr Bueso if (cxl_event_int_is_fw(policy.info_settings) || 804a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.warn_settings) || 805a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.failure_settings) || 806a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.fatal_settings)) { 80759f8d151SDan Williams dev_err(mds->cxlds.dev, 80859f8d151SDan Williams "FW still in control of Event Logs despite _OSC settings\n"); 809a49aa814SDavidlohr Bueso return -EBUSY; 810a49aa814SDavidlohr Bueso } 811a49aa814SDavidlohr Bueso 81259f8d151SDan Williams rc = cxl_event_irqsetup(mds); 813a49aa814SDavidlohr Bueso if (rc) 814a49aa814SDavidlohr Bueso return rc; 815a49aa814SDavidlohr Bueso 81659f8d151SDan Williams cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 817a49aa814SDavidlohr Bueso 818a49aa814SDavidlohr Bueso return 0; 819a49aa814SDavidlohr Bueso } 820a49aa814SDavidlohr Bueso 821ed97afb5SBen Widawsky static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 82221e9f767SBen Widawsky { 8236ebe28f9SIra Weiny struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 82459f8d151SDan Williams struct cxl_memdev_state *mds; 82559f8d151SDan Williams struct cxl_dev_state *cxlds; 82685afc317SBen Widawsky struct cxl_register_map map; 82721083f51SDan Williams struct cxl_memdev *cxlmd; 8281d5a4159SBen Widawsky int rc; 82921e9f767SBen Widawsky 8305a2328f4SDan Williams /* 8315a2328f4SDan Williams * Double check the anonymous union trickery in struct cxl_regs 8325a2328f4SDan Williams * FIXME switch to struct_group() 8335a2328f4SDan Williams */ 8345a2328f4SDan Williams BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 8355a2328f4SDan Williams offsetof(struct cxl_regs, device_regs.memdev)); 8365a2328f4SDan Williams 83721e9f767SBen Widawsky rc = pcim_enable_device(pdev); 83821e9f767SBen Widawsky if (rc) 83921e9f767SBen Widawsky return rc; 840a49aa814SDavidlohr Bueso pci_set_master(pdev); 84121e9f767SBen Widawsky 84259f8d151SDan Williams mds = cxl_memdev_state_create(&pdev->dev); 84359f8d151SDan Williams if (IS_ERR(mds)) 84459f8d151SDan Williams return PTR_ERR(mds); 84559f8d151SDan Williams cxlds = &mds->cxlds; 8462905cb52SDan Williams pci_set_drvdata(pdev, cxlds); 8471b0a1a2aSBen Widawsky 8480a19bfc8SDan Williams cxlds->rcd = is_cxl_restricted(pdev); 849bcc79ea3SDan Williams cxlds->serial = pci_get_dsn(pdev); 85006e279e5SBen Widawsky cxlds->cxl_dvsec = pci_find_dvsec_capability( 85106e279e5SBen Widawsky pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 85206e279e5SBen Widawsky if (!cxlds->cxl_dvsec) 85306e279e5SBen Widawsky dev_warn(&pdev->dev, 85406e279e5SBen Widawsky "Device DVSEC not present, skip CXL.mem init\n"); 85506e279e5SBen Widawsky 85685afc317SBen Widawsky rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 85785afc317SBen Widawsky if (rc) 85885afc317SBen Widawsky return rc; 85985afc317SBen Widawsky 8606c7f4f1eSDan Williams rc = cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map); 86121e9f767SBen Widawsky if (rc) 86221e9f767SBen Widawsky return rc; 86321e9f767SBen Widawsky 8644112a08dSBen Widawsky /* 8654112a08dSBen Widawsky * If the component registers can't be found, the cxl_pci driver may 8664112a08dSBen Widawsky * still be useful for management functions so don't return an error. 8674112a08dSBen Widawsky */ 8684112a08dSBen Widawsky cxlds->component_reg_phys = CXL_RESOURCE_NONE; 8694112a08dSBen Widawsky rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 8704112a08dSBen Widawsky if (rc) 8714112a08dSBen Widawsky dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 8724112a08dSBen Widawsky 8736c7f4f1eSDan Williams cxlds->component_reg_phys = map.resource; 8744112a08dSBen Widawsky 875bd09626bSDan Williams rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, 876bd09626bSDan Williams &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); 877bd09626bSDan Williams if (rc) 878bd09626bSDan Williams dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 879bd09626bSDan Williams 880e764f122SDave Jiang rc = cxl_await_media_ready(cxlds); 881e764f122SDave Jiang if (rc == 0) 882e764f122SDave Jiang cxlds->media_ready = true; 883e764f122SDave Jiang else 884e764f122SDave Jiang dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 885e764f122SDave Jiang 886f279d0bcSDavidlohr Bueso rc = cxl_alloc_irq_vectors(pdev); 887f279d0bcSDavidlohr Bueso if (rc) 888f279d0bcSDavidlohr Bueso return rc; 889f279d0bcSDavidlohr Bueso 89059f8d151SDan Williams rc = cxl_pci_setup_mailbox(mds); 89121e9f767SBen Widawsky if (rc) 89221e9f767SBen Widawsky return rc; 89321e9f767SBen Widawsky 89459f8d151SDan Williams rc = cxl_enumerate_cmds(mds); 89521e9f767SBen Widawsky if (rc) 89621e9f767SBen Widawsky return rc; 89721e9f767SBen Widawsky 89859f8d151SDan Williams rc = cxl_set_timestamp(mds); 899fa884345SJonathan Cameron if (rc) 900fa884345SJonathan Cameron return rc; 901fa884345SJonathan Cameron 90259f8d151SDan Williams rc = cxl_poison_state_init(mds); 903d0abf578SAlison Schofield if (rc) 904d0abf578SAlison Schofield return rc; 905d0abf578SAlison Schofield 90659f8d151SDan Williams rc = cxl_dev_state_identify(mds); 90721e9f767SBen Widawsky if (rc) 90821e9f767SBen Widawsky return rc; 90921e9f767SBen Widawsky 91059f8d151SDan Williams rc = cxl_mem_create_range_info(mds); 911f847502aSIra Weiny if (rc) 912f847502aSIra Weiny return rc; 913f847502aSIra Weiny 9145e2411aeSIra Weiny cxlmd = devm_cxl_add_memdev(cxlds); 91521083f51SDan Williams if (IS_ERR(cxlmd)) 91621083f51SDan Williams return PTR_ERR(cxlmd); 91721083f51SDan Williams 918aeaefabcSDan Williams rc = cxl_memdev_setup_fw_upload(mds); 919*9521875bSVishal Verma if (rc) 920*9521875bSVishal Verma return rc; 921*9521875bSVishal Verma 92259f8d151SDan Williams rc = cxl_event_config(host_bridge, mds); 9236ebe28f9SIra Weiny if (rc) 9246ebe28f9SIra Weiny return rc; 9256ebe28f9SIra Weiny 926248529edSDave Jiang rc = cxl_pci_ras_unmask(pdev); 9272905cb52SDan Williams if (rc) 928248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 929248529edSDave Jiang 9302905cb52SDan Williams pci_save_state(pdev); 9312905cb52SDan Williams 93221083f51SDan Williams return rc; 93321e9f767SBen Widawsky } 93421e9f767SBen Widawsky 93521e9f767SBen Widawsky static const struct pci_device_id cxl_mem_pci_tbl[] = { 93621e9f767SBen Widawsky /* PCI class code for CXL.mem Type-3 Devices */ 93721e9f767SBen Widawsky { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 93821e9f767SBen Widawsky { /* terminate list */ }, 93921e9f767SBen Widawsky }; 94021e9f767SBen Widawsky MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 94121e9f767SBen Widawsky 9422905cb52SDan Williams static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 9432905cb52SDan Williams { 9442905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9452905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9462905cb52SDan Williams struct device *dev = &cxlmd->dev; 9472905cb52SDan Williams 9482905cb52SDan Williams dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 9492905cb52SDan Williams dev_name(dev)); 9502905cb52SDan Williams pci_restore_state(pdev); 9512905cb52SDan Williams if (device_attach(dev) <= 0) 9522905cb52SDan Williams return PCI_ERS_RESULT_DISCONNECT; 9532905cb52SDan Williams return PCI_ERS_RESULT_RECOVERED; 9542905cb52SDan Williams } 9552905cb52SDan Williams 9562905cb52SDan Williams static void cxl_error_resume(struct pci_dev *pdev) 9572905cb52SDan Williams { 9582905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9592905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9602905cb52SDan Williams struct device *dev = &cxlmd->dev; 9612905cb52SDan Williams 9622905cb52SDan Williams dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 9632905cb52SDan Williams dev->driver ? "successful" : "failed"); 9642905cb52SDan Williams } 9652905cb52SDan Williams 9662905cb52SDan Williams static const struct pci_error_handlers cxl_error_handlers = { 9672905cb52SDan Williams .error_detected = cxl_error_detected, 9682905cb52SDan Williams .slot_reset = cxl_slot_reset, 9692905cb52SDan Williams .resume = cxl_error_resume, 9706155ccc9SDave Jiang .cor_error_detected = cxl_cor_error_detected, 9712905cb52SDan Williams }; 9722905cb52SDan Williams 973ed97afb5SBen Widawsky static struct pci_driver cxl_pci_driver = { 97421e9f767SBen Widawsky .name = KBUILD_MODNAME, 97521e9f767SBen Widawsky .id_table = cxl_mem_pci_tbl, 976ed97afb5SBen Widawsky .probe = cxl_pci_probe, 9772905cb52SDan Williams .err_handler = &cxl_error_handlers, 97821e9f767SBen Widawsky .driver = { 97921e9f767SBen Widawsky .probe_type = PROBE_PREFER_ASYNCHRONOUS, 98021e9f767SBen Widawsky }, 98121e9f767SBen Widawsky }; 98221e9f767SBen Widawsky 98321e9f767SBen Widawsky MODULE_LICENSE("GPL v2"); 984ed97afb5SBen Widawsky module_pci_driver(cxl_pci_driver); 98521e9f767SBen Widawsky MODULE_IMPORT_NS(CXL); 986