121e9f767SBen Widawsky // SPDX-License-Identifier: GPL-2.0-only 221e9f767SBen Widawsky /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 34faf31b4SDan Williams #include <linux/io-64-nonatomic-lo-hi.h> 4229e8828SBen Widawsky #include <linux/moduleparam.h> 521e9f767SBen Widawsky #include <linux/module.h> 6229e8828SBen Widawsky #include <linux/delay.h> 721e9f767SBen Widawsky #include <linux/sizes.h> 821e9f767SBen Widawsky #include <linux/mutex.h> 930af9729SIra Weiny #include <linux/list.h> 1021e9f767SBen Widawsky #include <linux/pci.h> 112905cb52SDan Williams #include <linux/aer.h> 1221e9f767SBen Widawsky #include <linux/io.h> 135161a55cSBen Widawsky #include "cxlmem.h" 14af9cae9fSDan Williams #include "cxlpci.h" 1521e9f767SBen Widawsky #include "cxl.h" 161ad3f701SJonathan Cameron #include "pmu.h" 1721e9f767SBen Widawsky 1821e9f767SBen Widawsky /** 1921e9f767SBen Widawsky * DOC: cxl pci 2021e9f767SBen Widawsky * 2121e9f767SBen Widawsky * This implements the PCI exclusive functionality for a CXL device as it is 2221e9f767SBen Widawsky * defined by the Compute Express Link specification. CXL devices may surface 23ed97afb5SBen Widawsky * certain functionality even if it isn't CXL enabled. While this driver is 24ed97afb5SBen Widawsky * focused around the PCI specific aspects of a CXL device, it binds to the 25ed97afb5SBen Widawsky * specific CXL memory device class code, and therefore the implementation of 26ed97afb5SBen Widawsky * cxl_pci is focused around CXL memory devices. 2721e9f767SBen Widawsky * 2821e9f767SBen Widawsky * The driver has several responsibilities, mainly: 2921e9f767SBen Widawsky * - Create the memX device and register on the CXL bus. 3021e9f767SBen Widawsky * - Enumerate device's register interface and map them. 31ed97afb5SBen Widawsky * - Registers nvdimm bridge device with cxl_core. 32ed97afb5SBen Widawsky * - Registers a CXL mailbox with cxl_core. 3321e9f767SBen Widawsky */ 3421e9f767SBen Widawsky 355e2411aeSIra Weiny #define cxl_doorbell_busy(cxlds) \ 365e2411aeSIra Weiny (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 3721e9f767SBen Widawsky CXLDEV_MBOX_CTRL_DOORBELL) 3821e9f767SBen Widawsky 3921e9f767SBen Widawsky /* CXL 2.0 - 8.2.8.4 */ 4021e9f767SBen Widawsky #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 4121e9f767SBen Widawsky 42229e8828SBen Widawsky /* 43229e8828SBen Widawsky * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 44229e8828SBen Widawsky * dictate how long to wait for the mailbox to become ready. The new 45229e8828SBen Widawsky * field allows the device to tell software the amount of time to wait 46229e8828SBen Widawsky * before mailbox ready. This field per the spec theoretically allows 47229e8828SBen Widawsky * for up to 255 seconds. 255 seconds is unreasonably long, its longer 48229e8828SBen Widawsky * than the maximum SATA port link recovery wait. Default to 60 seconds 49229e8828SBen Widawsky * until someone builds a CXL device that needs more time in practice. 50229e8828SBen Widawsky */ 51229e8828SBen Widawsky static unsigned short mbox_ready_timeout = 60; 52229e8828SBen Widawsky module_param(mbox_ready_timeout, ushort, 0644); 532e4ba0ecSDan Williams MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 54229e8828SBen Widawsky 555e2411aeSIra Weiny static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 5621e9f767SBen Widawsky { 5721e9f767SBen Widawsky const unsigned long start = jiffies; 5821e9f767SBen Widawsky unsigned long end = start; 5921e9f767SBen Widawsky 605e2411aeSIra Weiny while (cxl_doorbell_busy(cxlds)) { 6121e9f767SBen Widawsky end = jiffies; 6221e9f767SBen Widawsky 6321e9f767SBen Widawsky if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 6421e9f767SBen Widawsky /* Check again in case preempted before timeout test */ 655e2411aeSIra Weiny if (!cxl_doorbell_busy(cxlds)) 6621e9f767SBen Widawsky break; 6721e9f767SBen Widawsky return -ETIMEDOUT; 6821e9f767SBen Widawsky } 6921e9f767SBen Widawsky cpu_relax(); 7021e9f767SBen Widawsky } 7121e9f767SBen Widawsky 725e2411aeSIra Weiny dev_dbg(cxlds->dev, "Doorbell wait took %dms", 7321e9f767SBen Widawsky jiffies_to_msecs(end) - jiffies_to_msecs(start)); 7421e9f767SBen Widawsky return 0; 7521e9f767SBen Widawsky } 7621e9f767SBen Widawsky 774f195ee7SDan Williams #define cxl_err(dev, status, msg) \ 784f195ee7SDan Williams dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 794f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 804f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8121e9f767SBen Widawsky 824f195ee7SDan Williams #define cxl_cmd_err(dev, cmd, status, msg) \ 834f195ee7SDan Williams dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 844f195ee7SDan Williams (cmd)->opcode, \ 854f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 864f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8721e9f767SBen Widawsky 889f7a320dSDavidlohr Bueso struct cxl_dev_id { 899f7a320dSDavidlohr Bueso struct cxl_dev_state *cxlds; 909f7a320dSDavidlohr Bueso }; 919f7a320dSDavidlohr Bueso 929f7a320dSDavidlohr Bueso static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 939f7a320dSDavidlohr Bueso irq_handler_t handler, irq_handler_t thread_fn) 949f7a320dSDavidlohr Bueso { 959f7a320dSDavidlohr Bueso struct device *dev = cxlds->dev; 969f7a320dSDavidlohr Bueso struct cxl_dev_id *dev_id; 979f7a320dSDavidlohr Bueso 989f7a320dSDavidlohr Bueso /* dev_id must be globally unique and must contain the cxlds */ 999f7a320dSDavidlohr Bueso dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 1009f7a320dSDavidlohr Bueso if (!dev_id) 1019f7a320dSDavidlohr Bueso return -ENOMEM; 1029f7a320dSDavidlohr Bueso dev_id->cxlds = cxlds; 1039f7a320dSDavidlohr Bueso 1049f7a320dSDavidlohr Bueso return devm_request_threaded_irq(dev, irq, handler, thread_fn, 1059f7a320dSDavidlohr Bueso IRQF_SHARED | IRQF_ONESHOT, 1069f7a320dSDavidlohr Bueso NULL, dev_id); 1079f7a320dSDavidlohr Bueso } 1089f7a320dSDavidlohr Bueso 109ccadf131SDavidlohr Bueso static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 110ccadf131SDavidlohr Bueso { 111ccadf131SDavidlohr Bueso u64 reg; 112ccadf131SDavidlohr Bueso 113ccadf131SDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 114ccadf131SDavidlohr Bueso return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 115ccadf131SDavidlohr Bueso } 116ccadf131SDavidlohr Bueso 117ccadf131SDavidlohr Bueso static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 118ccadf131SDavidlohr Bueso { 1190c36b6adSDavidlohr Bueso u64 reg; 1200c36b6adSDavidlohr Bueso u16 opcode; 121ccadf131SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 122ccadf131SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 123aeaefabcSDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 124ccadf131SDavidlohr Bueso 1258ea9c33dSDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) 1268ea9c33dSDavidlohr Bueso return IRQ_NONE; 1278ea9c33dSDavidlohr Bueso 1280c36b6adSDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 1290c36b6adSDavidlohr Bueso opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 1300c36b6adSDavidlohr Bueso if (opcode == CXL_MBOX_OP_SANITIZE) { 131aeaefabcSDan Williams if (mds->security.sanitize_node) 132aeaefabcSDan Williams sysfs_notify_dirent(mds->security.sanitize_node); 13348dcdbb1SDavidlohr Bueso 1340c36b6adSDavidlohr Bueso dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 1350c36b6adSDavidlohr Bueso } else { 136ccadf131SDavidlohr Bueso /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 137aeaefabcSDan Williams rcuwait_wake_up(&mds->mbox_wait); 1380c36b6adSDavidlohr Bueso } 139ccadf131SDavidlohr Bueso 140ccadf131SDavidlohr Bueso return IRQ_HANDLED; 141ccadf131SDavidlohr Bueso } 142ccadf131SDavidlohr Bueso 1430c36b6adSDavidlohr Bueso /* 1440c36b6adSDavidlohr Bueso * Sanitization operation polling mode. 1450c36b6adSDavidlohr Bueso */ 1460c36b6adSDavidlohr Bueso static void cxl_mbox_sanitize_work(struct work_struct *work) 1470c36b6adSDavidlohr Bueso { 148aeaefabcSDan Williams struct cxl_memdev_state *mds = 149aeaefabcSDan Williams container_of(work, typeof(*mds), security.poll_dwork.work); 150aeaefabcSDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1510c36b6adSDavidlohr Bueso 152aeaefabcSDan Williams mutex_lock(&mds->mbox_mutex); 1530c36b6adSDavidlohr Bueso if (cxl_mbox_background_complete(cxlds)) { 154aeaefabcSDan Williams mds->security.poll_tmo_secs = 0; 1550c36b6adSDavidlohr Bueso put_device(cxlds->dev); 1560c36b6adSDavidlohr Bueso 157aeaefabcSDan Williams if (mds->security.sanitize_node) 158aeaefabcSDan Williams sysfs_notify_dirent(mds->security.sanitize_node); 15948dcdbb1SDavidlohr Bueso 1600c36b6adSDavidlohr Bueso dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 1610c36b6adSDavidlohr Bueso } else { 162aeaefabcSDan Williams int timeout = mds->security.poll_tmo_secs + 10; 1630c36b6adSDavidlohr Bueso 164aeaefabcSDan Williams mds->security.poll_tmo_secs = min(15 * 60, timeout); 165aeaefabcSDan Williams queue_delayed_work(system_wq, &mds->security.poll_dwork, 1660c36b6adSDavidlohr Bueso timeout * HZ); 1670c36b6adSDavidlohr Bueso } 168aeaefabcSDan Williams mutex_unlock(&mds->mbox_mutex); 1690c36b6adSDavidlohr Bueso } 1700c36b6adSDavidlohr Bueso 17121e9f767SBen Widawsky /** 172ed97afb5SBen Widawsky * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 17359f8d151SDan Williams * @mds: The memory device driver data 17421e9f767SBen Widawsky * @mbox_cmd: Command to send to the memory device. 17521e9f767SBen Widawsky * 17621e9f767SBen Widawsky * Context: Any context. Expects mbox_mutex to be held. 17721e9f767SBen Widawsky * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 17821e9f767SBen Widawsky * Caller should check the return code in @mbox_cmd to make sure it 17921e9f767SBen Widawsky * succeeded. 18021e9f767SBen Widawsky * 18121e9f767SBen Widawsky * This is a generic form of the CXL mailbox send command thus only using the 18221e9f767SBen Widawsky * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 18321e9f767SBen Widawsky * devices, and perhaps other types of CXL devices may have further information 18421e9f767SBen Widawsky * available upon error conditions. Driver facilities wishing to send mailbox 18521e9f767SBen Widawsky * commands should use the wrapper command. 18621e9f767SBen Widawsky * 18721e9f767SBen Widawsky * The CXL spec allows for up to two mailboxes. The intention is for the primary 18821e9f767SBen Widawsky * mailbox to be OS controlled and the secondary mailbox to be used by system 18921e9f767SBen Widawsky * firmware. This allows the OS and firmware to communicate with the device and 19021e9f767SBen Widawsky * not need to coordinate with each other. The driver only uses the primary 19121e9f767SBen Widawsky * mailbox. 19221e9f767SBen Widawsky */ 19359f8d151SDan Williams static int __cxl_pci_mbox_send_cmd(struct cxl_memdev_state *mds, 194b64955a9SDan Williams struct cxl_mbox_cmd *mbox_cmd) 19521e9f767SBen Widawsky { 19659f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1975e2411aeSIra Weiny void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 1985e2411aeSIra Weiny struct device *dev = cxlds->dev; 19921e9f767SBen Widawsky u64 cmd_reg, status_reg; 20021e9f767SBen Widawsky size_t out_len; 20121e9f767SBen Widawsky int rc; 20221e9f767SBen Widawsky 20359f8d151SDan Williams lockdep_assert_held(&mds->mbox_mutex); 20421e9f767SBen Widawsky 20521e9f767SBen Widawsky /* 20621e9f767SBen Widawsky * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 20721e9f767SBen Widawsky * 1. Caller reads MB Control Register to verify doorbell is clear 20821e9f767SBen Widawsky * 2. Caller writes Command Register 20921e9f767SBen Widawsky * 3. Caller writes Command Payload Registers if input payload is non-empty 21021e9f767SBen Widawsky * 4. Caller writes MB Control Register to set doorbell 21121e9f767SBen Widawsky * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 21221e9f767SBen Widawsky * 6. Caller reads MB Status Register to fetch Return code 21321e9f767SBen Widawsky * 7. If command successful, Caller reads Command Register to get Payload Length 21421e9f767SBen Widawsky * 8. If output payload is non-empty, host reads Command Payload Registers 21521e9f767SBen Widawsky * 21621e9f767SBen Widawsky * Hardware is free to do whatever it wants before the doorbell is rung, 21721e9f767SBen Widawsky * and isn't allowed to change anything after it clears the doorbell. As 21821e9f767SBen Widawsky * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 21921e9f767SBen Widawsky * also happen in any order (though some orders might not make sense). 22021e9f767SBen Widawsky */ 22121e9f767SBen Widawsky 22221e9f767SBen Widawsky /* #1 */ 2235e2411aeSIra Weiny if (cxl_doorbell_busy(cxlds)) { 2244f195ee7SDan Williams u64 md_status = 2254f195ee7SDan Williams readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2264f195ee7SDan Williams 2274f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 2284f195ee7SDan Williams "mailbox queue busy"); 22921e9f767SBen Widawsky return -EBUSY; 23021e9f767SBen Widawsky } 23121e9f767SBen Widawsky 2320c36b6adSDavidlohr Bueso /* 2330c36b6adSDavidlohr Bueso * With sanitize polling, hardware might be done and the poller still 2340c36b6adSDavidlohr Bueso * not be in sync. Ensure no new command comes in until so. Keep the 2350c36b6adSDavidlohr Bueso * hardware semantics and only allow device health status. 2360c36b6adSDavidlohr Bueso */ 237aeaefabcSDan Williams if (mds->security.poll_tmo_secs > 0) { 2380c36b6adSDavidlohr Bueso if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 2390c36b6adSDavidlohr Bueso return -EBUSY; 2400c36b6adSDavidlohr Bueso } 2410c36b6adSDavidlohr Bueso 24221e9f767SBen Widawsky cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 24321e9f767SBen Widawsky mbox_cmd->opcode); 24421e9f767SBen Widawsky if (mbox_cmd->size_in) { 24521e9f767SBen Widawsky if (WARN_ON(!mbox_cmd->payload_in)) 24621e9f767SBen Widawsky return -EINVAL; 24721e9f767SBen Widawsky 24821e9f767SBen Widawsky cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 24921e9f767SBen Widawsky mbox_cmd->size_in); 25021e9f767SBen Widawsky memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 25121e9f767SBen Widawsky } 25221e9f767SBen Widawsky 25321e9f767SBen Widawsky /* #2, #3 */ 2545e2411aeSIra Weiny writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 25521e9f767SBen Widawsky 25621e9f767SBen Widawsky /* #4 */ 257852db33cSRobert Richter dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 25821e9f767SBen Widawsky writel(CXLDEV_MBOX_CTRL_DOORBELL, 2595e2411aeSIra Weiny cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 26021e9f767SBen Widawsky 26121e9f767SBen Widawsky /* #5 */ 2625e2411aeSIra Weiny rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 26321e9f767SBen Widawsky if (rc == -ETIMEDOUT) { 2644f195ee7SDan Williams u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2654f195ee7SDan Williams 2664f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 26721e9f767SBen Widawsky return rc; 26821e9f767SBen Widawsky } 26921e9f767SBen Widawsky 27021e9f767SBen Widawsky /* #6 */ 2715e2411aeSIra Weiny status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 27221e9f767SBen Widawsky mbox_cmd->return_code = 27321e9f767SBen Widawsky FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 27421e9f767SBen Widawsky 275ccadf131SDavidlohr Bueso /* 276ccadf131SDavidlohr Bueso * Handle the background command in a synchronous manner. 277ccadf131SDavidlohr Bueso * 278ccadf131SDavidlohr Bueso * All other mailbox commands will serialize/queue on the mbox_mutex, 279ccadf131SDavidlohr Bueso * which we currently hold. Furthermore this also guarantees that 280ccadf131SDavidlohr Bueso * cxl_mbox_background_complete() checks are safe amongst each other, 281ccadf131SDavidlohr Bueso * in that no new bg operation can occur in between. 282ccadf131SDavidlohr Bueso * 283ccadf131SDavidlohr Bueso * Background operations are timesliced in accordance with the nature 284ccadf131SDavidlohr Bueso * of the command. In the event of timeout, the mailbox state is 285ccadf131SDavidlohr Bueso * indeterminate until the next successful command submission and the 286ccadf131SDavidlohr Bueso * driver can get back in sync with the hardware state. 287ccadf131SDavidlohr Bueso */ 288ccadf131SDavidlohr Bueso if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 289ccadf131SDavidlohr Bueso u64 bg_status_reg; 2900c36b6adSDavidlohr Bueso int i, timeout; 2910c36b6adSDavidlohr Bueso 2920c36b6adSDavidlohr Bueso /* 2930c36b6adSDavidlohr Bueso * Sanitization is a special case which monopolizes the device 2940c36b6adSDavidlohr Bueso * and cannot be timesliced. Handle asynchronously instead, 2950c36b6adSDavidlohr Bueso * and allow userspace to poll(2) for completion. 2960c36b6adSDavidlohr Bueso */ 2970c36b6adSDavidlohr Bueso if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 29871baec7bSDavidlohr Bueso if (mds->security.poll) { 2990c36b6adSDavidlohr Bueso /* hold the device throughout */ 3000c36b6adSDavidlohr Bueso get_device(cxlds->dev); 3010c36b6adSDavidlohr Bueso 3020c36b6adSDavidlohr Bueso /* give first timeout a second */ 3030c36b6adSDavidlohr Bueso timeout = 1; 304aeaefabcSDan Williams mds->security.poll_tmo_secs = timeout; 3050c36b6adSDavidlohr Bueso queue_delayed_work(system_wq, 306aeaefabcSDan Williams &mds->security.poll_dwork, 3070c36b6adSDavidlohr Bueso timeout * HZ); 3080c36b6adSDavidlohr Bueso } 3090c36b6adSDavidlohr Bueso 3100c36b6adSDavidlohr Bueso dev_dbg(dev, "Sanitization operation started\n"); 3110c36b6adSDavidlohr Bueso goto success; 3120c36b6adSDavidlohr Bueso } 313ccadf131SDavidlohr Bueso 314ccadf131SDavidlohr Bueso dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 315ccadf131SDavidlohr Bueso mbox_cmd->opcode); 316ccadf131SDavidlohr Bueso 3170c36b6adSDavidlohr Bueso timeout = mbox_cmd->poll_interval_ms; 318ccadf131SDavidlohr Bueso for (i = 0; i < mbox_cmd->poll_count; i++) { 319aeaefabcSDan Williams if (rcuwait_wait_event_timeout(&mds->mbox_wait, 320ccadf131SDavidlohr Bueso cxl_mbox_background_complete(cxlds), 321ccadf131SDavidlohr Bueso TASK_UNINTERRUPTIBLE, 322ccadf131SDavidlohr Bueso msecs_to_jiffies(timeout)) > 0) 323ccadf131SDavidlohr Bueso break; 324ccadf131SDavidlohr Bueso } 325ccadf131SDavidlohr Bueso 326ccadf131SDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) { 327ccadf131SDavidlohr Bueso dev_err(dev, "timeout waiting for background (%d ms)\n", 328ccadf131SDavidlohr Bueso timeout * mbox_cmd->poll_count); 329ccadf131SDavidlohr Bueso return -ETIMEDOUT; 330ccadf131SDavidlohr Bueso } 331ccadf131SDavidlohr Bueso 332ccadf131SDavidlohr Bueso bg_status_reg = readq(cxlds->regs.mbox + 333ccadf131SDavidlohr Bueso CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 334ccadf131SDavidlohr Bueso mbox_cmd->return_code = 335ccadf131SDavidlohr Bueso FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 336ccadf131SDavidlohr Bueso bg_status_reg); 337ccadf131SDavidlohr Bueso dev_dbg(dev, 338ccadf131SDavidlohr Bueso "Mailbox background operation (0x%04x) completed\n", 339ccadf131SDavidlohr Bueso mbox_cmd->opcode); 340ccadf131SDavidlohr Bueso } 341ccadf131SDavidlohr Bueso 34292fcc1abSDavidlohr Bueso if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 343c43e036dSDavidlohr Bueso dev_dbg(dev, "Mailbox operation had an error: %s\n", 344c43e036dSDavidlohr Bueso cxl_mbox_cmd_rc2str(mbox_cmd)); 345cbe83a20SDavidlohr Bueso return 0; /* completed but caller must check return_code */ 34621e9f767SBen Widawsky } 34721e9f767SBen Widawsky 3480c36b6adSDavidlohr Bueso success: 34921e9f767SBen Widawsky /* #7 */ 3505e2411aeSIra Weiny cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 35121e9f767SBen Widawsky out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 35221e9f767SBen Widawsky 35321e9f767SBen Widawsky /* #8 */ 35421e9f767SBen Widawsky if (out_len && mbox_cmd->payload_out) { 35521e9f767SBen Widawsky /* 35621e9f767SBen Widawsky * Sanitize the copy. If hardware misbehaves, out_len per the 35721e9f767SBen Widawsky * spec can actually be greater than the max allowed size (21 35821e9f767SBen Widawsky * bits available but spec defined 1M max). The caller also may 35921e9f767SBen Widawsky * have requested less data than the hardware supplied even 36021e9f767SBen Widawsky * within spec. 36121e9f767SBen Widawsky */ 36259f8d151SDan Williams size_t n; 36321e9f767SBen Widawsky 36459f8d151SDan Williams n = min3(mbox_cmd->size_out, mds->payload_size, out_len); 36521e9f767SBen Widawsky memcpy_fromio(mbox_cmd->payload_out, payload, n); 36621e9f767SBen Widawsky mbox_cmd->size_out = n; 36721e9f767SBen Widawsky } else { 36821e9f767SBen Widawsky mbox_cmd->size_out = 0; 36921e9f767SBen Widawsky } 37021e9f767SBen Widawsky 37121e9f767SBen Widawsky return 0; 37221e9f767SBen Widawsky } 37321e9f767SBen Widawsky 37459f8d151SDan Williams static int cxl_pci_mbox_send(struct cxl_memdev_state *mds, 37559f8d151SDan Williams struct cxl_mbox_cmd *cmd) 376b64955a9SDan Williams { 377b64955a9SDan Williams int rc; 378b64955a9SDan Williams 37959f8d151SDan Williams mutex_lock_io(&mds->mbox_mutex); 38059f8d151SDan Williams rc = __cxl_pci_mbox_send_cmd(mds, cmd); 38159f8d151SDan Williams mutex_unlock(&mds->mbox_mutex); 382b64955a9SDan Williams 383b64955a9SDan Williams return rc; 384b64955a9SDan Williams } 385b64955a9SDan Williams 38659f8d151SDan Williams static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) 38721e9f767SBen Widawsky { 38859f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 3895e2411aeSIra Weiny const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 39059f8d151SDan Williams struct device *dev = cxlds->dev; 391229e8828SBen Widawsky unsigned long timeout; 392229e8828SBen Widawsky u64 md_status; 393229e8828SBen Widawsky 394229e8828SBen Widawsky timeout = jiffies + mbox_ready_timeout * HZ; 395229e8828SBen Widawsky do { 396229e8828SBen Widawsky md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 397229e8828SBen Widawsky if (md_status & CXLMDEV_MBOX_IF_READY) 398229e8828SBen Widawsky break; 399229e8828SBen Widawsky if (msleep_interruptible(100)) 400229e8828SBen Widawsky break; 401229e8828SBen Widawsky } while (!time_after(jiffies, timeout)); 402229e8828SBen Widawsky 403229e8828SBen Widawsky if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 40459f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox ready"); 4054f195ee7SDan Williams return -ETIMEDOUT; 4064f195ee7SDan Williams } 4074f195ee7SDan Williams 4084f195ee7SDan Williams /* 4094f195ee7SDan Williams * A command may be in flight from a previous driver instance, 4104f195ee7SDan Williams * think kexec, do one doorbell wait so that 4114f195ee7SDan Williams * __cxl_pci_mbox_send_cmd() can assume that it is the only 4124f195ee7SDan Williams * source for future doorbell busy events. 4134f195ee7SDan Williams */ 4144f195ee7SDan Williams if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 41559f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox idle"); 4164f195ee7SDan Williams return -ETIMEDOUT; 417229e8828SBen Widawsky } 41821e9f767SBen Widawsky 41959f8d151SDan Williams mds->mbox_send = cxl_pci_mbox_send; 42059f8d151SDan Williams mds->payload_size = 42121e9f767SBen Widawsky 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 42221e9f767SBen Widawsky 42321e9f767SBen Widawsky /* 42421e9f767SBen Widawsky * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 42521e9f767SBen Widawsky * 42621e9f767SBen Widawsky * If the size is too small, mandatory commands will not work and so 42721e9f767SBen Widawsky * there's no point in going forward. If the size is too large, there's 42821e9f767SBen Widawsky * no harm is soft limiting it. 42921e9f767SBen Widawsky */ 43059f8d151SDan Williams mds->payload_size = min_t(size_t, mds->payload_size, SZ_1M); 43159f8d151SDan Williams if (mds->payload_size < 256) { 43259f8d151SDan Williams dev_err(dev, "Mailbox is too small (%zub)", 43359f8d151SDan Williams mds->payload_size); 43421e9f767SBen Widawsky return -ENXIO; 43521e9f767SBen Widawsky } 43621e9f767SBen Widawsky 43759f8d151SDan Williams dev_dbg(dev, "Mailbox payload sized %zu", mds->payload_size); 43821e9f767SBen Widawsky 439aeaefabcSDan Williams rcuwait_init(&mds->mbox_wait); 440ccadf131SDavidlohr Bueso 441ccadf131SDavidlohr Bueso if (cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) { 442ccadf131SDavidlohr Bueso u32 ctrl; 443ccadf131SDavidlohr Bueso int irq, msgnum; 444ccadf131SDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 445ccadf131SDavidlohr Bueso 446ccadf131SDavidlohr Bueso msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 447ccadf131SDavidlohr Bueso irq = pci_irq_vector(pdev, msgnum); 448ccadf131SDavidlohr Bueso if (irq < 0) 449ccadf131SDavidlohr Bueso goto mbox_poll; 450ccadf131SDavidlohr Bueso 451ccadf131SDavidlohr Bueso if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq, NULL)) 452ccadf131SDavidlohr Bueso goto mbox_poll; 453ccadf131SDavidlohr Bueso 454ccadf131SDavidlohr Bueso /* enable background command mbox irq support */ 455ccadf131SDavidlohr Bueso ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 456ccadf131SDavidlohr Bueso ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 457ccadf131SDavidlohr Bueso writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 458ccadf131SDavidlohr Bueso 459ccadf131SDavidlohr Bueso return 0; 460ccadf131SDavidlohr Bueso } 461ccadf131SDavidlohr Bueso 462ccadf131SDavidlohr Bueso mbox_poll: 463aeaefabcSDan Williams mds->security.poll = true; 464aeaefabcSDan Williams INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); 4650c36b6adSDavidlohr Bueso 466ccadf131SDavidlohr Bueso dev_dbg(cxlds->dev, "Mailbox interrupts are unsupported"); 46721e9f767SBen Widawsky return 0; 46821e9f767SBen Widawsky } 46921e9f767SBen Widawsky 4700a19bfc8SDan Williams /* 4710a19bfc8SDan Williams * Assume that any RCIEP that emits the CXL memory expander class code 4720a19bfc8SDan Williams * is an RCD 4730a19bfc8SDan Williams */ 4740a19bfc8SDan Williams static bool is_cxl_restricted(struct pci_dev *pdev) 4750a19bfc8SDan Williams { 4760a19bfc8SDan Williams return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 4770a19bfc8SDan Williams } 4780a19bfc8SDan Williams 479733b57f2SRobert Richter static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, 480733b57f2SRobert Richter struct cxl_register_map *map) 481733b57f2SRobert Richter { 482733b57f2SRobert Richter struct cxl_port *port; 483733b57f2SRobert Richter struct cxl_dport *dport; 484733b57f2SRobert Richter resource_size_t component_reg_phys; 485733b57f2SRobert Richter 486733b57f2SRobert Richter *map = (struct cxl_register_map) { 487733b57f2SRobert Richter .dev = &pdev->dev, 488733b57f2SRobert Richter .resource = CXL_RESOURCE_NONE, 489733b57f2SRobert Richter }; 490733b57f2SRobert Richter 491733b57f2SRobert Richter port = cxl_pci_find_port(pdev, &dport); 492733b57f2SRobert Richter if (!port) 493733b57f2SRobert Richter return -EPROBE_DEFER; 494733b57f2SRobert Richter 495733b57f2SRobert Richter component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); 496733b57f2SRobert Richter 497733b57f2SRobert Richter put_device(&port->dev); 498733b57f2SRobert Richter 499733b57f2SRobert Richter if (component_reg_phys == CXL_RESOURCE_NONE) 500733b57f2SRobert Richter return -ENXIO; 501733b57f2SRobert Richter 502733b57f2SRobert Richter map->resource = component_reg_phys; 503733b57f2SRobert Richter map->reg_type = CXL_REGLOC_RBI_COMPONENT; 504733b57f2SRobert Richter map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; 505733b57f2SRobert Richter 506733b57f2SRobert Richter return 0; 507733b57f2SRobert Richter } 508733b57f2SRobert Richter 509733b57f2SRobert Richter static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 510733b57f2SRobert Richter struct cxl_register_map *map) 511733b57f2SRobert Richter { 512733b57f2SRobert Richter int rc; 513733b57f2SRobert Richter 514733b57f2SRobert Richter rc = cxl_find_regblock(pdev, type, map); 515733b57f2SRobert Richter 516733b57f2SRobert Richter /* 517733b57f2SRobert Richter * If the Register Locator DVSEC does not exist, check if it 518733b57f2SRobert Richter * is an RCH and try to extract the Component Registers from 519733b57f2SRobert Richter * an RCRB. 520733b57f2SRobert Richter */ 521733b57f2SRobert Richter if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) 522733b57f2SRobert Richter rc = cxl_rcrb_get_comp_regs(pdev, map); 523733b57f2SRobert Richter 524733b57f2SRobert Richter if (rc) 525733b57f2SRobert Richter return rc; 526733b57f2SRobert Richter 527733b57f2SRobert Richter return cxl_setup_regs(map); 528733b57f2SRobert Richter } 529733b57f2SRobert Richter 530248529edSDave Jiang static int cxl_pci_ras_unmask(struct pci_dev *pdev) 531248529edSDave Jiang { 532248529edSDave Jiang struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 533248529edSDave Jiang void __iomem *addr; 534248529edSDave Jiang u32 orig_val, val, mask; 535248529edSDave Jiang u16 cap; 536248529edSDave Jiang int rc; 537248529edSDave Jiang 538248529edSDave Jiang if (!cxlds->regs.ras) { 539248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS registers.\n"); 540248529edSDave Jiang return 0; 541248529edSDave Jiang } 542248529edSDave Jiang 5430339dc39SSmita Koralahalli /* BIOS has PCIe AER error control */ 544*55b8ff06SSmita Koralahalli if (!pcie_aer_is_native(pdev)) 5450339dc39SSmita Koralahalli return 0; 546248529edSDave Jiang 547248529edSDave Jiang rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 548248529edSDave Jiang if (rc) 549248529edSDave Jiang return rc; 550248529edSDave Jiang 551248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_URRE) { 552248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 553248529edSDave Jiang orig_val = readl(addr); 554248529edSDave Jiang 555f3c8a37aSDan Williams mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | 556f3c8a37aSDan Williams CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 557248529edSDave Jiang val = orig_val & ~mask; 558248529edSDave Jiang writel(val, addr); 559248529edSDave Jiang dev_dbg(&pdev->dev, 560248529edSDave Jiang "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 561248529edSDave Jiang orig_val, val); 562248529edSDave Jiang } 563248529edSDave Jiang 564248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_CERE) { 565248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 566248529edSDave Jiang orig_val = readl(addr); 567248529edSDave Jiang val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 568248529edSDave Jiang writel(val, addr); 569248529edSDave Jiang dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 570248529edSDave Jiang orig_val, val); 571248529edSDave Jiang } 572248529edSDave Jiang 573248529edSDave Jiang return 0; 5742905cb52SDan Williams } 5752905cb52SDan Williams 5766ebe28f9SIra Weiny static void free_event_buf(void *buf) 5776ebe28f9SIra Weiny { 5786ebe28f9SIra Weiny kvfree(buf); 5796ebe28f9SIra Weiny } 5806ebe28f9SIra Weiny 5816ebe28f9SIra Weiny /* 5826ebe28f9SIra Weiny * There is a single buffer for reading event logs from the mailbox. All logs 58359f8d151SDan Williams * share this buffer protected by the mds->event_log_lock. 5846ebe28f9SIra Weiny */ 58559f8d151SDan Williams static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) 5866ebe28f9SIra Weiny { 5876ebe28f9SIra Weiny struct cxl_get_event_payload *buf; 5886ebe28f9SIra Weiny 58959f8d151SDan Williams buf = kvmalloc(mds->payload_size, GFP_KERNEL); 5906ebe28f9SIra Weiny if (!buf) 5916ebe28f9SIra Weiny return -ENOMEM; 59259f8d151SDan Williams mds->event.buf = buf; 5936ebe28f9SIra Weiny 59459f8d151SDan Williams return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); 5956ebe28f9SIra Weiny } 5966ebe28f9SIra Weiny 597a49aa814SDavidlohr Bueso static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 598a49aa814SDavidlohr Bueso { 599a49aa814SDavidlohr Bueso int nvecs; 600a49aa814SDavidlohr Bueso 601a49aa814SDavidlohr Bueso /* 602a49aa814SDavidlohr Bueso * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 603a49aa814SDavidlohr Bueso * not generate INTx messages if that function participates in 604a49aa814SDavidlohr Bueso * CXL.cache or CXL.mem. 605a49aa814SDavidlohr Bueso * 606a49aa814SDavidlohr Bueso * Additionally pci_alloc_irq_vectors() handles calling 607a49aa814SDavidlohr Bueso * pci_free_irq_vectors() automatically despite not being called 608a49aa814SDavidlohr Bueso * pcim_*. See pci_setup_msi_context(). 609a49aa814SDavidlohr Bueso */ 610a49aa814SDavidlohr Bueso nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 611a49aa814SDavidlohr Bueso PCI_IRQ_MSIX | PCI_IRQ_MSI); 612a49aa814SDavidlohr Bueso if (nvecs < 1) { 613a49aa814SDavidlohr Bueso dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 614a49aa814SDavidlohr Bueso return -ENXIO; 615a49aa814SDavidlohr Bueso } 616a49aa814SDavidlohr Bueso return 0; 617a49aa814SDavidlohr Bueso } 618a49aa814SDavidlohr Bueso 619a49aa814SDavidlohr Bueso static irqreturn_t cxl_event_thread(int irq, void *id) 620a49aa814SDavidlohr Bueso { 621a49aa814SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 622a49aa814SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 62359f8d151SDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 624a49aa814SDavidlohr Bueso u32 status; 625a49aa814SDavidlohr Bueso 626a49aa814SDavidlohr Bueso do { 627a49aa814SDavidlohr Bueso /* 628a49aa814SDavidlohr Bueso * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 629a49aa814SDavidlohr Bueso * ignore the reserved upper 32 bits 630a49aa814SDavidlohr Bueso */ 631a49aa814SDavidlohr Bueso status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 632a49aa814SDavidlohr Bueso /* Ignore logs unknown to the driver */ 633a49aa814SDavidlohr Bueso status &= CXLDEV_EVENT_STATUS_ALL; 634a49aa814SDavidlohr Bueso if (!status) 635a49aa814SDavidlohr Bueso break; 63659f8d151SDan Williams cxl_mem_get_event_records(mds, status); 637a49aa814SDavidlohr Bueso cond_resched(); 638a49aa814SDavidlohr Bueso } while (status); 639a49aa814SDavidlohr Bueso 640a49aa814SDavidlohr Bueso return IRQ_HANDLED; 641a49aa814SDavidlohr Bueso } 642a49aa814SDavidlohr Bueso 643a49aa814SDavidlohr Bueso static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 644a49aa814SDavidlohr Bueso { 6459f7a320dSDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 646a49aa814SDavidlohr Bueso int irq; 647a49aa814SDavidlohr Bueso 648a49aa814SDavidlohr Bueso if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 649a49aa814SDavidlohr Bueso return -ENXIO; 650a49aa814SDavidlohr Bueso 651a49aa814SDavidlohr Bueso irq = pci_irq_vector(pdev, 652a49aa814SDavidlohr Bueso FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 653a49aa814SDavidlohr Bueso if (irq < 0) 654a49aa814SDavidlohr Bueso return irq; 655a49aa814SDavidlohr Bueso 6569f7a320dSDavidlohr Bueso return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 657a49aa814SDavidlohr Bueso } 658a49aa814SDavidlohr Bueso 65959f8d151SDan Williams static int cxl_event_get_int_policy(struct cxl_memdev_state *mds, 660a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 661a49aa814SDavidlohr Bueso { 662a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd = { 663a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 664a49aa814SDavidlohr Bueso .payload_out = policy, 665a49aa814SDavidlohr Bueso .size_out = sizeof(*policy), 666a49aa814SDavidlohr Bueso }; 667a49aa814SDavidlohr Bueso int rc; 668a49aa814SDavidlohr Bueso 66959f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 670a49aa814SDavidlohr Bueso if (rc < 0) 67159f8d151SDan Williams dev_err(mds->cxlds.dev, 67259f8d151SDan Williams "Failed to get event interrupt policy : %d", rc); 673a49aa814SDavidlohr Bueso 674a49aa814SDavidlohr Bueso return rc; 675a49aa814SDavidlohr Bueso } 676a49aa814SDavidlohr Bueso 67759f8d151SDan Williams static int cxl_event_config_msgnums(struct cxl_memdev_state *mds, 678a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 679a49aa814SDavidlohr Bueso { 680a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd; 681a49aa814SDavidlohr Bueso int rc; 682a49aa814SDavidlohr Bueso 683a49aa814SDavidlohr Bueso *policy = (struct cxl_event_interrupt_policy) { 684a49aa814SDavidlohr Bueso .info_settings = CXL_INT_MSI_MSIX, 685a49aa814SDavidlohr Bueso .warn_settings = CXL_INT_MSI_MSIX, 686a49aa814SDavidlohr Bueso .failure_settings = CXL_INT_MSI_MSIX, 687a49aa814SDavidlohr Bueso .fatal_settings = CXL_INT_MSI_MSIX, 688a49aa814SDavidlohr Bueso }; 689a49aa814SDavidlohr Bueso 690a49aa814SDavidlohr Bueso mbox_cmd = (struct cxl_mbox_cmd) { 691a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 692a49aa814SDavidlohr Bueso .payload_in = policy, 693a49aa814SDavidlohr Bueso .size_in = sizeof(*policy), 694a49aa814SDavidlohr Bueso }; 695a49aa814SDavidlohr Bueso 69659f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 697a49aa814SDavidlohr Bueso if (rc < 0) { 69859f8d151SDan Williams dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d", 699a49aa814SDavidlohr Bueso rc); 700a49aa814SDavidlohr Bueso return rc; 701a49aa814SDavidlohr Bueso } 702a49aa814SDavidlohr Bueso 703a49aa814SDavidlohr Bueso /* Retrieve final interrupt settings */ 70459f8d151SDan Williams return cxl_event_get_int_policy(mds, policy); 705a49aa814SDavidlohr Bueso } 706a49aa814SDavidlohr Bueso 70759f8d151SDan Williams static int cxl_event_irqsetup(struct cxl_memdev_state *mds) 708a49aa814SDavidlohr Bueso { 70959f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 710a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 711a49aa814SDavidlohr Bueso int rc; 712a49aa814SDavidlohr Bueso 71359f8d151SDan Williams rc = cxl_event_config_msgnums(mds, &policy); 714a49aa814SDavidlohr Bueso if (rc) 715a49aa814SDavidlohr Bueso return rc; 716a49aa814SDavidlohr Bueso 717a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.info_settings); 718a49aa814SDavidlohr Bueso if (rc) { 719a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 720a49aa814SDavidlohr Bueso return rc; 721a49aa814SDavidlohr Bueso } 722a49aa814SDavidlohr Bueso 723a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.warn_settings); 724a49aa814SDavidlohr Bueso if (rc) { 725a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 726a49aa814SDavidlohr Bueso return rc; 727a49aa814SDavidlohr Bueso } 728a49aa814SDavidlohr Bueso 729a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.failure_settings); 730a49aa814SDavidlohr Bueso if (rc) { 731a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 732a49aa814SDavidlohr Bueso return rc; 733a49aa814SDavidlohr Bueso } 734a49aa814SDavidlohr Bueso 735a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 736a49aa814SDavidlohr Bueso if (rc) { 737a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 738a49aa814SDavidlohr Bueso return rc; 739a49aa814SDavidlohr Bueso } 740a49aa814SDavidlohr Bueso 741a49aa814SDavidlohr Bueso return 0; 742a49aa814SDavidlohr Bueso } 743a49aa814SDavidlohr Bueso 744a49aa814SDavidlohr Bueso static bool cxl_event_int_is_fw(u8 setting) 745a49aa814SDavidlohr Bueso { 746a49aa814SDavidlohr Bueso u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 747a49aa814SDavidlohr Bueso 748a49aa814SDavidlohr Bueso return mode == CXL_INT_FW; 749a49aa814SDavidlohr Bueso } 750a49aa814SDavidlohr Bueso 751a49aa814SDavidlohr Bueso static int cxl_event_config(struct pci_host_bridge *host_bridge, 75259f8d151SDan Williams struct cxl_memdev_state *mds) 753a49aa814SDavidlohr Bueso { 754a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 755a49aa814SDavidlohr Bueso int rc; 756a49aa814SDavidlohr Bueso 757a49aa814SDavidlohr Bueso /* 758a49aa814SDavidlohr Bueso * When BIOS maintains CXL error reporting control, it will process 759a49aa814SDavidlohr Bueso * event records. Only one agent can do so. 760a49aa814SDavidlohr Bueso */ 761a49aa814SDavidlohr Bueso if (!host_bridge->native_cxl_error) 762a49aa814SDavidlohr Bueso return 0; 763a49aa814SDavidlohr Bueso 76459f8d151SDan Williams rc = cxl_mem_alloc_event_buf(mds); 765a49aa814SDavidlohr Bueso if (rc) 766a49aa814SDavidlohr Bueso return rc; 767a49aa814SDavidlohr Bueso 76859f8d151SDan Williams rc = cxl_event_get_int_policy(mds, &policy); 769a49aa814SDavidlohr Bueso if (rc) 770a49aa814SDavidlohr Bueso return rc; 771a49aa814SDavidlohr Bueso 772a49aa814SDavidlohr Bueso if (cxl_event_int_is_fw(policy.info_settings) || 773a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.warn_settings) || 774a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.failure_settings) || 775a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.fatal_settings)) { 77659f8d151SDan Williams dev_err(mds->cxlds.dev, 77759f8d151SDan Williams "FW still in control of Event Logs despite _OSC settings\n"); 778a49aa814SDavidlohr Bueso return -EBUSY; 779a49aa814SDavidlohr Bueso } 780a49aa814SDavidlohr Bueso 78159f8d151SDan Williams rc = cxl_event_irqsetup(mds); 782a49aa814SDavidlohr Bueso if (rc) 783a49aa814SDavidlohr Bueso return rc; 784a49aa814SDavidlohr Bueso 78559f8d151SDan Williams cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 786a49aa814SDavidlohr Bueso 787a49aa814SDavidlohr Bueso return 0; 788a49aa814SDavidlohr Bueso } 789a49aa814SDavidlohr Bueso 790ed97afb5SBen Widawsky static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 79121e9f767SBen Widawsky { 7926ebe28f9SIra Weiny struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 79359f8d151SDan Williams struct cxl_memdev_state *mds; 79459f8d151SDan Williams struct cxl_dev_state *cxlds; 79585afc317SBen Widawsky struct cxl_register_map map; 79621083f51SDan Williams struct cxl_memdev *cxlmd; 7971ad3f701SJonathan Cameron int i, rc, pmu_count; 79821e9f767SBen Widawsky 7995a2328f4SDan Williams /* 8005a2328f4SDan Williams * Double check the anonymous union trickery in struct cxl_regs 8015a2328f4SDan Williams * FIXME switch to struct_group() 8025a2328f4SDan Williams */ 8035a2328f4SDan Williams BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 8045a2328f4SDan Williams offsetof(struct cxl_regs, device_regs.memdev)); 8055a2328f4SDan Williams 80621e9f767SBen Widawsky rc = pcim_enable_device(pdev); 80721e9f767SBen Widawsky if (rc) 80821e9f767SBen Widawsky return rc; 809a49aa814SDavidlohr Bueso pci_set_master(pdev); 81021e9f767SBen Widawsky 81159f8d151SDan Williams mds = cxl_memdev_state_create(&pdev->dev); 81259f8d151SDan Williams if (IS_ERR(mds)) 81359f8d151SDan Williams return PTR_ERR(mds); 81459f8d151SDan Williams cxlds = &mds->cxlds; 8152905cb52SDan Williams pci_set_drvdata(pdev, cxlds); 8161b0a1a2aSBen Widawsky 8170a19bfc8SDan Williams cxlds->rcd = is_cxl_restricted(pdev); 818bcc79ea3SDan Williams cxlds->serial = pci_get_dsn(pdev); 81906e279e5SBen Widawsky cxlds->cxl_dvsec = pci_find_dvsec_capability( 82006e279e5SBen Widawsky pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 82106e279e5SBen Widawsky if (!cxlds->cxl_dvsec) 82206e279e5SBen Widawsky dev_warn(&pdev->dev, 82306e279e5SBen Widawsky "Device DVSEC not present, skip CXL.mem init\n"); 82406e279e5SBen Widawsky 825d076bb8cSTerry Bowman rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 82685afc317SBen Widawsky if (rc) 82785afc317SBen Widawsky return rc; 82885afc317SBen Widawsky 82957340804SRobert Richter rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); 83021e9f767SBen Widawsky if (rc) 83121e9f767SBen Widawsky return rc; 83221e9f767SBen Widawsky 8334112a08dSBen Widawsky /* 8344112a08dSBen Widawsky * If the component registers can't be found, the cxl_pci driver may 8354112a08dSBen Widawsky * still be useful for management functions so don't return an error. 8364112a08dSBen Widawsky */ 8374112a08dSBen Widawsky cxlds->component_reg_phys = CXL_RESOURCE_NONE; 838d076bb8cSTerry Bowman rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 8394112a08dSBen Widawsky if (rc) 8404112a08dSBen Widawsky dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 841f1d0525eSRobert Richter else if (!map.component_map.ras.valid) 842f1d0525eSRobert Richter dev_dbg(&pdev->dev, "RAS registers not found\n"); 8434112a08dSBen Widawsky 8446c7f4f1eSDan Williams cxlds->component_reg_phys = map.resource; 8454112a08dSBen Widawsky 84657340804SRobert Richter rc = cxl_map_component_regs(&map, &cxlds->regs.component, 84757340804SRobert Richter BIT(CXL_CM_CAP_CAP_ID_RAS)); 848bd09626bSDan Williams if (rc) 849bd09626bSDan Williams dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 850bd09626bSDan Williams 851e764f122SDave Jiang rc = cxl_await_media_ready(cxlds); 852e764f122SDave Jiang if (rc == 0) 853e764f122SDave Jiang cxlds->media_ready = true; 854e764f122SDave Jiang else 855e764f122SDave Jiang dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 856e764f122SDave Jiang 857f279d0bcSDavidlohr Bueso rc = cxl_alloc_irq_vectors(pdev); 858f279d0bcSDavidlohr Bueso if (rc) 859f279d0bcSDavidlohr Bueso return rc; 860f279d0bcSDavidlohr Bueso 86159f8d151SDan Williams rc = cxl_pci_setup_mailbox(mds); 86221e9f767SBen Widawsky if (rc) 86321e9f767SBen Widawsky return rc; 86421e9f767SBen Widawsky 86559f8d151SDan Williams rc = cxl_enumerate_cmds(mds); 86621e9f767SBen Widawsky if (rc) 86721e9f767SBen Widawsky return rc; 86821e9f767SBen Widawsky 86959f8d151SDan Williams rc = cxl_set_timestamp(mds); 870fa884345SJonathan Cameron if (rc) 871fa884345SJonathan Cameron return rc; 872fa884345SJonathan Cameron 87359f8d151SDan Williams rc = cxl_poison_state_init(mds); 874d0abf578SAlison Schofield if (rc) 875d0abf578SAlison Schofield return rc; 876d0abf578SAlison Schofield 87759f8d151SDan Williams rc = cxl_dev_state_identify(mds); 87821e9f767SBen Widawsky if (rc) 87921e9f767SBen Widawsky return rc; 88021e9f767SBen Widawsky 88159f8d151SDan Williams rc = cxl_mem_create_range_info(mds); 882f847502aSIra Weiny if (rc) 883f847502aSIra Weiny return rc; 884f847502aSIra Weiny 8855e2411aeSIra Weiny cxlmd = devm_cxl_add_memdev(cxlds); 88621083f51SDan Williams if (IS_ERR(cxlmd)) 88721083f51SDan Williams return PTR_ERR(cxlmd); 88821083f51SDan Williams 889aeaefabcSDan Williams rc = cxl_memdev_setup_fw_upload(mds); 8909521875bSVishal Verma if (rc) 8919521875bSVishal Verma return rc; 8929521875bSVishal Verma 8931ad3f701SJonathan Cameron pmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_PMU); 8941ad3f701SJonathan Cameron for (i = 0; i < pmu_count; i++) { 8951ad3f701SJonathan Cameron struct cxl_pmu_regs pmu_regs; 8961ad3f701SJonathan Cameron 8971ad3f701SJonathan Cameron rc = cxl_find_regblock_instance(pdev, CXL_REGLOC_RBI_PMU, &map, i); 8981ad3f701SJonathan Cameron if (rc) { 8991ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not find PMU regblock\n"); 9001ad3f701SJonathan Cameron break; 9011ad3f701SJonathan Cameron } 9021ad3f701SJonathan Cameron 9031ad3f701SJonathan Cameron rc = cxl_map_pmu_regs(pdev, &pmu_regs, &map); 9041ad3f701SJonathan Cameron if (rc) { 9051ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not map PMU regs\n"); 9061ad3f701SJonathan Cameron break; 9071ad3f701SJonathan Cameron } 9081ad3f701SJonathan Cameron 9091ad3f701SJonathan Cameron rc = devm_cxl_pmu_add(cxlds->dev, &pmu_regs, cxlmd->id, i, CXL_PMU_MEMDEV); 9101ad3f701SJonathan Cameron if (rc) { 9111ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not add PMU instance\n"); 9121ad3f701SJonathan Cameron break; 9131ad3f701SJonathan Cameron } 9141ad3f701SJonathan Cameron } 9151ad3f701SJonathan Cameron 91659f8d151SDan Williams rc = cxl_event_config(host_bridge, mds); 9176ebe28f9SIra Weiny if (rc) 9186ebe28f9SIra Weiny return rc; 9196ebe28f9SIra Weiny 920248529edSDave Jiang rc = cxl_pci_ras_unmask(pdev); 9212905cb52SDan Williams if (rc) 922248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 923248529edSDave Jiang 9242905cb52SDan Williams pci_save_state(pdev); 9252905cb52SDan Williams 92621083f51SDan Williams return rc; 92721e9f767SBen Widawsky } 92821e9f767SBen Widawsky 92921e9f767SBen Widawsky static const struct pci_device_id cxl_mem_pci_tbl[] = { 93021e9f767SBen Widawsky /* PCI class code for CXL.mem Type-3 Devices */ 93121e9f767SBen Widawsky { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 93221e9f767SBen Widawsky { /* terminate list */ }, 93321e9f767SBen Widawsky }; 93421e9f767SBen Widawsky MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 93521e9f767SBen Widawsky 9362905cb52SDan Williams static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 9372905cb52SDan Williams { 9382905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9392905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9402905cb52SDan Williams struct device *dev = &cxlmd->dev; 9412905cb52SDan Williams 9422905cb52SDan Williams dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 9432905cb52SDan Williams dev_name(dev)); 9442905cb52SDan Williams pci_restore_state(pdev); 9452905cb52SDan Williams if (device_attach(dev) <= 0) 9462905cb52SDan Williams return PCI_ERS_RESULT_DISCONNECT; 9472905cb52SDan Williams return PCI_ERS_RESULT_RECOVERED; 9482905cb52SDan Williams } 9492905cb52SDan Williams 9502905cb52SDan Williams static void cxl_error_resume(struct pci_dev *pdev) 9512905cb52SDan Williams { 9522905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9532905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9542905cb52SDan Williams struct device *dev = &cxlmd->dev; 9552905cb52SDan Williams 9562905cb52SDan Williams dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 9572905cb52SDan Williams dev->driver ? "successful" : "failed"); 9582905cb52SDan Williams } 9592905cb52SDan Williams 9602905cb52SDan Williams static const struct pci_error_handlers cxl_error_handlers = { 9612905cb52SDan Williams .error_detected = cxl_error_detected, 9622905cb52SDan Williams .slot_reset = cxl_slot_reset, 9632905cb52SDan Williams .resume = cxl_error_resume, 9646155ccc9SDave Jiang .cor_error_detected = cxl_cor_error_detected, 9652905cb52SDan Williams }; 9662905cb52SDan Williams 967ed97afb5SBen Widawsky static struct pci_driver cxl_pci_driver = { 96821e9f767SBen Widawsky .name = KBUILD_MODNAME, 96921e9f767SBen Widawsky .id_table = cxl_mem_pci_tbl, 970ed97afb5SBen Widawsky .probe = cxl_pci_probe, 9712905cb52SDan Williams .err_handler = &cxl_error_handlers, 97221e9f767SBen Widawsky .driver = { 97321e9f767SBen Widawsky .probe_type = PROBE_PREFER_ASYNCHRONOUS, 97421e9f767SBen Widawsky }, 97521e9f767SBen Widawsky }; 97621e9f767SBen Widawsky 97721e9f767SBen Widawsky MODULE_LICENSE("GPL v2"); 978ed97afb5SBen Widawsky module_pci_driver(cxl_pci_driver); 97921e9f767SBen Widawsky MODULE_IMPORT_NS(CXL); 980