121e9f767SBen Widawsky // SPDX-License-Identifier: GPL-2.0-only 221e9f767SBen Widawsky /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 34faf31b4SDan Williams #include <linux/io-64-nonatomic-lo-hi.h> 4229e8828SBen Widawsky #include <linux/moduleparam.h> 521e9f767SBen Widawsky #include <linux/module.h> 6229e8828SBen Widawsky #include <linux/delay.h> 721e9f767SBen Widawsky #include <linux/sizes.h> 821e9f767SBen Widawsky #include <linux/mutex.h> 930af9729SIra Weiny #include <linux/list.h> 1021e9f767SBen Widawsky #include <linux/pci.h> 112905cb52SDan Williams #include <linux/aer.h> 1221e9f767SBen Widawsky #include <linux/io.h> 135161a55cSBen Widawsky #include "cxlmem.h" 14af9cae9fSDan Williams #include "cxlpci.h" 1521e9f767SBen Widawsky #include "cxl.h" 161ad3f701SJonathan Cameron #include "pmu.h" 1721e9f767SBen Widawsky 1821e9f767SBen Widawsky /** 1921e9f767SBen Widawsky * DOC: cxl pci 2021e9f767SBen Widawsky * 2121e9f767SBen Widawsky * This implements the PCI exclusive functionality for a CXL device as it is 2221e9f767SBen Widawsky * defined by the Compute Express Link specification. CXL devices may surface 23ed97afb5SBen Widawsky * certain functionality even if it isn't CXL enabled. While this driver is 24ed97afb5SBen Widawsky * focused around the PCI specific aspects of a CXL device, it binds to the 25ed97afb5SBen Widawsky * specific CXL memory device class code, and therefore the implementation of 26ed97afb5SBen Widawsky * cxl_pci is focused around CXL memory devices. 2721e9f767SBen Widawsky * 2821e9f767SBen Widawsky * The driver has several responsibilities, mainly: 2921e9f767SBen Widawsky * - Create the memX device and register on the CXL bus. 3021e9f767SBen Widawsky * - Enumerate device's register interface and map them. 31ed97afb5SBen Widawsky * - Registers nvdimm bridge device with cxl_core. 32ed97afb5SBen Widawsky * - Registers a CXL mailbox with cxl_core. 3321e9f767SBen Widawsky */ 3421e9f767SBen Widawsky 355e2411aeSIra Weiny #define cxl_doorbell_busy(cxlds) \ 365e2411aeSIra Weiny (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 3721e9f767SBen Widawsky CXLDEV_MBOX_CTRL_DOORBELL) 3821e9f767SBen Widawsky 3921e9f767SBen Widawsky /* CXL 2.0 - 8.2.8.4 */ 4021e9f767SBen Widawsky #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 4121e9f767SBen Widawsky 42229e8828SBen Widawsky /* 43229e8828SBen Widawsky * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 44229e8828SBen Widawsky * dictate how long to wait for the mailbox to become ready. The new 45229e8828SBen Widawsky * field allows the device to tell software the amount of time to wait 46229e8828SBen Widawsky * before mailbox ready. This field per the spec theoretically allows 47229e8828SBen Widawsky * for up to 255 seconds. 255 seconds is unreasonably long, its longer 48229e8828SBen Widawsky * than the maximum SATA port link recovery wait. Default to 60 seconds 49229e8828SBen Widawsky * until someone builds a CXL device that needs more time in practice. 50229e8828SBen Widawsky */ 51229e8828SBen Widawsky static unsigned short mbox_ready_timeout = 60; 52229e8828SBen Widawsky module_param(mbox_ready_timeout, ushort, 0644); 532e4ba0ecSDan Williams MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 54229e8828SBen Widawsky 555e2411aeSIra Weiny static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 5621e9f767SBen Widawsky { 5721e9f767SBen Widawsky const unsigned long start = jiffies; 5821e9f767SBen Widawsky unsigned long end = start; 5921e9f767SBen Widawsky 605e2411aeSIra Weiny while (cxl_doorbell_busy(cxlds)) { 6121e9f767SBen Widawsky end = jiffies; 6221e9f767SBen Widawsky 6321e9f767SBen Widawsky if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 6421e9f767SBen Widawsky /* Check again in case preempted before timeout test */ 655e2411aeSIra Weiny if (!cxl_doorbell_busy(cxlds)) 6621e9f767SBen Widawsky break; 6721e9f767SBen Widawsky return -ETIMEDOUT; 6821e9f767SBen Widawsky } 6921e9f767SBen Widawsky cpu_relax(); 7021e9f767SBen Widawsky } 7121e9f767SBen Widawsky 725e2411aeSIra Weiny dev_dbg(cxlds->dev, "Doorbell wait took %dms", 7321e9f767SBen Widawsky jiffies_to_msecs(end) - jiffies_to_msecs(start)); 7421e9f767SBen Widawsky return 0; 7521e9f767SBen Widawsky } 7621e9f767SBen Widawsky 774f195ee7SDan Williams #define cxl_err(dev, status, msg) \ 784f195ee7SDan Williams dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 794f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 804f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8121e9f767SBen Widawsky 824f195ee7SDan Williams #define cxl_cmd_err(dev, cmd, status, msg) \ 834f195ee7SDan Williams dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 844f195ee7SDan Williams (cmd)->opcode, \ 854f195ee7SDan Williams status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 864f195ee7SDan Williams status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 8721e9f767SBen Widawsky 889f7a320dSDavidlohr Bueso struct cxl_dev_id { 899f7a320dSDavidlohr Bueso struct cxl_dev_state *cxlds; 909f7a320dSDavidlohr Bueso }; 919f7a320dSDavidlohr Bueso 929f7a320dSDavidlohr Bueso static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 939f7a320dSDavidlohr Bueso irq_handler_t handler, irq_handler_t thread_fn) 949f7a320dSDavidlohr Bueso { 959f7a320dSDavidlohr Bueso struct device *dev = cxlds->dev; 969f7a320dSDavidlohr Bueso struct cxl_dev_id *dev_id; 979f7a320dSDavidlohr Bueso 989f7a320dSDavidlohr Bueso /* dev_id must be globally unique and must contain the cxlds */ 999f7a320dSDavidlohr Bueso dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 1009f7a320dSDavidlohr Bueso if (!dev_id) 1019f7a320dSDavidlohr Bueso return -ENOMEM; 1029f7a320dSDavidlohr Bueso dev_id->cxlds = cxlds; 1039f7a320dSDavidlohr Bueso 1049f7a320dSDavidlohr Bueso return devm_request_threaded_irq(dev, irq, handler, thread_fn, 1059f7a320dSDavidlohr Bueso IRQF_SHARED | IRQF_ONESHOT, 1069f7a320dSDavidlohr Bueso NULL, dev_id); 1079f7a320dSDavidlohr Bueso } 1089f7a320dSDavidlohr Bueso 109ccadf131SDavidlohr Bueso static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 110ccadf131SDavidlohr Bueso { 111ccadf131SDavidlohr Bueso u64 reg; 112ccadf131SDavidlohr Bueso 113ccadf131SDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 114ccadf131SDavidlohr Bueso return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 115ccadf131SDavidlohr Bueso } 116ccadf131SDavidlohr Bueso 117ccadf131SDavidlohr Bueso static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 118ccadf131SDavidlohr Bueso { 1190c36b6adSDavidlohr Bueso u64 reg; 1200c36b6adSDavidlohr Bueso u16 opcode; 121ccadf131SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 122ccadf131SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 123aeaefabcSDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 124ccadf131SDavidlohr Bueso 1258ea9c33dSDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) 1268ea9c33dSDavidlohr Bueso return IRQ_NONE; 1278ea9c33dSDavidlohr Bueso 1280c36b6adSDavidlohr Bueso reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 1290c36b6adSDavidlohr Bueso opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 1300c36b6adSDavidlohr Bueso if (opcode == CXL_MBOX_OP_SANITIZE) { 131e8347a1cSDan Williams mutex_lock(&mds->mbox_mutex); 132aeaefabcSDan Williams if (mds->security.sanitize_node) 133e8347a1cSDan Williams mod_delayed_work(system_wq, &mds->security.poll_dwork, 0); 134e8347a1cSDan Williams mutex_unlock(&mds->mbox_mutex); 1350c36b6adSDavidlohr Bueso } else { 136ccadf131SDavidlohr Bueso /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 137aeaefabcSDan Williams rcuwait_wake_up(&mds->mbox_wait); 1380c36b6adSDavidlohr Bueso } 139ccadf131SDavidlohr Bueso 140ccadf131SDavidlohr Bueso return IRQ_HANDLED; 141ccadf131SDavidlohr Bueso } 142ccadf131SDavidlohr Bueso 1430c36b6adSDavidlohr Bueso /* 1440c36b6adSDavidlohr Bueso * Sanitization operation polling mode. 1450c36b6adSDavidlohr Bueso */ 1460c36b6adSDavidlohr Bueso static void cxl_mbox_sanitize_work(struct work_struct *work) 1470c36b6adSDavidlohr Bueso { 148aeaefabcSDan Williams struct cxl_memdev_state *mds = 149aeaefabcSDan Williams container_of(work, typeof(*mds), security.poll_dwork.work); 150aeaefabcSDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1510c36b6adSDavidlohr Bueso 152aeaefabcSDan Williams mutex_lock(&mds->mbox_mutex); 1530c36b6adSDavidlohr Bueso if (cxl_mbox_background_complete(cxlds)) { 154aeaefabcSDan Williams mds->security.poll_tmo_secs = 0; 155aeaefabcSDan Williams if (mds->security.sanitize_node) 156aeaefabcSDan Williams sysfs_notify_dirent(mds->security.sanitize_node); 15748dcdbb1SDavidlohr Bueso 1580c36b6adSDavidlohr Bueso dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 1590c36b6adSDavidlohr Bueso } else { 160aeaefabcSDan Williams int timeout = mds->security.poll_tmo_secs + 10; 1610c36b6adSDavidlohr Bueso 162aeaefabcSDan Williams mds->security.poll_tmo_secs = min(15 * 60, timeout); 163e8347a1cSDan Williams schedule_delayed_work(&mds->security.poll_dwork, timeout * HZ); 1640c36b6adSDavidlohr Bueso } 165aeaefabcSDan Williams mutex_unlock(&mds->mbox_mutex); 1660c36b6adSDavidlohr Bueso } 1670c36b6adSDavidlohr Bueso 16821e9f767SBen Widawsky /** 169ed97afb5SBen Widawsky * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 17059f8d151SDan Williams * @mds: The memory device driver data 17121e9f767SBen Widawsky * @mbox_cmd: Command to send to the memory device. 17221e9f767SBen Widawsky * 17321e9f767SBen Widawsky * Context: Any context. Expects mbox_mutex to be held. 17421e9f767SBen Widawsky * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 17521e9f767SBen Widawsky * Caller should check the return code in @mbox_cmd to make sure it 17621e9f767SBen Widawsky * succeeded. 17721e9f767SBen Widawsky * 17821e9f767SBen Widawsky * This is a generic form of the CXL mailbox send command thus only using the 17921e9f767SBen Widawsky * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 18021e9f767SBen Widawsky * devices, and perhaps other types of CXL devices may have further information 18121e9f767SBen Widawsky * available upon error conditions. Driver facilities wishing to send mailbox 18221e9f767SBen Widawsky * commands should use the wrapper command. 18321e9f767SBen Widawsky * 18421e9f767SBen Widawsky * The CXL spec allows for up to two mailboxes. The intention is for the primary 18521e9f767SBen Widawsky * mailbox to be OS controlled and the secondary mailbox to be used by system 18621e9f767SBen Widawsky * firmware. This allows the OS and firmware to communicate with the device and 18721e9f767SBen Widawsky * not need to coordinate with each other. The driver only uses the primary 18821e9f767SBen Widawsky * mailbox. 18921e9f767SBen Widawsky */ 19059f8d151SDan Williams static int __cxl_pci_mbox_send_cmd(struct cxl_memdev_state *mds, 191b64955a9SDan Williams struct cxl_mbox_cmd *mbox_cmd) 19221e9f767SBen Widawsky { 19359f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 1945e2411aeSIra Weiny void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 1955e2411aeSIra Weiny struct device *dev = cxlds->dev; 19621e9f767SBen Widawsky u64 cmd_reg, status_reg; 19721e9f767SBen Widawsky size_t out_len; 19821e9f767SBen Widawsky int rc; 19921e9f767SBen Widawsky 20059f8d151SDan Williams lockdep_assert_held(&mds->mbox_mutex); 20121e9f767SBen Widawsky 20221e9f767SBen Widawsky /* 20321e9f767SBen Widawsky * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 20421e9f767SBen Widawsky * 1. Caller reads MB Control Register to verify doorbell is clear 20521e9f767SBen Widawsky * 2. Caller writes Command Register 20621e9f767SBen Widawsky * 3. Caller writes Command Payload Registers if input payload is non-empty 20721e9f767SBen Widawsky * 4. Caller writes MB Control Register to set doorbell 20821e9f767SBen Widawsky * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 20921e9f767SBen Widawsky * 6. Caller reads MB Status Register to fetch Return code 21021e9f767SBen Widawsky * 7. If command successful, Caller reads Command Register to get Payload Length 21121e9f767SBen Widawsky * 8. If output payload is non-empty, host reads Command Payload Registers 21221e9f767SBen Widawsky * 21321e9f767SBen Widawsky * Hardware is free to do whatever it wants before the doorbell is rung, 21421e9f767SBen Widawsky * and isn't allowed to change anything after it clears the doorbell. As 21521e9f767SBen Widawsky * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 21621e9f767SBen Widawsky * also happen in any order (though some orders might not make sense). 21721e9f767SBen Widawsky */ 21821e9f767SBen Widawsky 21921e9f767SBen Widawsky /* #1 */ 2205e2411aeSIra Weiny if (cxl_doorbell_busy(cxlds)) { 2214f195ee7SDan Williams u64 md_status = 2224f195ee7SDan Williams readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2234f195ee7SDan Williams 2244f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 2254f195ee7SDan Williams "mailbox queue busy"); 22621e9f767SBen Widawsky return -EBUSY; 22721e9f767SBen Widawsky } 22821e9f767SBen Widawsky 2290c36b6adSDavidlohr Bueso /* 2300c36b6adSDavidlohr Bueso * With sanitize polling, hardware might be done and the poller still 2310c36b6adSDavidlohr Bueso * not be in sync. Ensure no new command comes in until so. Keep the 2320c36b6adSDavidlohr Bueso * hardware semantics and only allow device health status. 2330c36b6adSDavidlohr Bueso */ 234aeaefabcSDan Williams if (mds->security.poll_tmo_secs > 0) { 2350c36b6adSDavidlohr Bueso if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 2360c36b6adSDavidlohr Bueso return -EBUSY; 2370c36b6adSDavidlohr Bueso } 2380c36b6adSDavidlohr Bueso 23921e9f767SBen Widawsky cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 24021e9f767SBen Widawsky mbox_cmd->opcode); 24121e9f767SBen Widawsky if (mbox_cmd->size_in) { 24221e9f767SBen Widawsky if (WARN_ON(!mbox_cmd->payload_in)) 24321e9f767SBen Widawsky return -EINVAL; 24421e9f767SBen Widawsky 24521e9f767SBen Widawsky cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 24621e9f767SBen Widawsky mbox_cmd->size_in); 24721e9f767SBen Widawsky memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 24821e9f767SBen Widawsky } 24921e9f767SBen Widawsky 25021e9f767SBen Widawsky /* #2, #3 */ 2515e2411aeSIra Weiny writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 25221e9f767SBen Widawsky 25321e9f767SBen Widawsky /* #4 */ 254852db33cSRobert Richter dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 25521e9f767SBen Widawsky writel(CXLDEV_MBOX_CTRL_DOORBELL, 2565e2411aeSIra Weiny cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 25721e9f767SBen Widawsky 25821e9f767SBen Widawsky /* #5 */ 2595e2411aeSIra Weiny rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 26021e9f767SBen Widawsky if (rc == -ETIMEDOUT) { 2614f195ee7SDan Williams u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 2624f195ee7SDan Williams 2634f195ee7SDan Williams cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 26421e9f767SBen Widawsky return rc; 26521e9f767SBen Widawsky } 26621e9f767SBen Widawsky 26721e9f767SBen Widawsky /* #6 */ 2685e2411aeSIra Weiny status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 26921e9f767SBen Widawsky mbox_cmd->return_code = 27021e9f767SBen Widawsky FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 27121e9f767SBen Widawsky 272ccadf131SDavidlohr Bueso /* 273ccadf131SDavidlohr Bueso * Handle the background command in a synchronous manner. 274ccadf131SDavidlohr Bueso * 275ccadf131SDavidlohr Bueso * All other mailbox commands will serialize/queue on the mbox_mutex, 276ccadf131SDavidlohr Bueso * which we currently hold. Furthermore this also guarantees that 277ccadf131SDavidlohr Bueso * cxl_mbox_background_complete() checks are safe amongst each other, 278ccadf131SDavidlohr Bueso * in that no new bg operation can occur in between. 279ccadf131SDavidlohr Bueso * 280ccadf131SDavidlohr Bueso * Background operations are timesliced in accordance with the nature 281ccadf131SDavidlohr Bueso * of the command. In the event of timeout, the mailbox state is 282ccadf131SDavidlohr Bueso * indeterminate until the next successful command submission and the 283ccadf131SDavidlohr Bueso * driver can get back in sync with the hardware state. 284ccadf131SDavidlohr Bueso */ 285ccadf131SDavidlohr Bueso if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 286ccadf131SDavidlohr Bueso u64 bg_status_reg; 2870c36b6adSDavidlohr Bueso int i, timeout; 2880c36b6adSDavidlohr Bueso 2890c36b6adSDavidlohr Bueso /* 2900c36b6adSDavidlohr Bueso * Sanitization is a special case which monopolizes the device 2910c36b6adSDavidlohr Bueso * and cannot be timesliced. Handle asynchronously instead, 2920c36b6adSDavidlohr Bueso * and allow userspace to poll(2) for completion. 2930c36b6adSDavidlohr Bueso */ 2940c36b6adSDavidlohr Bueso if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 2950c36b6adSDavidlohr Bueso /* give first timeout a second */ 2960c36b6adSDavidlohr Bueso timeout = 1; 297aeaefabcSDan Williams mds->security.poll_tmo_secs = timeout; 298e8347a1cSDan Williams schedule_delayed_work(&mds->security.poll_dwork, 2990c36b6adSDavidlohr Bueso timeout * HZ); 3000c36b6adSDavidlohr Bueso dev_dbg(dev, "Sanitization operation started\n"); 3010c36b6adSDavidlohr Bueso goto success; 3020c36b6adSDavidlohr Bueso } 303ccadf131SDavidlohr Bueso 304ccadf131SDavidlohr Bueso dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 305ccadf131SDavidlohr Bueso mbox_cmd->opcode); 306ccadf131SDavidlohr Bueso 3070c36b6adSDavidlohr Bueso timeout = mbox_cmd->poll_interval_ms; 308ccadf131SDavidlohr Bueso for (i = 0; i < mbox_cmd->poll_count; i++) { 309aeaefabcSDan Williams if (rcuwait_wait_event_timeout(&mds->mbox_wait, 310ccadf131SDavidlohr Bueso cxl_mbox_background_complete(cxlds), 311ccadf131SDavidlohr Bueso TASK_UNINTERRUPTIBLE, 312ccadf131SDavidlohr Bueso msecs_to_jiffies(timeout)) > 0) 313ccadf131SDavidlohr Bueso break; 314ccadf131SDavidlohr Bueso } 315ccadf131SDavidlohr Bueso 316ccadf131SDavidlohr Bueso if (!cxl_mbox_background_complete(cxlds)) { 317ccadf131SDavidlohr Bueso dev_err(dev, "timeout waiting for background (%d ms)\n", 318ccadf131SDavidlohr Bueso timeout * mbox_cmd->poll_count); 319ccadf131SDavidlohr Bueso return -ETIMEDOUT; 320ccadf131SDavidlohr Bueso } 321ccadf131SDavidlohr Bueso 322ccadf131SDavidlohr Bueso bg_status_reg = readq(cxlds->regs.mbox + 323ccadf131SDavidlohr Bueso CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 324ccadf131SDavidlohr Bueso mbox_cmd->return_code = 325ccadf131SDavidlohr Bueso FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 326ccadf131SDavidlohr Bueso bg_status_reg); 327ccadf131SDavidlohr Bueso dev_dbg(dev, 328ccadf131SDavidlohr Bueso "Mailbox background operation (0x%04x) completed\n", 329ccadf131SDavidlohr Bueso mbox_cmd->opcode); 330ccadf131SDavidlohr Bueso } 331ccadf131SDavidlohr Bueso 33292fcc1abSDavidlohr Bueso if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 333c43e036dSDavidlohr Bueso dev_dbg(dev, "Mailbox operation had an error: %s\n", 334c43e036dSDavidlohr Bueso cxl_mbox_cmd_rc2str(mbox_cmd)); 335cbe83a20SDavidlohr Bueso return 0; /* completed but caller must check return_code */ 33621e9f767SBen Widawsky } 33721e9f767SBen Widawsky 3380c36b6adSDavidlohr Bueso success: 33921e9f767SBen Widawsky /* #7 */ 3405e2411aeSIra Weiny cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 34121e9f767SBen Widawsky out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 34221e9f767SBen Widawsky 34321e9f767SBen Widawsky /* #8 */ 34421e9f767SBen Widawsky if (out_len && mbox_cmd->payload_out) { 34521e9f767SBen Widawsky /* 34621e9f767SBen Widawsky * Sanitize the copy. If hardware misbehaves, out_len per the 34721e9f767SBen Widawsky * spec can actually be greater than the max allowed size (21 34821e9f767SBen Widawsky * bits available but spec defined 1M max). The caller also may 34921e9f767SBen Widawsky * have requested less data than the hardware supplied even 35021e9f767SBen Widawsky * within spec. 35121e9f767SBen Widawsky */ 35259f8d151SDan Williams size_t n; 35321e9f767SBen Widawsky 35459f8d151SDan Williams n = min3(mbox_cmd->size_out, mds->payload_size, out_len); 35521e9f767SBen Widawsky memcpy_fromio(mbox_cmd->payload_out, payload, n); 35621e9f767SBen Widawsky mbox_cmd->size_out = n; 35721e9f767SBen Widawsky } else { 35821e9f767SBen Widawsky mbox_cmd->size_out = 0; 35921e9f767SBen Widawsky } 36021e9f767SBen Widawsky 36121e9f767SBen Widawsky return 0; 36221e9f767SBen Widawsky } 36321e9f767SBen Widawsky 36459f8d151SDan Williams static int cxl_pci_mbox_send(struct cxl_memdev_state *mds, 36559f8d151SDan Williams struct cxl_mbox_cmd *cmd) 366b64955a9SDan Williams { 367b64955a9SDan Williams int rc; 368b64955a9SDan Williams 36959f8d151SDan Williams mutex_lock_io(&mds->mbox_mutex); 37059f8d151SDan Williams rc = __cxl_pci_mbox_send_cmd(mds, cmd); 37159f8d151SDan Williams mutex_unlock(&mds->mbox_mutex); 372b64955a9SDan Williams 373b64955a9SDan Williams return rc; 374b64955a9SDan Williams } 375b64955a9SDan Williams 37659f8d151SDan Williams static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds) 37721e9f767SBen Widawsky { 37859f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 3795e2411aeSIra Weiny const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 38059f8d151SDan Williams struct device *dev = cxlds->dev; 381229e8828SBen Widawsky unsigned long timeout; 382e8347a1cSDan Williams int irq, msgnum; 383229e8828SBen Widawsky u64 md_status; 384e8347a1cSDan Williams u32 ctrl; 385229e8828SBen Widawsky 386229e8828SBen Widawsky timeout = jiffies + mbox_ready_timeout * HZ; 387229e8828SBen Widawsky do { 388229e8828SBen Widawsky md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 389229e8828SBen Widawsky if (md_status & CXLMDEV_MBOX_IF_READY) 390229e8828SBen Widawsky break; 391229e8828SBen Widawsky if (msleep_interruptible(100)) 392229e8828SBen Widawsky break; 393229e8828SBen Widawsky } while (!time_after(jiffies, timeout)); 394229e8828SBen Widawsky 395229e8828SBen Widawsky if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 39659f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox ready"); 3974f195ee7SDan Williams return -ETIMEDOUT; 3984f195ee7SDan Williams } 3994f195ee7SDan Williams 4004f195ee7SDan Williams /* 4014f195ee7SDan Williams * A command may be in flight from a previous driver instance, 4024f195ee7SDan Williams * think kexec, do one doorbell wait so that 4034f195ee7SDan Williams * __cxl_pci_mbox_send_cmd() can assume that it is the only 4044f195ee7SDan Williams * source for future doorbell busy events. 4054f195ee7SDan Williams */ 4064f195ee7SDan Williams if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 40759f8d151SDan Williams cxl_err(dev, md_status, "timeout awaiting mailbox idle"); 4084f195ee7SDan Williams return -ETIMEDOUT; 409229e8828SBen Widawsky } 41021e9f767SBen Widawsky 41159f8d151SDan Williams mds->mbox_send = cxl_pci_mbox_send; 41259f8d151SDan Williams mds->payload_size = 41321e9f767SBen Widawsky 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 41421e9f767SBen Widawsky 41521e9f767SBen Widawsky /* 41621e9f767SBen Widawsky * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 41721e9f767SBen Widawsky * 41821e9f767SBen Widawsky * If the size is too small, mandatory commands will not work and so 41921e9f767SBen Widawsky * there's no point in going forward. If the size is too large, there's 42021e9f767SBen Widawsky * no harm is soft limiting it. 42121e9f767SBen Widawsky */ 42259f8d151SDan Williams mds->payload_size = min_t(size_t, mds->payload_size, SZ_1M); 42359f8d151SDan Williams if (mds->payload_size < 256) { 42459f8d151SDan Williams dev_err(dev, "Mailbox is too small (%zub)", 42559f8d151SDan Williams mds->payload_size); 42621e9f767SBen Widawsky return -ENXIO; 42721e9f767SBen Widawsky } 42821e9f767SBen Widawsky 42959f8d151SDan Williams dev_dbg(dev, "Mailbox payload sized %zu", mds->payload_size); 43021e9f767SBen Widawsky 431aeaefabcSDan Williams rcuwait_init(&mds->mbox_wait); 432e8347a1cSDan Williams INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); 433ccadf131SDavidlohr Bueso 434e8347a1cSDan Williams /* background command interrupts are optional */ 435e8347a1cSDan Williams if (!(cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ)) 436e8347a1cSDan Williams return 0; 437ccadf131SDavidlohr Bueso 438ccadf131SDavidlohr Bueso msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 439e8347a1cSDan Williams irq = pci_irq_vector(to_pci_dev(cxlds->dev), msgnum); 440ccadf131SDavidlohr Bueso if (irq < 0) 441e8347a1cSDan Williams return 0; 442ccadf131SDavidlohr Bueso 443e8347a1cSDan Williams if (cxl_request_irq(cxlds, irq, NULL, cxl_pci_mbox_irq)) 444e8347a1cSDan Williams return 0; 445ccadf131SDavidlohr Bueso 446e8347a1cSDan Williams dev_dbg(cxlds->dev, "Mailbox interrupts enabled\n"); 447ccadf131SDavidlohr Bueso /* enable background command mbox irq support */ 448ccadf131SDavidlohr Bueso ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 449ccadf131SDavidlohr Bueso ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 450ccadf131SDavidlohr Bueso writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 451ccadf131SDavidlohr Bueso 452ccadf131SDavidlohr Bueso return 0; 453ccadf131SDavidlohr Bueso } 454ccadf131SDavidlohr Bueso 4550a19bfc8SDan Williams /* 4560a19bfc8SDan Williams * Assume that any RCIEP that emits the CXL memory expander class code 4570a19bfc8SDan Williams * is an RCD 4580a19bfc8SDan Williams */ 4590a19bfc8SDan Williams static bool is_cxl_restricted(struct pci_dev *pdev) 4600a19bfc8SDan Williams { 4610a19bfc8SDan Williams return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 4620a19bfc8SDan Williams } 4630a19bfc8SDan Williams 464733b57f2SRobert Richter static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, 465733b57f2SRobert Richter struct cxl_register_map *map) 466733b57f2SRobert Richter { 467733b57f2SRobert Richter struct cxl_port *port; 468733b57f2SRobert Richter struct cxl_dport *dport; 469733b57f2SRobert Richter resource_size_t component_reg_phys; 470733b57f2SRobert Richter 471733b57f2SRobert Richter *map = (struct cxl_register_map) { 472733b57f2SRobert Richter .dev = &pdev->dev, 473733b57f2SRobert Richter .resource = CXL_RESOURCE_NONE, 474733b57f2SRobert Richter }; 475733b57f2SRobert Richter 476733b57f2SRobert Richter port = cxl_pci_find_port(pdev, &dport); 477733b57f2SRobert Richter if (!port) 478733b57f2SRobert Richter return -EPROBE_DEFER; 479733b57f2SRobert Richter 480733b57f2SRobert Richter component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); 481733b57f2SRobert Richter 482733b57f2SRobert Richter put_device(&port->dev); 483733b57f2SRobert Richter 484733b57f2SRobert Richter if (component_reg_phys == CXL_RESOURCE_NONE) 485733b57f2SRobert Richter return -ENXIO; 486733b57f2SRobert Richter 487733b57f2SRobert Richter map->resource = component_reg_phys; 488733b57f2SRobert Richter map->reg_type = CXL_REGLOC_RBI_COMPONENT; 489733b57f2SRobert Richter map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; 490733b57f2SRobert Richter 491733b57f2SRobert Richter return 0; 492733b57f2SRobert Richter } 493733b57f2SRobert Richter 494733b57f2SRobert Richter static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 495733b57f2SRobert Richter struct cxl_register_map *map) 496733b57f2SRobert Richter { 497733b57f2SRobert Richter int rc; 498733b57f2SRobert Richter 499733b57f2SRobert Richter rc = cxl_find_regblock(pdev, type, map); 500733b57f2SRobert Richter 501733b57f2SRobert Richter /* 502733b57f2SRobert Richter * If the Register Locator DVSEC does not exist, check if it 503733b57f2SRobert Richter * is an RCH and try to extract the Component Registers from 504733b57f2SRobert Richter * an RCRB. 505733b57f2SRobert Richter */ 506733b57f2SRobert Richter if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) 507733b57f2SRobert Richter rc = cxl_rcrb_get_comp_regs(pdev, map); 508733b57f2SRobert Richter 509733b57f2SRobert Richter if (rc) 510733b57f2SRobert Richter return rc; 511733b57f2SRobert Richter 512733b57f2SRobert Richter return cxl_setup_regs(map); 513733b57f2SRobert Richter } 514733b57f2SRobert Richter 515248529edSDave Jiang static int cxl_pci_ras_unmask(struct pci_dev *pdev) 516248529edSDave Jiang { 517248529edSDave Jiang struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 518248529edSDave Jiang void __iomem *addr; 519248529edSDave Jiang u32 orig_val, val, mask; 520248529edSDave Jiang u16 cap; 521248529edSDave Jiang int rc; 522248529edSDave Jiang 523248529edSDave Jiang if (!cxlds->regs.ras) { 524248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS registers.\n"); 525248529edSDave Jiang return 0; 526248529edSDave Jiang } 527248529edSDave Jiang 5280339dc39SSmita Koralahalli /* BIOS has PCIe AER error control */ 52955b8ff06SSmita Koralahalli if (!pcie_aer_is_native(pdev)) 5300339dc39SSmita Koralahalli return 0; 531248529edSDave Jiang 532248529edSDave Jiang rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 533248529edSDave Jiang if (rc) 534248529edSDave Jiang return rc; 535248529edSDave Jiang 536248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_URRE) { 537248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 538248529edSDave Jiang orig_val = readl(addr); 539248529edSDave Jiang 540f3c8a37aSDan Williams mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | 541f3c8a37aSDan Williams CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 542248529edSDave Jiang val = orig_val & ~mask; 543248529edSDave Jiang writel(val, addr); 544248529edSDave Jiang dev_dbg(&pdev->dev, 545248529edSDave Jiang "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 546248529edSDave Jiang orig_val, val); 547248529edSDave Jiang } 548248529edSDave Jiang 549248529edSDave Jiang if (cap & PCI_EXP_DEVCTL_CERE) { 550248529edSDave Jiang addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 551248529edSDave Jiang orig_val = readl(addr); 552248529edSDave Jiang val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 553248529edSDave Jiang writel(val, addr); 554248529edSDave Jiang dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 555248529edSDave Jiang orig_val, val); 556248529edSDave Jiang } 557248529edSDave Jiang 558248529edSDave Jiang return 0; 5592905cb52SDan Williams } 5602905cb52SDan Williams 5616ebe28f9SIra Weiny static void free_event_buf(void *buf) 5626ebe28f9SIra Weiny { 5636ebe28f9SIra Weiny kvfree(buf); 5646ebe28f9SIra Weiny } 5656ebe28f9SIra Weiny 5666ebe28f9SIra Weiny /* 5676ebe28f9SIra Weiny * There is a single buffer for reading event logs from the mailbox. All logs 56859f8d151SDan Williams * share this buffer protected by the mds->event_log_lock. 5696ebe28f9SIra Weiny */ 57059f8d151SDan Williams static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) 5716ebe28f9SIra Weiny { 5726ebe28f9SIra Weiny struct cxl_get_event_payload *buf; 5736ebe28f9SIra Weiny 57459f8d151SDan Williams buf = kvmalloc(mds->payload_size, GFP_KERNEL); 5756ebe28f9SIra Weiny if (!buf) 5766ebe28f9SIra Weiny return -ENOMEM; 57759f8d151SDan Williams mds->event.buf = buf; 5786ebe28f9SIra Weiny 57959f8d151SDan Williams return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); 5806ebe28f9SIra Weiny } 5816ebe28f9SIra Weiny 582a49aa814SDavidlohr Bueso static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 583a49aa814SDavidlohr Bueso { 584a49aa814SDavidlohr Bueso int nvecs; 585a49aa814SDavidlohr Bueso 586a49aa814SDavidlohr Bueso /* 587a49aa814SDavidlohr Bueso * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 588a49aa814SDavidlohr Bueso * not generate INTx messages if that function participates in 589a49aa814SDavidlohr Bueso * CXL.cache or CXL.mem. 590a49aa814SDavidlohr Bueso * 591a49aa814SDavidlohr Bueso * Additionally pci_alloc_irq_vectors() handles calling 592a49aa814SDavidlohr Bueso * pci_free_irq_vectors() automatically despite not being called 593a49aa814SDavidlohr Bueso * pcim_*. See pci_setup_msi_context(). 594a49aa814SDavidlohr Bueso */ 595a49aa814SDavidlohr Bueso nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 596a49aa814SDavidlohr Bueso PCI_IRQ_MSIX | PCI_IRQ_MSI); 597a49aa814SDavidlohr Bueso if (nvecs < 1) { 598a49aa814SDavidlohr Bueso dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 599a49aa814SDavidlohr Bueso return -ENXIO; 600a49aa814SDavidlohr Bueso } 601a49aa814SDavidlohr Bueso return 0; 602a49aa814SDavidlohr Bueso } 603a49aa814SDavidlohr Bueso 604a49aa814SDavidlohr Bueso static irqreturn_t cxl_event_thread(int irq, void *id) 605a49aa814SDavidlohr Bueso { 606a49aa814SDavidlohr Bueso struct cxl_dev_id *dev_id = id; 607a49aa814SDavidlohr Bueso struct cxl_dev_state *cxlds = dev_id->cxlds; 60859f8d151SDan Williams struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 609a49aa814SDavidlohr Bueso u32 status; 610a49aa814SDavidlohr Bueso 611a49aa814SDavidlohr Bueso do { 612a49aa814SDavidlohr Bueso /* 613a49aa814SDavidlohr Bueso * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 614a49aa814SDavidlohr Bueso * ignore the reserved upper 32 bits 615a49aa814SDavidlohr Bueso */ 616a49aa814SDavidlohr Bueso status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 617a49aa814SDavidlohr Bueso /* Ignore logs unknown to the driver */ 618a49aa814SDavidlohr Bueso status &= CXLDEV_EVENT_STATUS_ALL; 619a49aa814SDavidlohr Bueso if (!status) 620a49aa814SDavidlohr Bueso break; 62159f8d151SDan Williams cxl_mem_get_event_records(mds, status); 622a49aa814SDavidlohr Bueso cond_resched(); 623a49aa814SDavidlohr Bueso } while (status); 624a49aa814SDavidlohr Bueso 625a49aa814SDavidlohr Bueso return IRQ_HANDLED; 626a49aa814SDavidlohr Bueso } 627a49aa814SDavidlohr Bueso 628a49aa814SDavidlohr Bueso static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 629a49aa814SDavidlohr Bueso { 6309f7a320dSDavidlohr Bueso struct pci_dev *pdev = to_pci_dev(cxlds->dev); 631a49aa814SDavidlohr Bueso int irq; 632a49aa814SDavidlohr Bueso 633a49aa814SDavidlohr Bueso if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 634a49aa814SDavidlohr Bueso return -ENXIO; 635a49aa814SDavidlohr Bueso 636a49aa814SDavidlohr Bueso irq = pci_irq_vector(pdev, 637a49aa814SDavidlohr Bueso FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 638a49aa814SDavidlohr Bueso if (irq < 0) 639a49aa814SDavidlohr Bueso return irq; 640a49aa814SDavidlohr Bueso 6419f7a320dSDavidlohr Bueso return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 642a49aa814SDavidlohr Bueso } 643a49aa814SDavidlohr Bueso 64459f8d151SDan Williams static int cxl_event_get_int_policy(struct cxl_memdev_state *mds, 645a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 646a49aa814SDavidlohr Bueso { 647a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd = { 648a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 649a49aa814SDavidlohr Bueso .payload_out = policy, 650a49aa814SDavidlohr Bueso .size_out = sizeof(*policy), 651a49aa814SDavidlohr Bueso }; 652a49aa814SDavidlohr Bueso int rc; 653a49aa814SDavidlohr Bueso 65459f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 655a49aa814SDavidlohr Bueso if (rc < 0) 65659f8d151SDan Williams dev_err(mds->cxlds.dev, 65759f8d151SDan Williams "Failed to get event interrupt policy : %d", rc); 658a49aa814SDavidlohr Bueso 659a49aa814SDavidlohr Bueso return rc; 660a49aa814SDavidlohr Bueso } 661a49aa814SDavidlohr Bueso 66259f8d151SDan Williams static int cxl_event_config_msgnums(struct cxl_memdev_state *mds, 663a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy *policy) 664a49aa814SDavidlohr Bueso { 665a49aa814SDavidlohr Bueso struct cxl_mbox_cmd mbox_cmd; 666a49aa814SDavidlohr Bueso int rc; 667a49aa814SDavidlohr Bueso 668a49aa814SDavidlohr Bueso *policy = (struct cxl_event_interrupt_policy) { 669a49aa814SDavidlohr Bueso .info_settings = CXL_INT_MSI_MSIX, 670a49aa814SDavidlohr Bueso .warn_settings = CXL_INT_MSI_MSIX, 671a49aa814SDavidlohr Bueso .failure_settings = CXL_INT_MSI_MSIX, 672a49aa814SDavidlohr Bueso .fatal_settings = CXL_INT_MSI_MSIX, 673a49aa814SDavidlohr Bueso }; 674a49aa814SDavidlohr Bueso 675a49aa814SDavidlohr Bueso mbox_cmd = (struct cxl_mbox_cmd) { 676a49aa814SDavidlohr Bueso .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 677a49aa814SDavidlohr Bueso .payload_in = policy, 678a49aa814SDavidlohr Bueso .size_in = sizeof(*policy), 679a49aa814SDavidlohr Bueso }; 680a49aa814SDavidlohr Bueso 68159f8d151SDan Williams rc = cxl_internal_send_cmd(mds, &mbox_cmd); 682a49aa814SDavidlohr Bueso if (rc < 0) { 68359f8d151SDan Williams dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d", 684a49aa814SDavidlohr Bueso rc); 685a49aa814SDavidlohr Bueso return rc; 686a49aa814SDavidlohr Bueso } 687a49aa814SDavidlohr Bueso 688a49aa814SDavidlohr Bueso /* Retrieve final interrupt settings */ 68959f8d151SDan Williams return cxl_event_get_int_policy(mds, policy); 690a49aa814SDavidlohr Bueso } 691a49aa814SDavidlohr Bueso 69259f8d151SDan Williams static int cxl_event_irqsetup(struct cxl_memdev_state *mds) 693a49aa814SDavidlohr Bueso { 69459f8d151SDan Williams struct cxl_dev_state *cxlds = &mds->cxlds; 695a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 696a49aa814SDavidlohr Bueso int rc; 697a49aa814SDavidlohr Bueso 69859f8d151SDan Williams rc = cxl_event_config_msgnums(mds, &policy); 699a49aa814SDavidlohr Bueso if (rc) 700a49aa814SDavidlohr Bueso return rc; 701a49aa814SDavidlohr Bueso 702a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.info_settings); 703a49aa814SDavidlohr Bueso if (rc) { 704a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 705a49aa814SDavidlohr Bueso return rc; 706a49aa814SDavidlohr Bueso } 707a49aa814SDavidlohr Bueso 708a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.warn_settings); 709a49aa814SDavidlohr Bueso if (rc) { 710a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 711a49aa814SDavidlohr Bueso return rc; 712a49aa814SDavidlohr Bueso } 713a49aa814SDavidlohr Bueso 714a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.failure_settings); 715a49aa814SDavidlohr Bueso if (rc) { 716a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 717a49aa814SDavidlohr Bueso return rc; 718a49aa814SDavidlohr Bueso } 719a49aa814SDavidlohr Bueso 720a49aa814SDavidlohr Bueso rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 721a49aa814SDavidlohr Bueso if (rc) { 722a49aa814SDavidlohr Bueso dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 723a49aa814SDavidlohr Bueso return rc; 724a49aa814SDavidlohr Bueso } 725a49aa814SDavidlohr Bueso 726a49aa814SDavidlohr Bueso return 0; 727a49aa814SDavidlohr Bueso } 728a49aa814SDavidlohr Bueso 729a49aa814SDavidlohr Bueso static bool cxl_event_int_is_fw(u8 setting) 730a49aa814SDavidlohr Bueso { 731a49aa814SDavidlohr Bueso u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 732a49aa814SDavidlohr Bueso 733a49aa814SDavidlohr Bueso return mode == CXL_INT_FW; 734a49aa814SDavidlohr Bueso } 735a49aa814SDavidlohr Bueso 736a49aa814SDavidlohr Bueso static int cxl_event_config(struct pci_host_bridge *host_bridge, 73759f8d151SDan Williams struct cxl_memdev_state *mds) 738a49aa814SDavidlohr Bueso { 739a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy policy; 740a49aa814SDavidlohr Bueso int rc; 741a49aa814SDavidlohr Bueso 742a49aa814SDavidlohr Bueso /* 743a49aa814SDavidlohr Bueso * When BIOS maintains CXL error reporting control, it will process 744a49aa814SDavidlohr Bueso * event records. Only one agent can do so. 745a49aa814SDavidlohr Bueso */ 746a49aa814SDavidlohr Bueso if (!host_bridge->native_cxl_error) 747a49aa814SDavidlohr Bueso return 0; 748a49aa814SDavidlohr Bueso 74959f8d151SDan Williams rc = cxl_mem_alloc_event_buf(mds); 750a49aa814SDavidlohr Bueso if (rc) 751a49aa814SDavidlohr Bueso return rc; 752a49aa814SDavidlohr Bueso 75359f8d151SDan Williams rc = cxl_event_get_int_policy(mds, &policy); 754a49aa814SDavidlohr Bueso if (rc) 755a49aa814SDavidlohr Bueso return rc; 756a49aa814SDavidlohr Bueso 757a49aa814SDavidlohr Bueso if (cxl_event_int_is_fw(policy.info_settings) || 758a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.warn_settings) || 759a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.failure_settings) || 760a49aa814SDavidlohr Bueso cxl_event_int_is_fw(policy.fatal_settings)) { 76159f8d151SDan Williams dev_err(mds->cxlds.dev, 76259f8d151SDan Williams "FW still in control of Event Logs despite _OSC settings\n"); 763a49aa814SDavidlohr Bueso return -EBUSY; 764a49aa814SDavidlohr Bueso } 765a49aa814SDavidlohr Bueso 76659f8d151SDan Williams rc = cxl_event_irqsetup(mds); 767a49aa814SDavidlohr Bueso if (rc) 768a49aa814SDavidlohr Bueso return rc; 769a49aa814SDavidlohr Bueso 77059f8d151SDan Williams cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 771a49aa814SDavidlohr Bueso 772a49aa814SDavidlohr Bueso return 0; 773a49aa814SDavidlohr Bueso } 774a49aa814SDavidlohr Bueso 775ed97afb5SBen Widawsky static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 77621e9f767SBen Widawsky { 7776ebe28f9SIra Weiny struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 77859f8d151SDan Williams struct cxl_memdev_state *mds; 77959f8d151SDan Williams struct cxl_dev_state *cxlds; 78085afc317SBen Widawsky struct cxl_register_map map; 78121083f51SDan Williams struct cxl_memdev *cxlmd; 7821ad3f701SJonathan Cameron int i, rc, pmu_count; 78321e9f767SBen Widawsky 7845a2328f4SDan Williams /* 7855a2328f4SDan Williams * Double check the anonymous union trickery in struct cxl_regs 7865a2328f4SDan Williams * FIXME switch to struct_group() 7875a2328f4SDan Williams */ 7885a2328f4SDan Williams BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 7895a2328f4SDan Williams offsetof(struct cxl_regs, device_regs.memdev)); 7905a2328f4SDan Williams 79121e9f767SBen Widawsky rc = pcim_enable_device(pdev); 79221e9f767SBen Widawsky if (rc) 79321e9f767SBen Widawsky return rc; 794a49aa814SDavidlohr Bueso pci_set_master(pdev); 79521e9f767SBen Widawsky 79659f8d151SDan Williams mds = cxl_memdev_state_create(&pdev->dev); 79759f8d151SDan Williams if (IS_ERR(mds)) 79859f8d151SDan Williams return PTR_ERR(mds); 79959f8d151SDan Williams cxlds = &mds->cxlds; 8002905cb52SDan Williams pci_set_drvdata(pdev, cxlds); 8011b0a1a2aSBen Widawsky 8020a19bfc8SDan Williams cxlds->rcd = is_cxl_restricted(pdev); 803bcc79ea3SDan Williams cxlds->serial = pci_get_dsn(pdev); 80406e279e5SBen Widawsky cxlds->cxl_dvsec = pci_find_dvsec_capability( 80506e279e5SBen Widawsky pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 80606e279e5SBen Widawsky if (!cxlds->cxl_dvsec) 80706e279e5SBen Widawsky dev_warn(&pdev->dev, 80806e279e5SBen Widawsky "Device DVSEC not present, skip CXL.mem init\n"); 80906e279e5SBen Widawsky 810d076bb8cSTerry Bowman rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 81185afc317SBen Widawsky if (rc) 81285afc317SBen Widawsky return rc; 81385afc317SBen Widawsky 81457340804SRobert Richter rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); 81521e9f767SBen Widawsky if (rc) 81621e9f767SBen Widawsky return rc; 81721e9f767SBen Widawsky 8184112a08dSBen Widawsky /* 8194112a08dSBen Widawsky * If the component registers can't be found, the cxl_pci driver may 8204112a08dSBen Widawsky * still be useful for management functions so don't return an error. 8214112a08dSBen Widawsky */ 8224112a08dSBen Widawsky cxlds->component_reg_phys = CXL_RESOURCE_NONE; 823d076bb8cSTerry Bowman rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 8244112a08dSBen Widawsky if (rc) 8254112a08dSBen Widawsky dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 826f1d0525eSRobert Richter else if (!map.component_map.ras.valid) 827f1d0525eSRobert Richter dev_dbg(&pdev->dev, "RAS registers not found\n"); 8284112a08dSBen Widawsky 8296c7f4f1eSDan Williams cxlds->component_reg_phys = map.resource; 8304112a08dSBen Widawsky 83157340804SRobert Richter rc = cxl_map_component_regs(&map, &cxlds->regs.component, 83257340804SRobert Richter BIT(CXL_CM_CAP_CAP_ID_RAS)); 833bd09626bSDan Williams if (rc) 834bd09626bSDan Williams dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 835bd09626bSDan Williams 836e764f122SDave Jiang rc = cxl_await_media_ready(cxlds); 837e764f122SDave Jiang if (rc == 0) 838e764f122SDave Jiang cxlds->media_ready = true; 839e764f122SDave Jiang else 840e764f122SDave Jiang dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 841e764f122SDave Jiang 842f279d0bcSDavidlohr Bueso rc = cxl_alloc_irq_vectors(pdev); 843f279d0bcSDavidlohr Bueso if (rc) 844f279d0bcSDavidlohr Bueso return rc; 845f279d0bcSDavidlohr Bueso 84659f8d151SDan Williams rc = cxl_pci_setup_mailbox(mds); 84721e9f767SBen Widawsky if (rc) 84821e9f767SBen Widawsky return rc; 84921e9f767SBen Widawsky 85059f8d151SDan Williams rc = cxl_enumerate_cmds(mds); 85121e9f767SBen Widawsky if (rc) 85221e9f767SBen Widawsky return rc; 85321e9f767SBen Widawsky 85459f8d151SDan Williams rc = cxl_set_timestamp(mds); 855fa884345SJonathan Cameron if (rc) 856fa884345SJonathan Cameron return rc; 857fa884345SJonathan Cameron 85859f8d151SDan Williams rc = cxl_poison_state_init(mds); 859d0abf578SAlison Schofield if (rc) 860d0abf578SAlison Schofield return rc; 861d0abf578SAlison Schofield 86259f8d151SDan Williams rc = cxl_dev_state_identify(mds); 86321e9f767SBen Widawsky if (rc) 86421e9f767SBen Widawsky return rc; 86521e9f767SBen Widawsky 86659f8d151SDan Williams rc = cxl_mem_create_range_info(mds); 867f847502aSIra Weiny if (rc) 868f847502aSIra Weiny return rc; 869f847502aSIra Weiny 870*22c9bb1eSDan Williams cxlmd = devm_cxl_add_memdev(&pdev->dev, cxlds); 87121083f51SDan Williams if (IS_ERR(cxlmd)) 87221083f51SDan Williams return PTR_ERR(cxlmd); 87321083f51SDan Williams 874*22c9bb1eSDan Williams rc = devm_cxl_setup_fw_upload(&pdev->dev, mds); 8759521875bSVishal Verma if (rc) 8769521875bSVishal Verma return rc; 8779521875bSVishal Verma 8781ad3f701SJonathan Cameron pmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_PMU); 8791ad3f701SJonathan Cameron for (i = 0; i < pmu_count; i++) { 8801ad3f701SJonathan Cameron struct cxl_pmu_regs pmu_regs; 8811ad3f701SJonathan Cameron 8821ad3f701SJonathan Cameron rc = cxl_find_regblock_instance(pdev, CXL_REGLOC_RBI_PMU, &map, i); 8831ad3f701SJonathan Cameron if (rc) { 8841ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not find PMU regblock\n"); 8851ad3f701SJonathan Cameron break; 8861ad3f701SJonathan Cameron } 8871ad3f701SJonathan Cameron 8881ad3f701SJonathan Cameron rc = cxl_map_pmu_regs(pdev, &pmu_regs, &map); 8891ad3f701SJonathan Cameron if (rc) { 8901ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not map PMU regs\n"); 8911ad3f701SJonathan Cameron break; 8921ad3f701SJonathan Cameron } 8931ad3f701SJonathan Cameron 8941ad3f701SJonathan Cameron rc = devm_cxl_pmu_add(cxlds->dev, &pmu_regs, cxlmd->id, i, CXL_PMU_MEMDEV); 8951ad3f701SJonathan Cameron if (rc) { 8961ad3f701SJonathan Cameron dev_dbg(&pdev->dev, "Could not add PMU instance\n"); 8971ad3f701SJonathan Cameron break; 8981ad3f701SJonathan Cameron } 8991ad3f701SJonathan Cameron } 9001ad3f701SJonathan Cameron 90159f8d151SDan Williams rc = cxl_event_config(host_bridge, mds); 9026ebe28f9SIra Weiny if (rc) 9036ebe28f9SIra Weiny return rc; 9046ebe28f9SIra Weiny 905248529edSDave Jiang rc = cxl_pci_ras_unmask(pdev); 9062905cb52SDan Williams if (rc) 907248529edSDave Jiang dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 908248529edSDave Jiang 9092905cb52SDan Williams pci_save_state(pdev); 9102905cb52SDan Williams 91121083f51SDan Williams return rc; 91221e9f767SBen Widawsky } 91321e9f767SBen Widawsky 91421e9f767SBen Widawsky static const struct pci_device_id cxl_mem_pci_tbl[] = { 91521e9f767SBen Widawsky /* PCI class code for CXL.mem Type-3 Devices */ 91621e9f767SBen Widawsky { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 91721e9f767SBen Widawsky { /* terminate list */ }, 91821e9f767SBen Widawsky }; 91921e9f767SBen Widawsky MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 92021e9f767SBen Widawsky 9212905cb52SDan Williams static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 9222905cb52SDan Williams { 9232905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9242905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9252905cb52SDan Williams struct device *dev = &cxlmd->dev; 9262905cb52SDan Williams 9272905cb52SDan Williams dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 9282905cb52SDan Williams dev_name(dev)); 9292905cb52SDan Williams pci_restore_state(pdev); 9302905cb52SDan Williams if (device_attach(dev) <= 0) 9312905cb52SDan Williams return PCI_ERS_RESULT_DISCONNECT; 9322905cb52SDan Williams return PCI_ERS_RESULT_RECOVERED; 9332905cb52SDan Williams } 9342905cb52SDan Williams 9352905cb52SDan Williams static void cxl_error_resume(struct pci_dev *pdev) 9362905cb52SDan Williams { 9372905cb52SDan Williams struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 9382905cb52SDan Williams struct cxl_memdev *cxlmd = cxlds->cxlmd; 9392905cb52SDan Williams struct device *dev = &cxlmd->dev; 9402905cb52SDan Williams 9412905cb52SDan Williams dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 9422905cb52SDan Williams dev->driver ? "successful" : "failed"); 9432905cb52SDan Williams } 9442905cb52SDan Williams 9452905cb52SDan Williams static const struct pci_error_handlers cxl_error_handlers = { 9462905cb52SDan Williams .error_detected = cxl_error_detected, 9472905cb52SDan Williams .slot_reset = cxl_slot_reset, 9482905cb52SDan Williams .resume = cxl_error_resume, 9496155ccc9SDave Jiang .cor_error_detected = cxl_cor_error_detected, 9502905cb52SDan Williams }; 9512905cb52SDan Williams 952ed97afb5SBen Widawsky static struct pci_driver cxl_pci_driver = { 95321e9f767SBen Widawsky .name = KBUILD_MODNAME, 95421e9f767SBen Widawsky .id_table = cxl_mem_pci_tbl, 955ed97afb5SBen Widawsky .probe = cxl_pci_probe, 9562905cb52SDan Williams .err_handler = &cxl_error_handlers, 95721e9f767SBen Widawsky .driver = { 95821e9f767SBen Widawsky .probe_type = PROBE_PREFER_ASYNCHRONOUS, 95921e9f767SBen Widawsky }, 96021e9f767SBen Widawsky }; 96121e9f767SBen Widawsky 96221e9f767SBen Widawsky MODULE_LICENSE("GPL v2"); 963ed97afb5SBen Widawsky module_pci_driver(cxl_pci_driver); 96421e9f767SBen Widawsky MODULE_IMPORT_NS(CXL); 965