1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #include <linux/debugfs.h> 4 #include <linux/device.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include "cxlmem.h" 9 #include "cxlpci.h" 10 11 /** 12 * DOC: cxl mem 13 * 14 * CXL memory endpoint devices and switches are CXL capable devices that are 15 * participating in CXL.mem protocol. Their functionality builds on top of the 16 * CXL.io protocol that allows enumerating and configuring components via 17 * standard PCI mechanisms. 18 * 19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem 20 * capability. With the detection of a CXL capable endpoint, the driver will 21 * walk up to find the platform specific port it is connected to, and determine 22 * if there are intervening switches in the path. If there are switches, a 23 * secondary action is to enumerate those (implemented in cxl_core). Finally the 24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use 25 * in higher level operations. 26 */ 27 28 static void enable_suspend(void *data) 29 { 30 cxl_mem_active_dec(); 31 } 32 33 static void remove_debugfs(void *dentry) 34 { 35 debugfs_remove_recursive(dentry); 36 } 37 38 static int cxl_mem_dpa_show(struct seq_file *file, void *data) 39 { 40 struct device *dev = file->private; 41 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 42 43 cxl_dpa_debug(file, cxlmd->cxlds); 44 45 return 0; 46 } 47 48 static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, 49 struct cxl_dport *parent_dport) 50 { 51 struct cxl_port *parent_port = parent_dport->port; 52 struct cxl_dev_state *cxlds = cxlmd->cxlds; 53 struct cxl_port *endpoint, *iter, *down; 54 resource_size_t component_reg_phys; 55 int rc; 56 57 /* 58 * Now that the path to the root is established record all the 59 * intervening ports in the chain. 60 */ 61 for (iter = parent_port, down = NULL; !is_cxl_root(iter); 62 down = iter, iter = to_cxl_port(iter->dev.parent)) { 63 struct cxl_ep *ep; 64 65 ep = cxl_ep_load(iter, cxlmd); 66 ep->next = down; 67 } 68 69 /* 70 * The component registers for an RCD might come from the 71 * host-bridge RCRB if they are not already mapped via the 72 * typical register locator mechanism. 73 */ 74 if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) 75 component_reg_phys = cxl_rcrb_to_component( 76 &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM); 77 else 78 component_reg_phys = cxlds->component_reg_phys; 79 endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, 80 parent_dport); 81 if (IS_ERR(endpoint)) 82 return PTR_ERR(endpoint); 83 84 rc = cxl_endpoint_autoremove(cxlmd, endpoint); 85 if (rc) 86 return rc; 87 88 if (!endpoint->dev.driver) { 89 dev_err(&cxlmd->dev, "%s failed probe\n", 90 dev_name(&endpoint->dev)); 91 return -ENXIO; 92 } 93 94 return 0; 95 } 96 97 static int cxl_debugfs_poison_inject(void *data, u64 dpa) 98 { 99 struct cxl_memdev *cxlmd = data; 100 101 return cxl_inject_poison(cxlmd, dpa); 102 } 103 104 DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_inject_fops, NULL, 105 cxl_debugfs_poison_inject, "%llx\n"); 106 107 static int cxl_debugfs_poison_clear(void *data, u64 dpa) 108 { 109 struct cxl_memdev *cxlmd = data; 110 111 return cxl_clear_poison(cxlmd, dpa); 112 } 113 114 DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_clear_fops, NULL, 115 cxl_debugfs_poison_clear, "%llx\n"); 116 117 static int cxl_mem_probe(struct device *dev) 118 { 119 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 120 struct cxl_dev_state *cxlds = cxlmd->cxlds; 121 struct device *endpoint_parent; 122 struct cxl_port *parent_port; 123 struct cxl_dport *dport; 124 struct dentry *dentry; 125 int rc; 126 127 /* 128 * Someone is trying to reattach this device after it lost its port 129 * connection (an endpoint port previously registered by this memdev was 130 * disabled). This racy check is ok because if the port is still gone, 131 * no harm done, and if the port hierarchy comes back it will re-trigger 132 * this probe. Port rescan and memdev detach work share the same 133 * single-threaded workqueue. 134 */ 135 if (work_pending(&cxlmd->detach_work)) 136 return -EBUSY; 137 138 dentry = cxl_debugfs_create_dir(dev_name(dev)); 139 debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show); 140 141 if (test_bit(CXL_POISON_ENABLED_INJECT, cxlds->poison.enabled_cmds)) 142 debugfs_create_file("inject_poison", 0200, dentry, cxlmd, 143 &cxl_poison_inject_fops); 144 if (test_bit(CXL_POISON_ENABLED_CLEAR, cxlds->poison.enabled_cmds)) 145 debugfs_create_file("clear_poison", 0200, dentry, cxlmd, 146 &cxl_poison_clear_fops); 147 148 rc = devm_add_action_or_reset(dev, remove_debugfs, dentry); 149 if (rc) 150 return rc; 151 152 rc = devm_cxl_enumerate_ports(cxlmd); 153 if (rc) 154 return rc; 155 156 parent_port = cxl_mem_find_port(cxlmd, &dport); 157 if (!parent_port) { 158 dev_err(dev, "CXL port topology not found\n"); 159 return -ENXIO; 160 } 161 162 if (dport->rch) 163 endpoint_parent = parent_port->uport; 164 else 165 endpoint_parent = &parent_port->dev; 166 167 device_lock(endpoint_parent); 168 if (!endpoint_parent->driver) { 169 dev_err(dev, "CXL port topology %s not enabled\n", 170 dev_name(endpoint_parent)); 171 rc = -ENXIO; 172 goto unlock; 173 } 174 175 rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport); 176 unlock: 177 device_unlock(endpoint_parent); 178 put_device(&parent_port->dev); 179 if (rc) 180 return rc; 181 182 if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) { 183 rc = devm_cxl_add_nvdimm(cxlmd); 184 if (rc == -ENODEV) 185 dev_info(dev, "PMEM disabled by platform\n"); 186 else 187 return rc; 188 } 189 190 /* 191 * The kernel may be operating out of CXL memory on this device, 192 * there is no spec defined way to determine whether this device 193 * preserves contents over suspend, and there is no simple way 194 * to arrange for the suspend image to avoid CXL memory which 195 * would setup a circular dependency between PCI resume and save 196 * state restoration. 197 * 198 * TODO: support suspend when all the regions this device is 199 * hosting are locked and covered by the system address map, 200 * i.e. platform firmware owns restoring the HDM configuration 201 * that it locked. 202 */ 203 cxl_mem_active_inc(); 204 return devm_add_action_or_reset(dev, enable_suspend, NULL); 205 } 206 207 static ssize_t trigger_poison_list_store(struct device *dev, 208 struct device_attribute *attr, 209 const char *buf, size_t len) 210 { 211 bool trigger; 212 int rc; 213 214 if (kstrtobool(buf, &trigger) || !trigger) 215 return -EINVAL; 216 217 rc = cxl_trigger_poison_list(to_cxl_memdev(dev)); 218 219 return rc ? rc : len; 220 } 221 static DEVICE_ATTR_WO(trigger_poison_list); 222 223 static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n) 224 { 225 if (a == &dev_attr_trigger_poison_list.attr) { 226 struct device *dev = kobj_to_dev(kobj); 227 228 if (!test_bit(CXL_POISON_ENABLED_LIST, 229 to_cxl_memdev(dev)->cxlds->poison.enabled_cmds)) 230 return 0; 231 } 232 return a->mode; 233 } 234 235 static struct attribute *cxl_mem_attrs[] = { 236 &dev_attr_trigger_poison_list.attr, 237 NULL 238 }; 239 240 static struct attribute_group cxl_mem_group = { 241 .attrs = cxl_mem_attrs, 242 .is_visible = cxl_mem_visible, 243 }; 244 245 __ATTRIBUTE_GROUPS(cxl_mem); 246 247 static struct cxl_driver cxl_mem_driver = { 248 .name = "cxl_mem", 249 .probe = cxl_mem_probe, 250 .id = CXL_DEVICE_MEMORY_EXPANDER, 251 .drv = { 252 .dev_groups = cxl_mem_groups, 253 }, 254 }; 255 256 module_cxl_driver(cxl_mem_driver); 257 258 MODULE_LICENSE("GPL v2"); 259 MODULE_IMPORT_NS(CXL); 260 MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER); 261 /* 262 * create_endpoint() wants to validate port driver attach immediately after 263 * endpoint registration. 264 */ 265 MODULE_SOFTDEP("pre: cxl_port"); 266