1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include <linux/rcuwait.h> 9 #include "cxl.h" 10 11 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 12 #define CXLMDEV_STATUS_OFFSET 0x0 13 #define CXLMDEV_DEV_FATAL BIT(0) 14 #define CXLMDEV_FW_HALT BIT(1) 15 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 16 #define CXLMDEV_MS_NOT_READY 0 17 #define CXLMDEV_MS_READY 1 18 #define CXLMDEV_MS_ERROR 2 19 #define CXLMDEV_MS_DISABLED 3 20 #define CXLMDEV_READY(status) \ 21 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 22 CXLMDEV_MS_READY) 23 #define CXLMDEV_MBOX_IF_READY BIT(4) 24 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 25 #define CXLMDEV_RESET_NEEDED_NOT 0 26 #define CXLMDEV_RESET_NEEDED_COLD 1 27 #define CXLMDEV_RESET_NEEDED_WARM 2 28 #define CXLMDEV_RESET_NEEDED_HOT 3 29 #define CXLMDEV_RESET_NEEDED_CXL 4 30 #define CXLMDEV_RESET_NEEDED(status) \ 31 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 32 CXLMDEV_RESET_NEEDED_NOT) 33 34 /** 35 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 36 * @dev: driver core device object 37 * @cdev: char dev core object for ioctl operations 38 * @cxlds: The device state backing this device 39 * @detach_work: active memdev lost a port in its ancestry 40 * @cxl_nvb: coordinate removal of @cxl_nvd if present 41 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 42 * @endpoint: connection to the CXL port topology for this memory device 43 * @id: id number of this memdev instance. 44 * @depth: endpoint port depth 45 */ 46 struct cxl_memdev { 47 struct device dev; 48 struct cdev cdev; 49 struct cxl_dev_state *cxlds; 50 struct work_struct detach_work; 51 struct cxl_nvdimm_bridge *cxl_nvb; 52 struct cxl_nvdimm *cxl_nvd; 53 struct cxl_port *endpoint; 54 int id; 55 int depth; 56 }; 57 58 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 59 { 60 return container_of(dev, struct cxl_memdev, dev); 61 } 62 63 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 64 { 65 return to_cxl_port(cxled->cxld.dev.parent); 66 } 67 68 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 69 { 70 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 71 } 72 73 static inline struct cxl_memdev * 74 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 75 { 76 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 77 78 return to_cxl_memdev(port->uport_dev); 79 } 80 81 bool is_cxl_memdev(const struct device *dev); 82 static inline bool is_cxl_endpoint(struct cxl_port *port) 83 { 84 return is_cxl_memdev(port->uport_dev); 85 } 86 87 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 88 struct cxl_memdev_state; 89 int cxl_memdev_setup_fw_upload(struct cxl_memdev_state *mds); 90 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 91 resource_size_t base, resource_size_t len, 92 resource_size_t skipped); 93 94 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 95 struct cxl_memdev *cxlmd) 96 { 97 if (!port) 98 return NULL; 99 100 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 101 } 102 103 /** 104 * struct cxl_mbox_cmd - A command to be submitted to hardware. 105 * @opcode: (input) The command set and command submitted to hardware. 106 * @payload_in: (input) Pointer to the input payload. 107 * @payload_out: (output) Pointer to the output payload. Must be allocated by 108 * the caller. 109 * @size_in: (input) Number of bytes to load from @payload_in. 110 * @size_out: (input) Max number of bytes loaded into @payload_out. 111 * (output) Number of bytes generated by the device. For fixed size 112 * outputs commands this is always expected to be deterministic. For 113 * variable sized output commands, it tells the exact number of bytes 114 * written. 115 * @min_out: (input) internal command output payload size validation 116 * @poll_count: (input) Number of timeouts to attempt. 117 * @poll_interval_ms: (input) Time between mailbox background command polling 118 * interval timeouts. 119 * @return_code: (output) Error code returned from hardware. 120 * 121 * This is the primary mechanism used to send commands to the hardware. 122 * All the fields except @payload_* correspond exactly to the fields described in 123 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 124 * @payload_out are written to, and read from the Command Payload Registers 125 * defined in CXL 2.0 8.2.8.4.8. 126 */ 127 struct cxl_mbox_cmd { 128 u16 opcode; 129 void *payload_in; 130 void *payload_out; 131 size_t size_in; 132 size_t size_out; 133 size_t min_out; 134 int poll_count; 135 int poll_interval_ms; 136 u16 return_code; 137 }; 138 139 /* 140 * Per CXL 3.0 Section 8.2.8.4.5.1 141 */ 142 #define CMD_CMD_RC_TABLE \ 143 C(SUCCESS, 0, NULL), \ 144 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 145 C(INPUT, -ENXIO, "cmd input was invalid"), \ 146 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 147 C(INTERNAL, -ENXIO, "internal device error"), \ 148 C(RETRY, -ENXIO, "temporary error, retry once"), \ 149 C(BUSY, -ENXIO, "ongoing background operation"), \ 150 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 151 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 152 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 153 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 154 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 155 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 156 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 157 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 158 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 159 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 160 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 161 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 162 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 163 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 164 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 165 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 166 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 167 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 168 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 169 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 170 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 171 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 172 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 173 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 174 175 #undef C 176 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 177 enum { CMD_CMD_RC_TABLE }; 178 #undef C 179 #define C(a, b, c) { b, c } 180 struct cxl_mbox_cmd_rc { 181 int err; 182 const char *desc; 183 }; 184 185 static const 186 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 187 #undef C 188 189 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 190 { 191 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 192 } 193 194 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 195 { 196 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 197 } 198 199 /* 200 * CXL 2.0 - Memory capacity multiplier 201 * See Section 8.2.9.5 202 * 203 * Volatile, Persistent, and Partition capacities are specified to be in 204 * multiples of 256MB - define a multiplier to convert to/from bytes. 205 */ 206 #define CXL_CAPACITY_MULTIPLIER SZ_256M 207 208 /* 209 * Event Interrupt Policy 210 * 211 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 212 */ 213 enum cxl_event_int_mode { 214 CXL_INT_NONE = 0x00, 215 CXL_INT_MSI_MSIX = 0x01, 216 CXL_INT_FW = 0x02 217 }; 218 struct cxl_event_interrupt_policy { 219 u8 info_settings; 220 u8 warn_settings; 221 u8 failure_settings; 222 u8 fatal_settings; 223 } __packed; 224 225 /** 226 * struct cxl_event_state - Event log driver state 227 * 228 * @buf: Buffer to receive event data 229 * @log_lock: Serialize event_buf and log use 230 */ 231 struct cxl_event_state { 232 struct cxl_get_event_payload *buf; 233 struct mutex log_lock; 234 }; 235 236 /* Device enabled poison commands */ 237 enum poison_cmd_enabled_bits { 238 CXL_POISON_ENABLED_LIST, 239 CXL_POISON_ENABLED_INJECT, 240 CXL_POISON_ENABLED_CLEAR, 241 CXL_POISON_ENABLED_SCAN_CAPS, 242 CXL_POISON_ENABLED_SCAN_MEDIA, 243 CXL_POISON_ENABLED_SCAN_RESULTS, 244 CXL_POISON_ENABLED_MAX 245 }; 246 247 /** 248 * struct cxl_poison_state - Driver poison state info 249 * 250 * @max_errors: Maximum media error records held in device cache 251 * @enabled_cmds: All poison commands enabled in the CEL 252 * @list_out: The poison list payload returned by device 253 * @lock: Protect reads of the poison list 254 * 255 * Reads of the poison list are synchronized to ensure that a reader 256 * does not get an incomplete list because their request overlapped 257 * (was interrupted or preceded by) another read request of the same 258 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 259 */ 260 struct cxl_poison_state { 261 u32 max_errors; 262 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 263 struct cxl_mbox_poison_out *list_out; 264 struct mutex lock; /* Protect reads of poison list */ 265 }; 266 267 /* 268 * Get FW Info 269 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 270 */ 271 struct cxl_mbox_get_fw_info { 272 u8 num_slots; 273 u8 slot_info; 274 u8 activation_cap; 275 u8 reserved[13]; 276 char slot_1_revision[16]; 277 char slot_2_revision[16]; 278 char slot_3_revision[16]; 279 char slot_4_revision[16]; 280 } __packed; 281 282 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 283 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 284 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 285 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 286 287 /* 288 * Transfer FW Input Payload 289 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 290 */ 291 struct cxl_mbox_transfer_fw { 292 u8 action; 293 u8 slot; 294 u8 reserved[2]; 295 __le32 offset; 296 u8 reserved2[0x78]; 297 u8 data[]; 298 } __packed; 299 300 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 301 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 302 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 303 #define CXL_FW_TRANSFER_ACTION_END 0x3 304 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 305 306 /* 307 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 308 * and for each part transferred in a Transfer FW command. 309 */ 310 #define CXL_FW_TRANSFER_ALIGNMENT 128 311 312 /* 313 * Activate FW Input Payload 314 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 315 */ 316 struct cxl_mbox_activate_fw { 317 u8 action; 318 u8 slot; 319 } __packed; 320 321 #define CXL_FW_ACTIVATE_ONLINE 0x0 322 #define CXL_FW_ACTIVATE_OFFLINE 0x1 323 324 /* FW state bits */ 325 #define CXL_FW_STATE_BITS 32 326 #define CXL_FW_CANCEL BIT(0) 327 328 /** 329 * struct cxl_fw_state - Firmware upload / activation state 330 * 331 * @state: fw_uploader state bitmask 332 * @oneshot: whether the fw upload fits in a single transfer 333 * @num_slots: Number of FW slots available 334 * @cur_slot: Slot number currently active 335 * @next_slot: Slot number for the new firmware 336 */ 337 struct cxl_fw_state { 338 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 339 bool oneshot; 340 int num_slots; 341 int cur_slot; 342 int next_slot; 343 }; 344 345 /** 346 * struct cxl_security_state - Device security state 347 * 348 * @state: state of last security operation 349 * @poll: polling for sanitization is enabled, device has no mbox irq support 350 * @poll_tmo_secs: polling timeout 351 * @poll_dwork: polling work item 352 * @sanitize_node: sanitation sysfs file to notify 353 */ 354 struct cxl_security_state { 355 unsigned long state; 356 bool poll; 357 int poll_tmo_secs; 358 struct delayed_work poll_dwork; 359 struct kernfs_node *sanitize_node; 360 }; 361 362 /* 363 * enum cxl_devtype - delineate type-2 from a generic type-3 device 364 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or 365 * HDM-DB, no requirement that this device implements a 366 * mailbox, or other memory-device-standard manageability 367 * flows. 368 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with 369 * HDM-H and class-mandatory memory device registers 370 */ 371 enum cxl_devtype { 372 CXL_DEVTYPE_DEVMEM, 373 CXL_DEVTYPE_CLASSMEM, 374 }; 375 376 /** 377 * struct cxl_dev_state - The driver device state 378 * 379 * cxl_dev_state represents the CXL driver/device state. It provides an 380 * interface to mailbox commands as well as some cached data about the device. 381 * Currently only memory devices are represented. 382 * 383 * @dev: The device associated with this CXL state 384 * @cxlmd: The device representing the CXL.mem capabilities of @dev 385 * @regs: Parsed register blocks 386 * @cxl_dvsec: Offset to the PCIe device DVSEC 387 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 388 * @media_ready: Indicate whether the device media is usable 389 * @dpa_res: Overall DPA resource tree for the device 390 * @pmem_res: Active Persistent memory capacity configuration 391 * @ram_res: Active Volatile memory capacity configuration 392 * @component_reg_phys: register base of component registers 393 * @serial: PCIe Device Serial Number 394 * @type: Generic Memory Class device or Vendor Specific Memory device 395 */ 396 struct cxl_dev_state { 397 struct device *dev; 398 struct cxl_memdev *cxlmd; 399 struct cxl_regs regs; 400 int cxl_dvsec; 401 bool rcd; 402 bool media_ready; 403 struct resource dpa_res; 404 struct resource pmem_res; 405 struct resource ram_res; 406 resource_size_t component_reg_phys; 407 u64 serial; 408 enum cxl_devtype type; 409 }; 410 411 /** 412 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 413 * 414 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 415 * common memory device functionality like the presence of a mailbox and 416 * the functionality related to that like Identify Memory Device and Get 417 * Partition Info 418 * @cxlds: Core driver state common across Type-2 and Type-3 devices 419 * @payload_size: Size of space for payload 420 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 421 * @lsa_size: Size of Label Storage Area 422 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 423 * @mbox_mutex: Mutex to synchronize mailbox access. 424 * @firmware_version: Firmware version for the memory device. 425 * @enabled_cmds: Hardware commands found enabled in CEL. 426 * @exclusive_cmds: Commands that are kernel-internal only 427 * @total_bytes: sum of all possible capacities 428 * @volatile_only_bytes: hard volatile capacity 429 * @persistent_only_bytes: hard persistent capacity 430 * @partition_align_bytes: alignment size for partition-able capacity 431 * @active_volatile_bytes: sum of hard + soft volatile 432 * @active_persistent_bytes: sum of hard + soft persistent 433 * @next_volatile_bytes: volatile capacity change pending device reset 434 * @next_persistent_bytes: persistent capacity change pending device reset 435 * @event: event log driver state 436 * @poison: poison driver state info 437 * @fw: firmware upload / activation state 438 * @mbox_send: @dev specific transport for transmitting mailbox commands 439 * 440 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 441 * details on capacity parameters. 442 */ 443 struct cxl_memdev_state { 444 struct cxl_dev_state cxlds; 445 size_t payload_size; 446 size_t lsa_size; 447 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 448 char firmware_version[0x10]; 449 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 450 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 451 u64 total_bytes; 452 u64 volatile_only_bytes; 453 u64 persistent_only_bytes; 454 u64 partition_align_bytes; 455 u64 active_volatile_bytes; 456 u64 active_persistent_bytes; 457 u64 next_volatile_bytes; 458 u64 next_persistent_bytes; 459 struct cxl_event_state event; 460 struct cxl_poison_state poison; 461 struct cxl_security_state security; 462 struct cxl_fw_state fw; 463 464 struct rcuwait mbox_wait; 465 int (*mbox_send)(struct cxl_memdev_state *mds, 466 struct cxl_mbox_cmd *cmd); 467 }; 468 469 static inline struct cxl_memdev_state * 470 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 471 { 472 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 473 return NULL; 474 return container_of(cxlds, struct cxl_memdev_state, cxlds); 475 } 476 477 enum cxl_opcode { 478 CXL_MBOX_OP_INVALID = 0x0000, 479 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 480 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 481 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 482 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 483 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 484 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 485 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 486 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 487 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 488 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 489 CXL_MBOX_OP_GET_LOG = 0x0401, 490 CXL_MBOX_OP_IDENTIFY = 0x4000, 491 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 492 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 493 CXL_MBOX_OP_GET_LSA = 0x4102, 494 CXL_MBOX_OP_SET_LSA = 0x4103, 495 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 496 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 497 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 498 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 499 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 500 CXL_MBOX_OP_GET_POISON = 0x4300, 501 CXL_MBOX_OP_INJECT_POISON = 0x4301, 502 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 503 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 504 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 505 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 506 CXL_MBOX_OP_SANITIZE = 0x4400, 507 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 508 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 509 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 510 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 511 CXL_MBOX_OP_UNLOCK = 0x4503, 512 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 513 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 514 CXL_MBOX_OP_MAX = 0x10000 515 }; 516 517 #define DEFINE_CXL_CEL_UUID \ 518 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 519 0x3b, 0x3f, 0x17) 520 521 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 522 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 523 0x40, 0x3d, 0x86) 524 525 struct cxl_mbox_get_supported_logs { 526 __le16 entries; 527 u8 rsvd[6]; 528 struct cxl_gsl_entry { 529 uuid_t uuid; 530 __le32 size; 531 } __packed entry[]; 532 } __packed; 533 534 struct cxl_cel_entry { 535 __le16 opcode; 536 __le16 effect; 537 } __packed; 538 539 struct cxl_mbox_get_log { 540 uuid_t uuid; 541 __le32 offset; 542 __le32 length; 543 } __packed; 544 545 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 546 struct cxl_mbox_identify { 547 char fw_revision[0x10]; 548 __le64 total_capacity; 549 __le64 volatile_capacity; 550 __le64 persistent_capacity; 551 __le64 partition_align; 552 __le16 info_event_log_size; 553 __le16 warning_event_log_size; 554 __le16 failure_event_log_size; 555 __le16 fatal_event_log_size; 556 __le32 lsa_size; 557 u8 poison_list_max_mer[3]; 558 __le16 inject_poison_limit; 559 u8 poison_caps; 560 u8 qos_telemetry_caps; 561 } __packed; 562 563 /* 564 * Common Event Record Format 565 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 566 */ 567 struct cxl_event_record_hdr { 568 uuid_t id; 569 u8 length; 570 u8 flags[3]; 571 __le16 handle; 572 __le16 related_handle; 573 __le64 timestamp; 574 u8 maint_op_class; 575 u8 reserved[15]; 576 } __packed; 577 578 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 579 struct cxl_event_record_raw { 580 struct cxl_event_record_hdr hdr; 581 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 582 } __packed; 583 584 /* 585 * Get Event Records output payload 586 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 587 */ 588 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 589 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 590 struct cxl_get_event_payload { 591 u8 flags; 592 u8 reserved1; 593 __le16 overflow_err_count; 594 __le64 first_overflow_timestamp; 595 __le64 last_overflow_timestamp; 596 __le16 record_count; 597 u8 reserved2[10]; 598 struct cxl_event_record_raw records[]; 599 } __packed; 600 601 /* 602 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 603 */ 604 enum cxl_event_log_type { 605 CXL_EVENT_TYPE_INFO = 0x00, 606 CXL_EVENT_TYPE_WARN, 607 CXL_EVENT_TYPE_FAIL, 608 CXL_EVENT_TYPE_FATAL, 609 CXL_EVENT_TYPE_MAX 610 }; 611 612 /* 613 * Clear Event Records input payload 614 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 615 */ 616 struct cxl_mbox_clear_event_payload { 617 u8 event_log; /* enum cxl_event_log_type */ 618 u8 clear_flags; 619 u8 nr_recs; 620 u8 reserved[3]; 621 __le16 handles[]; 622 } __packed; 623 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 624 625 /* 626 * General Media Event Record 627 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 628 */ 629 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 630 struct cxl_event_gen_media { 631 struct cxl_event_record_hdr hdr; 632 __le64 phys_addr; 633 u8 descriptor; 634 u8 type; 635 u8 transaction_type; 636 u8 validity_flags[2]; 637 u8 channel; 638 u8 rank; 639 u8 device[3]; 640 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 641 u8 reserved[46]; 642 } __packed; 643 644 /* 645 * DRAM Event Record - DER 646 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 647 */ 648 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 649 struct cxl_event_dram { 650 struct cxl_event_record_hdr hdr; 651 __le64 phys_addr; 652 u8 descriptor; 653 u8 type; 654 u8 transaction_type; 655 u8 validity_flags[2]; 656 u8 channel; 657 u8 rank; 658 u8 nibble_mask[3]; 659 u8 bank_group; 660 u8 bank; 661 u8 row[3]; 662 u8 column[2]; 663 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 664 u8 reserved[0x17]; 665 } __packed; 666 667 /* 668 * Get Health Info Record 669 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 670 */ 671 struct cxl_get_health_info { 672 u8 health_status; 673 u8 media_status; 674 u8 add_status; 675 u8 life_used; 676 u8 device_temp[2]; 677 u8 dirty_shutdown_cnt[4]; 678 u8 cor_vol_err_cnt[4]; 679 u8 cor_per_err_cnt[4]; 680 } __packed; 681 682 /* 683 * Memory Module Event Record 684 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 685 */ 686 struct cxl_event_mem_module { 687 struct cxl_event_record_hdr hdr; 688 u8 event_type; 689 struct cxl_get_health_info info; 690 u8 reserved[0x3d]; 691 } __packed; 692 693 struct cxl_mbox_get_partition_info { 694 __le64 active_volatile_cap; 695 __le64 active_persistent_cap; 696 __le64 next_volatile_cap; 697 __le64 next_persistent_cap; 698 } __packed; 699 700 struct cxl_mbox_get_lsa { 701 __le32 offset; 702 __le32 length; 703 } __packed; 704 705 struct cxl_mbox_set_lsa { 706 __le32 offset; 707 __le32 reserved; 708 u8 data[]; 709 } __packed; 710 711 struct cxl_mbox_set_partition_info { 712 __le64 volatile_capacity; 713 u8 flags; 714 } __packed; 715 716 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 717 718 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 719 struct cxl_mbox_set_timestamp_in { 720 __le64 timestamp; 721 722 } __packed; 723 724 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 725 struct cxl_mbox_poison_in { 726 __le64 offset; 727 __le64 length; 728 } __packed; 729 730 struct cxl_mbox_poison_out { 731 u8 flags; 732 u8 rsvd1; 733 __le64 overflow_ts; 734 __le16 count; 735 u8 rsvd2[20]; 736 struct cxl_poison_record { 737 __le64 address; 738 __le32 length; 739 __le32 rsvd; 740 } __packed record[]; 741 } __packed; 742 743 /* 744 * Get Poison List address field encodes the starting 745 * address of poison, and the source of the poison. 746 */ 747 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 748 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 749 750 /* Get Poison List record length is in units of 64 bytes */ 751 #define CXL_POISON_LEN_MULT 64 752 753 /* Kernel defined maximum for a list of poison errors */ 754 #define CXL_POISON_LIST_MAX 1024 755 756 /* Get Poison List: Payload out flags */ 757 #define CXL_POISON_FLAG_MORE BIT(0) 758 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 759 #define CXL_POISON_FLAG_SCANNING BIT(2) 760 761 /* Get Poison List: Poison Source */ 762 #define CXL_POISON_SOURCE_UNKNOWN 0 763 #define CXL_POISON_SOURCE_EXTERNAL 1 764 #define CXL_POISON_SOURCE_INTERNAL 2 765 #define CXL_POISON_SOURCE_INJECTED 3 766 #define CXL_POISON_SOURCE_VENDOR 7 767 768 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 769 struct cxl_mbox_inject_poison { 770 __le64 address; 771 }; 772 773 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 774 struct cxl_mbox_clear_poison { 775 __le64 address; 776 u8 write_data[CXL_POISON_LEN_MULT]; 777 } __packed; 778 779 /** 780 * struct cxl_mem_command - Driver representation of a memory device command 781 * @info: Command information as it exists for the UAPI 782 * @opcode: The actual bits used for the mailbox protocol 783 * @flags: Set of flags effecting driver behavior. 784 * 785 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 786 * will be enabled by the driver regardless of what hardware may have 787 * advertised. 788 * 789 * The cxl_mem_command is the driver's internal representation of commands that 790 * are supported by the driver. Some of these commands may not be supported by 791 * the hardware. The driver will use @info to validate the fields passed in by 792 * the user then submit the @opcode to the hardware. 793 * 794 * See struct cxl_command_info. 795 */ 796 struct cxl_mem_command { 797 struct cxl_command_info info; 798 enum cxl_opcode opcode; 799 u32 flags; 800 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 801 }; 802 803 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 804 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 805 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 806 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 807 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 808 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 809 810 /* set passphrase input payload */ 811 struct cxl_set_pass { 812 u8 type; 813 u8 reserved[31]; 814 /* CXL field using NVDIMM define, same length */ 815 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 816 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 817 } __packed; 818 819 /* disable passphrase input payload */ 820 struct cxl_disable_pass { 821 u8 type; 822 u8 reserved[31]; 823 u8 pass[NVDIMM_PASSPHRASE_LEN]; 824 } __packed; 825 826 /* passphrase secure erase payload */ 827 struct cxl_pass_erase { 828 u8 type; 829 u8 reserved[31]; 830 u8 pass[NVDIMM_PASSPHRASE_LEN]; 831 } __packed; 832 833 enum { 834 CXL_PMEM_SEC_PASS_MASTER = 0, 835 CXL_PMEM_SEC_PASS_USER, 836 }; 837 838 int cxl_internal_send_cmd(struct cxl_memdev_state *mds, 839 struct cxl_mbox_cmd *cmd); 840 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 841 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 842 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 843 int cxl_mem_create_range_info(struct cxl_memdev_state *mds); 844 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev); 845 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 846 unsigned long *cmds); 847 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 848 unsigned long *cmds); 849 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 850 int cxl_set_timestamp(struct cxl_memdev_state *mds); 851 int cxl_poison_state_init(struct cxl_memdev_state *mds); 852 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 853 struct cxl_region *cxlr); 854 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 855 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 856 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 857 858 #ifdef CONFIG_CXL_SUSPEND 859 void cxl_mem_active_inc(void); 860 void cxl_mem_active_dec(void); 861 #else 862 static inline void cxl_mem_active_inc(void) 863 { 864 } 865 static inline void cxl_mem_active_dec(void) 866 { 867 } 868 #endif 869 870 int cxl_mem_sanitize(struct cxl_memdev_state *mds, u16 cmd); 871 872 struct cxl_hdm { 873 struct cxl_component_regs regs; 874 unsigned int decoder_count; 875 unsigned int target_count; 876 unsigned int interleave_mask; 877 struct cxl_port *port; 878 }; 879 880 struct seq_file; 881 struct dentry *cxl_debugfs_create_dir(const char *dir); 882 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 883 #endif /* __CXL_MEM_H__ */ 884