1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include "cxl.h" 8 9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 10 #define CXLMDEV_STATUS_OFFSET 0x0 11 #define CXLMDEV_DEV_FATAL BIT(0) 12 #define CXLMDEV_FW_HALT BIT(1) 13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 14 #define CXLMDEV_MS_NOT_READY 0 15 #define CXLMDEV_MS_READY 1 16 #define CXLMDEV_MS_ERROR 2 17 #define CXLMDEV_MS_DISABLED 3 18 #define CXLMDEV_READY(status) \ 19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 20 CXLMDEV_MS_READY) 21 #define CXLMDEV_MBOX_IF_READY BIT(4) 22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 23 #define CXLMDEV_RESET_NEEDED_NOT 0 24 #define CXLMDEV_RESET_NEEDED_COLD 1 25 #define CXLMDEV_RESET_NEEDED_WARM 2 26 #define CXLMDEV_RESET_NEEDED_HOT 3 27 #define CXLMDEV_RESET_NEEDED_CXL 4 28 #define CXLMDEV_RESET_NEEDED(status) \ 29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 30 CXLMDEV_RESET_NEEDED_NOT) 31 32 /** 33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 34 * @dev: driver core device object 35 * @cdev: char dev core object for ioctl operations 36 * @cxlds: The device state backing this device 37 * @detach_work: active memdev lost a port in its ancestry 38 * @cxl_nvb: coordinate removal of @cxl_nvd if present 39 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 40 * @id: id number of this memdev instance. 41 */ 42 struct cxl_memdev { 43 struct device dev; 44 struct cdev cdev; 45 struct cxl_dev_state *cxlds; 46 struct work_struct detach_work; 47 struct cxl_nvdimm_bridge *cxl_nvb; 48 struct cxl_nvdimm *cxl_nvd; 49 int id; 50 }; 51 52 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 53 { 54 return container_of(dev, struct cxl_memdev, dev); 55 } 56 57 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 58 { 59 return to_cxl_port(cxled->cxld.dev.parent); 60 } 61 62 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 63 { 64 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 65 } 66 67 static inline struct cxl_memdev * 68 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 69 { 70 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 71 72 return to_cxl_memdev(port->uport); 73 } 74 75 bool is_cxl_memdev(struct device *dev); 76 static inline bool is_cxl_endpoint(struct cxl_port *port) 77 { 78 return is_cxl_memdev(port->uport); 79 } 80 81 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 82 83 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 84 struct cxl_memdev *cxlmd) 85 { 86 if (!port) 87 return NULL; 88 89 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 90 } 91 92 /** 93 * struct cxl_mbox_cmd - A command to be submitted to hardware. 94 * @opcode: (input) The command set and command submitted to hardware. 95 * @payload_in: (input) Pointer to the input payload. 96 * @payload_out: (output) Pointer to the output payload. Must be allocated by 97 * the caller. 98 * @size_in: (input) Number of bytes to load from @payload_in. 99 * @size_out: (input) Max number of bytes loaded into @payload_out. 100 * (output) Number of bytes generated by the device. For fixed size 101 * outputs commands this is always expected to be deterministic. For 102 * variable sized output commands, it tells the exact number of bytes 103 * written. 104 * @min_out: (input) internal command output payload size validation 105 * @return_code: (output) Error code returned from hardware. 106 * 107 * This is the primary mechanism used to send commands to the hardware. 108 * All the fields except @payload_* correspond exactly to the fields described in 109 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 110 * @payload_out are written to, and read from the Command Payload Registers 111 * defined in CXL 2.0 8.2.8.4.8. 112 */ 113 struct cxl_mbox_cmd { 114 u16 opcode; 115 void *payload_in; 116 void *payload_out; 117 size_t size_in; 118 size_t size_out; 119 size_t min_out; 120 u16 return_code; 121 }; 122 123 /* 124 * Per CXL 2.0 Section 8.2.8.4.5.1 125 */ 126 #define CMD_CMD_RC_TABLE \ 127 C(SUCCESS, 0, NULL), \ 128 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 129 C(INPUT, -ENXIO, "cmd input was invalid"), \ 130 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 131 C(INTERNAL, -ENXIO, "internal device error"), \ 132 C(RETRY, -ENXIO, "temporary error, retry once"), \ 133 C(BUSY, -ENXIO, "ongoing background operation"), \ 134 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 135 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 136 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 137 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 138 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 139 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 140 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 141 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 142 C(PADDR, -ENXIO, "physical address specified is invalid"), \ 143 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 144 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 145 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 146 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 147 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 148 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 149 C(PAYLOADLEN, -ENXIO, "invalid payload length") 150 151 #undef C 152 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 153 enum { CMD_CMD_RC_TABLE }; 154 #undef C 155 #define C(a, b, c) { b, c } 156 struct cxl_mbox_cmd_rc { 157 int err; 158 const char *desc; 159 }; 160 161 static const 162 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 163 #undef C 164 165 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 166 { 167 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 168 } 169 170 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 171 { 172 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 173 } 174 175 /* 176 * CXL 2.0 - Memory capacity multiplier 177 * See Section 8.2.9.5 178 * 179 * Volatile, Persistent, and Partition capacities are specified to be in 180 * multiples of 256MB - define a multiplier to convert to/from bytes. 181 */ 182 #define CXL_CAPACITY_MULTIPLIER SZ_256M 183 184 /** 185 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 186 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE 187 * @ranges: Number of active HDM ranges this device uses. 188 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 189 */ 190 struct cxl_endpoint_dvsec_info { 191 bool mem_enabled; 192 int ranges; 193 struct range dvsec_range[2]; 194 }; 195 196 /** 197 * struct cxl_dev_state - The driver device state 198 * 199 * cxl_dev_state represents the CXL driver/device state. It provides an 200 * interface to mailbox commands as well as some cached data about the device. 201 * Currently only memory devices are represented. 202 * 203 * @dev: The device associated with this CXL state 204 * @cxlmd: The device representing the CXL.mem capabilities of @dev 205 * @regs: Parsed register blocks 206 * @cxl_dvsec: Offset to the PCIe device DVSEC 207 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 208 * @payload_size: Size of space for payload 209 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 210 * @lsa_size: Size of Label Storage Area 211 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 212 * @mbox_mutex: Mutex to synchronize mailbox access. 213 * @firmware_version: Firmware version for the memory device. 214 * @enabled_cmds: Hardware commands found enabled in CEL. 215 * @exclusive_cmds: Commands that are kernel-internal only 216 * @dpa_res: Overall DPA resource tree for the device 217 * @pmem_res: Active Persistent memory capacity configuration 218 * @ram_res: Active Volatile memory capacity configuration 219 * @total_bytes: sum of all possible capacities 220 * @volatile_only_bytes: hard volatile capacity 221 * @persistent_only_bytes: hard persistent capacity 222 * @partition_align_bytes: alignment size for partition-able capacity 223 * @active_volatile_bytes: sum of hard + soft volatile 224 * @active_persistent_bytes: sum of hard + soft persistent 225 * @next_volatile_bytes: volatile capacity change pending device reset 226 * @next_persistent_bytes: persistent capacity change pending device reset 227 * @component_reg_phys: register base of component registers 228 * @info: Cached DVSEC information about the device. 229 * @serial: PCIe Device Serial Number 230 * @doe_mbs: PCI DOE mailbox array 231 * @mbox_send: @dev specific transport for transmitting mailbox commands 232 * 233 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 234 * details on capacity parameters. 235 */ 236 struct cxl_dev_state { 237 struct device *dev; 238 struct cxl_memdev *cxlmd; 239 240 struct cxl_regs regs; 241 int cxl_dvsec; 242 243 bool rcd; 244 size_t payload_size; 245 size_t lsa_size; 246 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 247 char firmware_version[0x10]; 248 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 249 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 250 251 struct resource dpa_res; 252 struct resource pmem_res; 253 struct resource ram_res; 254 u64 total_bytes; 255 u64 volatile_only_bytes; 256 u64 persistent_only_bytes; 257 u64 partition_align_bytes; 258 259 u64 active_volatile_bytes; 260 u64 active_persistent_bytes; 261 u64 next_volatile_bytes; 262 u64 next_persistent_bytes; 263 264 resource_size_t component_reg_phys; 265 u64 serial; 266 267 struct xarray doe_mbs; 268 269 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 270 }; 271 272 enum cxl_opcode { 273 CXL_MBOX_OP_INVALID = 0x0000, 274 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 275 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 276 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 277 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 278 CXL_MBOX_OP_GET_LOG = 0x0401, 279 CXL_MBOX_OP_IDENTIFY = 0x4000, 280 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 281 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 282 CXL_MBOX_OP_GET_LSA = 0x4102, 283 CXL_MBOX_OP_SET_LSA = 0x4103, 284 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 285 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 286 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 287 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 288 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 289 CXL_MBOX_OP_GET_POISON = 0x4300, 290 CXL_MBOX_OP_INJECT_POISON = 0x4301, 291 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 292 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 293 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 294 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 295 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 296 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 297 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 298 CXL_MBOX_OP_UNLOCK = 0x4503, 299 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 300 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 301 CXL_MBOX_OP_MAX = 0x10000 302 }; 303 304 #define DEFINE_CXL_CEL_UUID \ 305 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 306 0x3b, 0x3f, 0x17) 307 308 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 309 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 310 0x40, 0x3d, 0x86) 311 312 struct cxl_mbox_get_supported_logs { 313 __le16 entries; 314 u8 rsvd[6]; 315 struct cxl_gsl_entry { 316 uuid_t uuid; 317 __le32 size; 318 } __packed entry[]; 319 } __packed; 320 321 struct cxl_cel_entry { 322 __le16 opcode; 323 __le16 effect; 324 } __packed; 325 326 struct cxl_mbox_get_log { 327 uuid_t uuid; 328 __le32 offset; 329 __le32 length; 330 } __packed; 331 332 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 333 struct cxl_mbox_identify { 334 char fw_revision[0x10]; 335 __le64 total_capacity; 336 __le64 volatile_capacity; 337 __le64 persistent_capacity; 338 __le64 partition_align; 339 __le16 info_event_log_size; 340 __le16 warning_event_log_size; 341 __le16 failure_event_log_size; 342 __le16 fatal_event_log_size; 343 __le32 lsa_size; 344 u8 poison_list_max_mer[3]; 345 __le16 inject_poison_limit; 346 u8 poison_caps; 347 u8 qos_telemetry_caps; 348 } __packed; 349 350 struct cxl_mbox_get_partition_info { 351 __le64 active_volatile_cap; 352 __le64 active_persistent_cap; 353 __le64 next_volatile_cap; 354 __le64 next_persistent_cap; 355 } __packed; 356 357 struct cxl_mbox_get_lsa { 358 __le32 offset; 359 __le32 length; 360 } __packed; 361 362 struct cxl_mbox_set_lsa { 363 __le32 offset; 364 __le32 reserved; 365 u8 data[]; 366 } __packed; 367 368 struct cxl_mbox_set_partition_info { 369 __le64 volatile_capacity; 370 u8 flags; 371 } __packed; 372 373 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 374 375 /** 376 * struct cxl_mem_command - Driver representation of a memory device command 377 * @info: Command information as it exists for the UAPI 378 * @opcode: The actual bits used for the mailbox protocol 379 * @flags: Set of flags effecting driver behavior. 380 * 381 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 382 * will be enabled by the driver regardless of what hardware may have 383 * advertised. 384 * 385 * The cxl_mem_command is the driver's internal representation of commands that 386 * are supported by the driver. Some of these commands may not be supported by 387 * the hardware. The driver will use @info to validate the fields passed in by 388 * the user then submit the @opcode to the hardware. 389 * 390 * See struct cxl_command_info. 391 */ 392 struct cxl_mem_command { 393 struct cxl_command_info info; 394 enum cxl_opcode opcode; 395 u32 flags; 396 #define CXL_CMD_FLAG_NONE 0 397 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 398 }; 399 400 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 401 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 402 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 403 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 404 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 405 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 406 407 /* set passphrase input payload */ 408 struct cxl_set_pass { 409 u8 type; 410 u8 reserved[31]; 411 /* CXL field using NVDIMM define, same length */ 412 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 413 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 414 } __packed; 415 416 /* disable passphrase input payload */ 417 struct cxl_disable_pass { 418 u8 type; 419 u8 reserved[31]; 420 u8 pass[NVDIMM_PASSPHRASE_LEN]; 421 } __packed; 422 423 /* passphrase secure erase payload */ 424 struct cxl_pass_erase { 425 u8 type; 426 u8 reserved[31]; 427 u8 pass[NVDIMM_PASSPHRASE_LEN]; 428 } __packed; 429 430 enum { 431 CXL_PMEM_SEC_PASS_MASTER = 0, 432 CXL_PMEM_SEC_PASS_USER, 433 }; 434 435 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds, 436 struct cxl_mbox_cmd *cmd); 437 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 438 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 439 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 440 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 441 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 442 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 443 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 444 #ifdef CONFIG_CXL_SUSPEND 445 void cxl_mem_active_inc(void); 446 void cxl_mem_active_dec(void); 447 #else 448 static inline void cxl_mem_active_inc(void) 449 { 450 } 451 static inline void cxl_mem_active_dec(void) 452 { 453 } 454 #endif 455 456 struct cxl_hdm { 457 struct cxl_component_regs regs; 458 unsigned int decoder_count; 459 unsigned int target_count; 460 unsigned int interleave_mask; 461 struct cxl_port *port; 462 }; 463 464 struct seq_file; 465 struct dentry *cxl_debugfs_create_dir(const char *dir); 466 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 467 #endif /* __CXL_MEM_H__ */ 468