1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include "cxl.h" 8 9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 10 #define CXLMDEV_STATUS_OFFSET 0x0 11 #define CXLMDEV_DEV_FATAL BIT(0) 12 #define CXLMDEV_FW_HALT BIT(1) 13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 14 #define CXLMDEV_MS_NOT_READY 0 15 #define CXLMDEV_MS_READY 1 16 #define CXLMDEV_MS_ERROR 2 17 #define CXLMDEV_MS_DISABLED 3 18 #define CXLMDEV_READY(status) \ 19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 20 CXLMDEV_MS_READY) 21 #define CXLMDEV_MBOX_IF_READY BIT(4) 22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 23 #define CXLMDEV_RESET_NEEDED_NOT 0 24 #define CXLMDEV_RESET_NEEDED_COLD 1 25 #define CXLMDEV_RESET_NEEDED_WARM 2 26 #define CXLMDEV_RESET_NEEDED_HOT 3 27 #define CXLMDEV_RESET_NEEDED_CXL 4 28 #define CXLMDEV_RESET_NEEDED(status) \ 29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 30 CXLMDEV_RESET_NEEDED_NOT) 31 32 /** 33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 34 * @dev: driver core device object 35 * @cdev: char dev core object for ioctl operations 36 * @cxlds: The device state backing this device 37 * @id: id number of this memdev instance. 38 */ 39 struct cxl_memdev { 40 struct device dev; 41 struct cdev cdev; 42 struct cxl_dev_state *cxlds; 43 int id; 44 }; 45 46 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 47 { 48 return container_of(dev, struct cxl_memdev, dev); 49 } 50 51 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 52 53 /** 54 * struct cxl_mbox_cmd - A command to be submitted to hardware. 55 * @opcode: (input) The command set and command submitted to hardware. 56 * @payload_in: (input) Pointer to the input payload. 57 * @payload_out: (output) Pointer to the output payload. Must be allocated by 58 * the caller. 59 * @size_in: (input) Number of bytes to load from @payload_in. 60 * @size_out: (input) Max number of bytes loaded into @payload_out. 61 * (output) Number of bytes generated by the device. For fixed size 62 * outputs commands this is always expected to be deterministic. For 63 * variable sized output commands, it tells the exact number of bytes 64 * written. 65 * @return_code: (output) Error code returned from hardware. 66 * 67 * This is the primary mechanism used to send commands to the hardware. 68 * All the fields except @payload_* correspond exactly to the fields described in 69 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 70 * @payload_out are written to, and read from the Command Payload Registers 71 * defined in CXL 2.0 8.2.8.4.8. 72 */ 73 struct cxl_mbox_cmd { 74 u16 opcode; 75 void *payload_in; 76 void *payload_out; 77 size_t size_in; 78 size_t size_out; 79 u16 return_code; 80 #define CXL_MBOX_SUCCESS 0 81 }; 82 83 /* 84 * CXL 2.0 - Memory capacity multiplier 85 * See Section 8.2.9.5 86 * 87 * Volatile, Persistent, and Partition capacities are specified to be in 88 * multiples of 256MB - define a multiplier to convert to/from bytes. 89 */ 90 #define CXL_CAPACITY_MULTIPLIER SZ_256M 91 92 /** 93 * struct cxl_dev_state - The driver device state 94 * 95 * cxl_dev_state represents the CXL driver/device state. It provides an 96 * interface to mailbox commands as well as some cached data about the device. 97 * Currently only memory devices are represented. 98 * 99 * @dev: The device associated with this CXL state 100 * @regs: Parsed register blocks 101 * @payload_size: Size of space for payload 102 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 103 * @lsa_size: Size of Label Storage Area 104 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 105 * @mbox_mutex: Mutex to synchronize mailbox access. 106 * @firmware_version: Firmware version for the memory device. 107 * @enabled_cmds: Hardware commands found enabled in CEL. 108 * @exclusive_cmds: Commands that are kernel-internal only 109 * @pmem_range: Active Persistent memory capacity configuration 110 * @ram_range: Active Volatile memory capacity configuration 111 * @total_bytes: sum of all possible capacities 112 * @volatile_only_bytes: hard volatile capacity 113 * @persistent_only_bytes: hard persistent capacity 114 * @partition_align_bytes: alignment size for partition-able capacity 115 * @active_volatile_bytes: sum of hard + soft volatile 116 * @active_persistent_bytes: sum of hard + soft persistent 117 * @next_volatile_bytes: volatile capacity change pending device reset 118 * @next_persistent_bytes: persistent capacity change pending device reset 119 * @mbox_send: @dev specific transport for transmitting mailbox commands 120 * 121 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 122 * details on capacity parameters. 123 */ 124 struct cxl_dev_state { 125 struct device *dev; 126 127 struct cxl_regs regs; 128 129 size_t payload_size; 130 size_t lsa_size; 131 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 132 char firmware_version[0x10]; 133 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 134 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 135 136 struct range pmem_range; 137 struct range ram_range; 138 u64 total_bytes; 139 u64 volatile_only_bytes; 140 u64 persistent_only_bytes; 141 u64 partition_align_bytes; 142 143 u64 active_volatile_bytes; 144 u64 active_persistent_bytes; 145 u64 next_volatile_bytes; 146 u64 next_persistent_bytes; 147 148 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 149 }; 150 151 enum cxl_opcode { 152 CXL_MBOX_OP_INVALID = 0x0000, 153 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 154 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 155 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 156 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 157 CXL_MBOX_OP_GET_LOG = 0x0401, 158 CXL_MBOX_OP_IDENTIFY = 0x4000, 159 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 160 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 161 CXL_MBOX_OP_GET_LSA = 0x4102, 162 CXL_MBOX_OP_SET_LSA = 0x4103, 163 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 164 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 165 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 166 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 167 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 168 CXL_MBOX_OP_GET_POISON = 0x4300, 169 CXL_MBOX_OP_INJECT_POISON = 0x4301, 170 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 171 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 172 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 173 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 174 CXL_MBOX_OP_MAX = 0x10000 175 }; 176 177 #define DEFINE_CXL_CEL_UUID \ 178 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 179 0x3b, 0x3f, 0x17) 180 181 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 182 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 183 0x40, 0x3d, 0x86) 184 185 struct cxl_mbox_get_supported_logs { 186 __le16 entries; 187 u8 rsvd[6]; 188 struct cxl_gsl_entry { 189 uuid_t uuid; 190 __le32 size; 191 } __packed entry[]; 192 } __packed; 193 194 struct cxl_cel_entry { 195 __le16 opcode; 196 __le16 effect; 197 } __packed; 198 199 struct cxl_mbox_get_log { 200 uuid_t uuid; 201 __le32 offset; 202 __le32 length; 203 } __packed; 204 205 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 206 struct cxl_mbox_identify { 207 char fw_revision[0x10]; 208 __le64 total_capacity; 209 __le64 volatile_capacity; 210 __le64 persistent_capacity; 211 __le64 partition_align; 212 __le16 info_event_log_size; 213 __le16 warning_event_log_size; 214 __le16 failure_event_log_size; 215 __le16 fatal_event_log_size; 216 __le32 lsa_size; 217 u8 poison_list_max_mer[3]; 218 __le16 inject_poison_limit; 219 u8 poison_caps; 220 u8 qos_telemetry_caps; 221 } __packed; 222 223 struct cxl_mbox_get_lsa { 224 u32 offset; 225 u32 length; 226 } __packed; 227 228 struct cxl_mbox_set_lsa { 229 u32 offset; 230 u32 reserved; 231 u8 data[]; 232 } __packed; 233 234 /** 235 * struct cxl_mem_command - Driver representation of a memory device command 236 * @info: Command information as it exists for the UAPI 237 * @opcode: The actual bits used for the mailbox protocol 238 * @flags: Set of flags effecting driver behavior. 239 * 240 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 241 * will be enabled by the driver regardless of what hardware may have 242 * advertised. 243 * 244 * The cxl_mem_command is the driver's internal representation of commands that 245 * are supported by the driver. Some of these commands may not be supported by 246 * the hardware. The driver will use @info to validate the fields passed in by 247 * the user then submit the @opcode to the hardware. 248 * 249 * See struct cxl_command_info. 250 */ 251 struct cxl_mem_command { 252 struct cxl_command_info info; 253 enum cxl_opcode opcode; 254 u32 flags; 255 #define CXL_CMD_FLAG_NONE 0 256 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 257 }; 258 259 int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in, 260 size_t in_size, void *out, size_t out_size); 261 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 262 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 263 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 264 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 265 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 266 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 267 #endif /* __CXL_MEM_H__ */ 268