1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include "cxl.h" 9 10 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 11 #define CXLMDEV_STATUS_OFFSET 0x0 12 #define CXLMDEV_DEV_FATAL BIT(0) 13 #define CXLMDEV_FW_HALT BIT(1) 14 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 15 #define CXLMDEV_MS_NOT_READY 0 16 #define CXLMDEV_MS_READY 1 17 #define CXLMDEV_MS_ERROR 2 18 #define CXLMDEV_MS_DISABLED 3 19 #define CXLMDEV_READY(status) \ 20 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 21 CXLMDEV_MS_READY) 22 #define CXLMDEV_MBOX_IF_READY BIT(4) 23 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 24 #define CXLMDEV_RESET_NEEDED_NOT 0 25 #define CXLMDEV_RESET_NEEDED_COLD 1 26 #define CXLMDEV_RESET_NEEDED_WARM 2 27 #define CXLMDEV_RESET_NEEDED_HOT 3 28 #define CXLMDEV_RESET_NEEDED_CXL 4 29 #define CXLMDEV_RESET_NEEDED(status) \ 30 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 31 CXLMDEV_RESET_NEEDED_NOT) 32 33 /** 34 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 35 * @dev: driver core device object 36 * @cdev: char dev core object for ioctl operations 37 * @cxlds: The device state backing this device 38 * @detach_work: active memdev lost a port in its ancestry 39 * @cxl_nvb: coordinate removal of @cxl_nvd if present 40 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 41 * @id: id number of this memdev instance. 42 * @depth: endpoint port depth 43 */ 44 struct cxl_memdev { 45 struct device dev; 46 struct cdev cdev; 47 struct cxl_dev_state *cxlds; 48 struct work_struct detach_work; 49 struct cxl_nvdimm_bridge *cxl_nvb; 50 struct cxl_nvdimm *cxl_nvd; 51 int id; 52 int depth; 53 }; 54 55 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 56 { 57 return container_of(dev, struct cxl_memdev, dev); 58 } 59 60 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 61 { 62 return to_cxl_port(cxled->cxld.dev.parent); 63 } 64 65 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 66 { 67 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 68 } 69 70 static inline struct cxl_memdev * 71 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 72 { 73 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 74 75 return to_cxl_memdev(port->uport); 76 } 77 78 bool is_cxl_memdev(const struct device *dev); 79 static inline bool is_cxl_endpoint(struct cxl_port *port) 80 { 81 return is_cxl_memdev(port->uport); 82 } 83 84 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 85 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 86 resource_size_t base, resource_size_t len, 87 resource_size_t skipped); 88 89 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 90 struct cxl_memdev *cxlmd) 91 { 92 if (!port) 93 return NULL; 94 95 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 96 } 97 98 /** 99 * struct cxl_mbox_cmd - A command to be submitted to hardware. 100 * @opcode: (input) The command set and command submitted to hardware. 101 * @payload_in: (input) Pointer to the input payload. 102 * @payload_out: (output) Pointer to the output payload. Must be allocated by 103 * the caller. 104 * @size_in: (input) Number of bytes to load from @payload_in. 105 * @size_out: (input) Max number of bytes loaded into @payload_out. 106 * (output) Number of bytes generated by the device. For fixed size 107 * outputs commands this is always expected to be deterministic. For 108 * variable sized output commands, it tells the exact number of bytes 109 * written. 110 * @min_out: (input) internal command output payload size validation 111 * @return_code: (output) Error code returned from hardware. 112 * 113 * This is the primary mechanism used to send commands to the hardware. 114 * All the fields except @payload_* correspond exactly to the fields described in 115 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 116 * @payload_out are written to, and read from the Command Payload Registers 117 * defined in CXL 2.0 8.2.8.4.8. 118 */ 119 struct cxl_mbox_cmd { 120 u16 opcode; 121 void *payload_in; 122 void *payload_out; 123 size_t size_in; 124 size_t size_out; 125 size_t min_out; 126 u16 return_code; 127 }; 128 129 /* 130 * Per CXL 3.0 Section 8.2.8.4.5.1 131 */ 132 #define CMD_CMD_RC_TABLE \ 133 C(SUCCESS, 0, NULL), \ 134 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 135 C(INPUT, -ENXIO, "cmd input was invalid"), \ 136 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 137 C(INTERNAL, -ENXIO, "internal device error"), \ 138 C(RETRY, -ENXIO, "temporary error, retry once"), \ 139 C(BUSY, -ENXIO, "ongoing background operation"), \ 140 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 141 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 142 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 143 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 144 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 145 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 146 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 147 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 148 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 149 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 150 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 151 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 152 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 153 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 154 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 155 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 156 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 157 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 158 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 159 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 160 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 161 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 162 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 163 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 164 165 #undef C 166 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 167 enum { CMD_CMD_RC_TABLE }; 168 #undef C 169 #define C(a, b, c) { b, c } 170 struct cxl_mbox_cmd_rc { 171 int err; 172 const char *desc; 173 }; 174 175 static const 176 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 177 #undef C 178 179 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 180 { 181 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 182 } 183 184 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 185 { 186 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 187 } 188 189 /* 190 * CXL 2.0 - Memory capacity multiplier 191 * See Section 8.2.9.5 192 * 193 * Volatile, Persistent, and Partition capacities are specified to be in 194 * multiples of 256MB - define a multiplier to convert to/from bytes. 195 */ 196 #define CXL_CAPACITY_MULTIPLIER SZ_256M 197 198 /** 199 * Event Interrupt Policy 200 * 201 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 202 */ 203 enum cxl_event_int_mode { 204 CXL_INT_NONE = 0x00, 205 CXL_INT_MSI_MSIX = 0x01, 206 CXL_INT_FW = 0x02 207 }; 208 struct cxl_event_interrupt_policy { 209 u8 info_settings; 210 u8 warn_settings; 211 u8 failure_settings; 212 u8 fatal_settings; 213 } __packed; 214 215 /** 216 * struct cxl_event_state - Event log driver state 217 * 218 * @event_buf: Buffer to receive event data 219 * @event_log_lock: Serialize event_buf and log use 220 */ 221 struct cxl_event_state { 222 struct cxl_get_event_payload *buf; 223 struct mutex log_lock; 224 }; 225 226 /* Device enabled poison commands */ 227 enum poison_cmd_enabled_bits { 228 CXL_POISON_ENABLED_LIST, 229 CXL_POISON_ENABLED_INJECT, 230 CXL_POISON_ENABLED_CLEAR, 231 CXL_POISON_ENABLED_SCAN_CAPS, 232 CXL_POISON_ENABLED_SCAN_MEDIA, 233 CXL_POISON_ENABLED_SCAN_RESULTS, 234 CXL_POISON_ENABLED_MAX 235 }; 236 237 /** 238 * struct cxl_poison_state - Driver poison state info 239 * 240 * @max_errors: Maximum media error records held in device cache 241 * @enabled_cmds: All poison commands enabled in the CEL 242 * @list_out: The poison list payload returned by device 243 * @lock: Protect reads of the poison list 244 * 245 * Reads of the poison list are synchronized to ensure that a reader 246 * does not get an incomplete list because their request overlapped 247 * (was interrupted or preceded by) another read request of the same 248 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 249 */ 250 struct cxl_poison_state { 251 u32 max_errors; 252 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 253 struct cxl_mbox_poison_out *list_out; 254 struct mutex lock; /* Protect reads of poison list */ 255 }; 256 257 /** 258 * struct cxl_dev_state - The driver device state 259 * 260 * cxl_dev_state represents the CXL driver/device state. It provides an 261 * interface to mailbox commands as well as some cached data about the device. 262 * Currently only memory devices are represented. 263 * 264 * @dev: The device associated with this CXL state 265 * @cxlmd: The device representing the CXL.mem capabilities of @dev 266 * @regs: Parsed register blocks 267 * @cxl_dvsec: Offset to the PCIe device DVSEC 268 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 269 * @media_ready: Indicate whether the device media is usable 270 * @payload_size: Size of space for payload 271 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 272 * @lsa_size: Size of Label Storage Area 273 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 274 * @mbox_mutex: Mutex to synchronize mailbox access. 275 * @firmware_version: Firmware version for the memory device. 276 * @enabled_cmds: Hardware commands found enabled in CEL. 277 * @exclusive_cmds: Commands that are kernel-internal only 278 * @dpa_res: Overall DPA resource tree for the device 279 * @pmem_res: Active Persistent memory capacity configuration 280 * @ram_res: Active Volatile memory capacity configuration 281 * @total_bytes: sum of all possible capacities 282 * @volatile_only_bytes: hard volatile capacity 283 * @persistent_only_bytes: hard persistent capacity 284 * @partition_align_bytes: alignment size for partition-able capacity 285 * @active_volatile_bytes: sum of hard + soft volatile 286 * @active_persistent_bytes: sum of hard + soft persistent 287 * @next_volatile_bytes: volatile capacity change pending device reset 288 * @next_persistent_bytes: persistent capacity change pending device reset 289 * @component_reg_phys: register base of component registers 290 * @info: Cached DVSEC information about the device. 291 * @serial: PCIe Device Serial Number 292 * @event: event log driver state 293 * @poison: poison driver state info 294 * @mbox_send: @dev specific transport for transmitting mailbox commands 295 * 296 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 297 * details on capacity parameters. 298 */ 299 struct cxl_dev_state { 300 struct device *dev; 301 struct cxl_memdev *cxlmd; 302 303 struct cxl_regs regs; 304 int cxl_dvsec; 305 306 bool rcd; 307 bool media_ready; 308 size_t payload_size; 309 size_t lsa_size; 310 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 311 char firmware_version[0x10]; 312 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 313 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 314 315 struct resource dpa_res; 316 struct resource pmem_res; 317 struct resource ram_res; 318 u64 total_bytes; 319 u64 volatile_only_bytes; 320 u64 persistent_only_bytes; 321 u64 partition_align_bytes; 322 323 u64 active_volatile_bytes; 324 u64 active_persistent_bytes; 325 u64 next_volatile_bytes; 326 u64 next_persistent_bytes; 327 328 resource_size_t component_reg_phys; 329 u64 serial; 330 331 struct cxl_event_state event; 332 struct cxl_poison_state poison; 333 334 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 335 }; 336 337 enum cxl_opcode { 338 CXL_MBOX_OP_INVALID = 0x0000, 339 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 340 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 341 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 342 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 343 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 344 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 345 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 346 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 347 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 348 CXL_MBOX_OP_GET_LOG = 0x0401, 349 CXL_MBOX_OP_IDENTIFY = 0x4000, 350 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 351 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 352 CXL_MBOX_OP_GET_LSA = 0x4102, 353 CXL_MBOX_OP_SET_LSA = 0x4103, 354 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 355 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 356 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 357 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 358 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 359 CXL_MBOX_OP_GET_POISON = 0x4300, 360 CXL_MBOX_OP_INJECT_POISON = 0x4301, 361 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 362 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 363 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 364 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 365 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 366 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 367 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 368 CXL_MBOX_OP_UNLOCK = 0x4503, 369 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 370 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 371 CXL_MBOX_OP_MAX = 0x10000 372 }; 373 374 #define DEFINE_CXL_CEL_UUID \ 375 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 376 0x3b, 0x3f, 0x17) 377 378 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 379 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 380 0x40, 0x3d, 0x86) 381 382 struct cxl_mbox_get_supported_logs { 383 __le16 entries; 384 u8 rsvd[6]; 385 struct cxl_gsl_entry { 386 uuid_t uuid; 387 __le32 size; 388 } __packed entry[]; 389 } __packed; 390 391 struct cxl_cel_entry { 392 __le16 opcode; 393 __le16 effect; 394 } __packed; 395 396 struct cxl_mbox_get_log { 397 uuid_t uuid; 398 __le32 offset; 399 __le32 length; 400 } __packed; 401 402 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 403 struct cxl_mbox_identify { 404 char fw_revision[0x10]; 405 __le64 total_capacity; 406 __le64 volatile_capacity; 407 __le64 persistent_capacity; 408 __le64 partition_align; 409 __le16 info_event_log_size; 410 __le16 warning_event_log_size; 411 __le16 failure_event_log_size; 412 __le16 fatal_event_log_size; 413 __le32 lsa_size; 414 u8 poison_list_max_mer[3]; 415 __le16 inject_poison_limit; 416 u8 poison_caps; 417 u8 qos_telemetry_caps; 418 } __packed; 419 420 /* 421 * Common Event Record Format 422 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 423 */ 424 struct cxl_event_record_hdr { 425 uuid_t id; 426 u8 length; 427 u8 flags[3]; 428 __le16 handle; 429 __le16 related_handle; 430 __le64 timestamp; 431 u8 maint_op_class; 432 u8 reserved[15]; 433 } __packed; 434 435 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 436 struct cxl_event_record_raw { 437 struct cxl_event_record_hdr hdr; 438 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 439 } __packed; 440 441 /* 442 * Get Event Records output payload 443 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 444 */ 445 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 446 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 447 struct cxl_get_event_payload { 448 u8 flags; 449 u8 reserved1; 450 __le16 overflow_err_count; 451 __le64 first_overflow_timestamp; 452 __le64 last_overflow_timestamp; 453 __le16 record_count; 454 u8 reserved2[10]; 455 struct cxl_event_record_raw records[]; 456 } __packed; 457 458 /* 459 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 460 */ 461 enum cxl_event_log_type { 462 CXL_EVENT_TYPE_INFO = 0x00, 463 CXL_EVENT_TYPE_WARN, 464 CXL_EVENT_TYPE_FAIL, 465 CXL_EVENT_TYPE_FATAL, 466 CXL_EVENT_TYPE_MAX 467 }; 468 469 /* 470 * Clear Event Records input payload 471 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 472 */ 473 struct cxl_mbox_clear_event_payload { 474 u8 event_log; /* enum cxl_event_log_type */ 475 u8 clear_flags; 476 u8 nr_recs; 477 u8 reserved[3]; 478 __le16 handles[]; 479 } __packed; 480 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 481 482 /* 483 * General Media Event Record 484 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 485 */ 486 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 487 struct cxl_event_gen_media { 488 struct cxl_event_record_hdr hdr; 489 __le64 phys_addr; 490 u8 descriptor; 491 u8 type; 492 u8 transaction_type; 493 u8 validity_flags[2]; 494 u8 channel; 495 u8 rank; 496 u8 device[3]; 497 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 498 u8 reserved[46]; 499 } __packed; 500 501 /* 502 * DRAM Event Record - DER 503 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 504 */ 505 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 506 struct cxl_event_dram { 507 struct cxl_event_record_hdr hdr; 508 __le64 phys_addr; 509 u8 descriptor; 510 u8 type; 511 u8 transaction_type; 512 u8 validity_flags[2]; 513 u8 channel; 514 u8 rank; 515 u8 nibble_mask[3]; 516 u8 bank_group; 517 u8 bank; 518 u8 row[3]; 519 u8 column[2]; 520 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 521 u8 reserved[0x17]; 522 } __packed; 523 524 /* 525 * Get Health Info Record 526 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 527 */ 528 struct cxl_get_health_info { 529 u8 health_status; 530 u8 media_status; 531 u8 add_status; 532 u8 life_used; 533 u8 device_temp[2]; 534 u8 dirty_shutdown_cnt[4]; 535 u8 cor_vol_err_cnt[4]; 536 u8 cor_per_err_cnt[4]; 537 } __packed; 538 539 /* 540 * Memory Module Event Record 541 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 542 */ 543 struct cxl_event_mem_module { 544 struct cxl_event_record_hdr hdr; 545 u8 event_type; 546 struct cxl_get_health_info info; 547 u8 reserved[0x3d]; 548 } __packed; 549 550 struct cxl_mbox_get_partition_info { 551 __le64 active_volatile_cap; 552 __le64 active_persistent_cap; 553 __le64 next_volatile_cap; 554 __le64 next_persistent_cap; 555 } __packed; 556 557 struct cxl_mbox_get_lsa { 558 __le32 offset; 559 __le32 length; 560 } __packed; 561 562 struct cxl_mbox_set_lsa { 563 __le32 offset; 564 __le32 reserved; 565 u8 data[]; 566 } __packed; 567 568 struct cxl_mbox_set_partition_info { 569 __le64 volatile_capacity; 570 u8 flags; 571 } __packed; 572 573 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 574 575 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 576 struct cxl_mbox_set_timestamp_in { 577 __le64 timestamp; 578 579 } __packed; 580 581 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 582 struct cxl_mbox_poison_in { 583 __le64 offset; 584 __le64 length; 585 } __packed; 586 587 struct cxl_mbox_poison_out { 588 u8 flags; 589 u8 rsvd1; 590 __le64 overflow_ts; 591 __le16 count; 592 u8 rsvd2[20]; 593 struct cxl_poison_record { 594 __le64 address; 595 __le32 length; 596 __le32 rsvd; 597 } __packed record[]; 598 } __packed; 599 600 /* 601 * Get Poison List address field encodes the starting 602 * address of poison, and the source of the poison. 603 */ 604 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 605 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 606 607 /* Get Poison List record length is in units of 64 bytes */ 608 #define CXL_POISON_LEN_MULT 64 609 610 /* Kernel defined maximum for a list of poison errors */ 611 #define CXL_POISON_LIST_MAX 1024 612 613 /* Get Poison List: Payload out flags */ 614 #define CXL_POISON_FLAG_MORE BIT(0) 615 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 616 #define CXL_POISON_FLAG_SCANNING BIT(2) 617 618 /* Get Poison List: Poison Source */ 619 #define CXL_POISON_SOURCE_UNKNOWN 0 620 #define CXL_POISON_SOURCE_EXTERNAL 1 621 #define CXL_POISON_SOURCE_INTERNAL 2 622 #define CXL_POISON_SOURCE_INJECTED 3 623 #define CXL_POISON_SOURCE_VENDOR 7 624 625 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 626 struct cxl_mbox_inject_poison { 627 __le64 address; 628 }; 629 630 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 631 struct cxl_mbox_clear_poison { 632 __le64 address; 633 u8 write_data[CXL_POISON_LEN_MULT]; 634 } __packed; 635 636 /** 637 * struct cxl_mem_command - Driver representation of a memory device command 638 * @info: Command information as it exists for the UAPI 639 * @opcode: The actual bits used for the mailbox protocol 640 * @flags: Set of flags effecting driver behavior. 641 * 642 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 643 * will be enabled by the driver regardless of what hardware may have 644 * advertised. 645 * 646 * The cxl_mem_command is the driver's internal representation of commands that 647 * are supported by the driver. Some of these commands may not be supported by 648 * the hardware. The driver will use @info to validate the fields passed in by 649 * the user then submit the @opcode to the hardware. 650 * 651 * See struct cxl_command_info. 652 */ 653 struct cxl_mem_command { 654 struct cxl_command_info info; 655 enum cxl_opcode opcode; 656 u32 flags; 657 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 658 }; 659 660 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 661 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 662 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 663 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 664 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 665 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 666 667 /* set passphrase input payload */ 668 struct cxl_set_pass { 669 u8 type; 670 u8 reserved[31]; 671 /* CXL field using NVDIMM define, same length */ 672 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 673 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 674 } __packed; 675 676 /* disable passphrase input payload */ 677 struct cxl_disable_pass { 678 u8 type; 679 u8 reserved[31]; 680 u8 pass[NVDIMM_PASSPHRASE_LEN]; 681 } __packed; 682 683 /* passphrase secure erase payload */ 684 struct cxl_pass_erase { 685 u8 type; 686 u8 reserved[31]; 687 u8 pass[NVDIMM_PASSPHRASE_LEN]; 688 } __packed; 689 690 enum { 691 CXL_PMEM_SEC_PASS_MASTER = 0, 692 CXL_PMEM_SEC_PASS_USER, 693 }; 694 695 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds, 696 struct cxl_mbox_cmd *cmd); 697 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 698 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 699 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 700 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 701 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 702 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 703 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 704 void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status); 705 int cxl_set_timestamp(struct cxl_dev_state *cxlds); 706 int cxl_poison_state_init(struct cxl_dev_state *cxlds); 707 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 708 struct cxl_region *cxlr); 709 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 710 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 711 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 712 713 #ifdef CONFIG_CXL_SUSPEND 714 void cxl_mem_active_inc(void); 715 void cxl_mem_active_dec(void); 716 #else 717 static inline void cxl_mem_active_inc(void) 718 { 719 } 720 static inline void cxl_mem_active_dec(void) 721 { 722 } 723 #endif 724 725 struct cxl_hdm { 726 struct cxl_component_regs regs; 727 unsigned int decoder_count; 728 unsigned int target_count; 729 unsigned int interleave_mask; 730 struct cxl_port *port; 731 }; 732 733 struct seq_file; 734 struct dentry *cxl_debugfs_create_dir(const char *dir); 735 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 736 #endif /* __CXL_MEM_H__ */ 737