1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include "cxl.h" 9 10 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 11 #define CXLMDEV_STATUS_OFFSET 0x0 12 #define CXLMDEV_DEV_FATAL BIT(0) 13 #define CXLMDEV_FW_HALT BIT(1) 14 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 15 #define CXLMDEV_MS_NOT_READY 0 16 #define CXLMDEV_MS_READY 1 17 #define CXLMDEV_MS_ERROR 2 18 #define CXLMDEV_MS_DISABLED 3 19 #define CXLMDEV_READY(status) \ 20 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 21 CXLMDEV_MS_READY) 22 #define CXLMDEV_MBOX_IF_READY BIT(4) 23 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 24 #define CXLMDEV_RESET_NEEDED_NOT 0 25 #define CXLMDEV_RESET_NEEDED_COLD 1 26 #define CXLMDEV_RESET_NEEDED_WARM 2 27 #define CXLMDEV_RESET_NEEDED_HOT 3 28 #define CXLMDEV_RESET_NEEDED_CXL 4 29 #define CXLMDEV_RESET_NEEDED(status) \ 30 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 31 CXLMDEV_RESET_NEEDED_NOT) 32 33 /** 34 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 35 * @dev: driver core device object 36 * @cdev: char dev core object for ioctl operations 37 * @cxlds: The device state backing this device 38 * @detach_work: active memdev lost a port in its ancestry 39 * @cxl_nvb: coordinate removal of @cxl_nvd if present 40 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 41 * @id: id number of this memdev instance. 42 * @depth: endpoint port depth 43 */ 44 struct cxl_memdev { 45 struct device dev; 46 struct cdev cdev; 47 struct cxl_dev_state *cxlds; 48 struct work_struct detach_work; 49 struct cxl_nvdimm_bridge *cxl_nvb; 50 struct cxl_nvdimm *cxl_nvd; 51 int id; 52 int depth; 53 }; 54 55 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 56 { 57 return container_of(dev, struct cxl_memdev, dev); 58 } 59 60 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 61 { 62 return to_cxl_port(cxled->cxld.dev.parent); 63 } 64 65 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 66 { 67 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 68 } 69 70 static inline struct cxl_memdev * 71 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 72 { 73 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 74 75 return to_cxl_memdev(port->uport); 76 } 77 78 bool is_cxl_memdev(const struct device *dev); 79 static inline bool is_cxl_endpoint(struct cxl_port *port) 80 { 81 return is_cxl_memdev(port->uport); 82 } 83 84 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 85 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 86 resource_size_t base, resource_size_t len, 87 resource_size_t skipped); 88 89 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 90 struct cxl_memdev *cxlmd) 91 { 92 if (!port) 93 return NULL; 94 95 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 96 } 97 98 /** 99 * struct cxl_mbox_cmd - A command to be submitted to hardware. 100 * @opcode: (input) The command set and command submitted to hardware. 101 * @payload_in: (input) Pointer to the input payload. 102 * @payload_out: (output) Pointer to the output payload. Must be allocated by 103 * the caller. 104 * @size_in: (input) Number of bytes to load from @payload_in. 105 * @size_out: (input) Max number of bytes loaded into @payload_out. 106 * (output) Number of bytes generated by the device. For fixed size 107 * outputs commands this is always expected to be deterministic. For 108 * variable sized output commands, it tells the exact number of bytes 109 * written. 110 * @min_out: (input) internal command output payload size validation 111 * @return_code: (output) Error code returned from hardware. 112 * 113 * This is the primary mechanism used to send commands to the hardware. 114 * All the fields except @payload_* correspond exactly to the fields described in 115 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 116 * @payload_out are written to, and read from the Command Payload Registers 117 * defined in CXL 2.0 8.2.8.4.8. 118 */ 119 struct cxl_mbox_cmd { 120 u16 opcode; 121 void *payload_in; 122 void *payload_out; 123 size_t size_in; 124 size_t size_out; 125 size_t min_out; 126 u16 return_code; 127 }; 128 129 /* 130 * Per CXL 2.0 Section 8.2.8.4.5.1 131 */ 132 #define CMD_CMD_RC_TABLE \ 133 C(SUCCESS, 0, NULL), \ 134 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 135 C(INPUT, -ENXIO, "cmd input was invalid"), \ 136 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 137 C(INTERNAL, -ENXIO, "internal device error"), \ 138 C(RETRY, -ENXIO, "temporary error, retry once"), \ 139 C(BUSY, -ENXIO, "ongoing background operation"), \ 140 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 141 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 142 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 143 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 144 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 145 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 146 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 147 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 148 C(PADDR, -ENXIO, "physical address specified is invalid"), \ 149 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 150 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 151 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 152 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 153 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 154 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 155 C(PAYLOADLEN, -ENXIO, "invalid payload length") 156 157 #undef C 158 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 159 enum { CMD_CMD_RC_TABLE }; 160 #undef C 161 #define C(a, b, c) { b, c } 162 struct cxl_mbox_cmd_rc { 163 int err; 164 const char *desc; 165 }; 166 167 static const 168 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 169 #undef C 170 171 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 172 { 173 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 174 } 175 176 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 177 { 178 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 179 } 180 181 /* 182 * CXL 2.0 - Memory capacity multiplier 183 * See Section 8.2.9.5 184 * 185 * Volatile, Persistent, and Partition capacities are specified to be in 186 * multiples of 256MB - define a multiplier to convert to/from bytes. 187 */ 188 #define CXL_CAPACITY_MULTIPLIER SZ_256M 189 190 /** 191 * Event Interrupt Policy 192 * 193 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 194 */ 195 enum cxl_event_int_mode { 196 CXL_INT_NONE = 0x00, 197 CXL_INT_MSI_MSIX = 0x01, 198 CXL_INT_FW = 0x02 199 }; 200 struct cxl_event_interrupt_policy { 201 u8 info_settings; 202 u8 warn_settings; 203 u8 failure_settings; 204 u8 fatal_settings; 205 } __packed; 206 207 /** 208 * struct cxl_event_state - Event log driver state 209 * 210 * @event_buf: Buffer to receive event data 211 * @event_log_lock: Serialize event_buf and log use 212 */ 213 struct cxl_event_state { 214 struct cxl_get_event_payload *buf; 215 struct mutex log_lock; 216 }; 217 218 /** 219 * struct cxl_dev_state - The driver device state 220 * 221 * cxl_dev_state represents the CXL driver/device state. It provides an 222 * interface to mailbox commands as well as some cached data about the device. 223 * Currently only memory devices are represented. 224 * 225 * @dev: The device associated with this CXL state 226 * @cxlmd: The device representing the CXL.mem capabilities of @dev 227 * @regs: Parsed register blocks 228 * @cxl_dvsec: Offset to the PCIe device DVSEC 229 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 230 * @payload_size: Size of space for payload 231 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 232 * @lsa_size: Size of Label Storage Area 233 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 234 * @mbox_mutex: Mutex to synchronize mailbox access. 235 * @firmware_version: Firmware version for the memory device. 236 * @enabled_cmds: Hardware commands found enabled in CEL. 237 * @exclusive_cmds: Commands that are kernel-internal only 238 * @dpa_res: Overall DPA resource tree for the device 239 * @pmem_res: Active Persistent memory capacity configuration 240 * @ram_res: Active Volatile memory capacity configuration 241 * @total_bytes: sum of all possible capacities 242 * @volatile_only_bytes: hard volatile capacity 243 * @persistent_only_bytes: hard persistent capacity 244 * @partition_align_bytes: alignment size for partition-able capacity 245 * @active_volatile_bytes: sum of hard + soft volatile 246 * @active_persistent_bytes: sum of hard + soft persistent 247 * @next_volatile_bytes: volatile capacity change pending device reset 248 * @next_persistent_bytes: persistent capacity change pending device reset 249 * @component_reg_phys: register base of component registers 250 * @info: Cached DVSEC information about the device. 251 * @serial: PCIe Device Serial Number 252 * @doe_mbs: PCI DOE mailbox array 253 * @event: event log driver state 254 * @mbox_send: @dev specific transport for transmitting mailbox commands 255 * 256 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 257 * details on capacity parameters. 258 */ 259 struct cxl_dev_state { 260 struct device *dev; 261 struct cxl_memdev *cxlmd; 262 263 struct cxl_regs regs; 264 int cxl_dvsec; 265 266 bool rcd; 267 size_t payload_size; 268 size_t lsa_size; 269 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 270 char firmware_version[0x10]; 271 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 272 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 273 274 struct resource dpa_res; 275 struct resource pmem_res; 276 struct resource ram_res; 277 u64 total_bytes; 278 u64 volatile_only_bytes; 279 u64 persistent_only_bytes; 280 u64 partition_align_bytes; 281 282 u64 active_volatile_bytes; 283 u64 active_persistent_bytes; 284 u64 next_volatile_bytes; 285 u64 next_persistent_bytes; 286 287 resource_size_t component_reg_phys; 288 u64 serial; 289 290 struct xarray doe_mbs; 291 292 struct cxl_event_state event; 293 294 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 295 }; 296 297 enum cxl_opcode { 298 CXL_MBOX_OP_INVALID = 0x0000, 299 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 300 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 301 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 302 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 303 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 304 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 305 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 306 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 307 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 308 CXL_MBOX_OP_GET_LOG = 0x0401, 309 CXL_MBOX_OP_IDENTIFY = 0x4000, 310 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 311 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 312 CXL_MBOX_OP_GET_LSA = 0x4102, 313 CXL_MBOX_OP_SET_LSA = 0x4103, 314 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 315 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 316 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 317 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 318 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 319 CXL_MBOX_OP_GET_POISON = 0x4300, 320 CXL_MBOX_OP_INJECT_POISON = 0x4301, 321 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 322 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 323 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 324 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 325 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 326 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 327 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 328 CXL_MBOX_OP_UNLOCK = 0x4503, 329 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 330 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 331 CXL_MBOX_OP_MAX = 0x10000 332 }; 333 334 #define DEFINE_CXL_CEL_UUID \ 335 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 336 0x3b, 0x3f, 0x17) 337 338 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 339 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 340 0x40, 0x3d, 0x86) 341 342 struct cxl_mbox_get_supported_logs { 343 __le16 entries; 344 u8 rsvd[6]; 345 struct cxl_gsl_entry { 346 uuid_t uuid; 347 __le32 size; 348 } __packed entry[]; 349 } __packed; 350 351 struct cxl_cel_entry { 352 __le16 opcode; 353 __le16 effect; 354 } __packed; 355 356 struct cxl_mbox_get_log { 357 uuid_t uuid; 358 __le32 offset; 359 __le32 length; 360 } __packed; 361 362 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 363 struct cxl_mbox_identify { 364 char fw_revision[0x10]; 365 __le64 total_capacity; 366 __le64 volatile_capacity; 367 __le64 persistent_capacity; 368 __le64 partition_align; 369 __le16 info_event_log_size; 370 __le16 warning_event_log_size; 371 __le16 failure_event_log_size; 372 __le16 fatal_event_log_size; 373 __le32 lsa_size; 374 u8 poison_list_max_mer[3]; 375 __le16 inject_poison_limit; 376 u8 poison_caps; 377 u8 qos_telemetry_caps; 378 } __packed; 379 380 /* 381 * Common Event Record Format 382 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 383 */ 384 struct cxl_event_record_hdr { 385 uuid_t id; 386 u8 length; 387 u8 flags[3]; 388 __le16 handle; 389 __le16 related_handle; 390 __le64 timestamp; 391 u8 maint_op_class; 392 u8 reserved[15]; 393 } __packed; 394 395 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 396 struct cxl_event_record_raw { 397 struct cxl_event_record_hdr hdr; 398 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 399 } __packed; 400 401 /* 402 * Get Event Records output payload 403 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 404 */ 405 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 406 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 407 struct cxl_get_event_payload { 408 u8 flags; 409 u8 reserved1; 410 __le16 overflow_err_count; 411 __le64 first_overflow_timestamp; 412 __le64 last_overflow_timestamp; 413 __le16 record_count; 414 u8 reserved2[10]; 415 struct cxl_event_record_raw records[]; 416 } __packed; 417 418 /* 419 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 420 */ 421 enum cxl_event_log_type { 422 CXL_EVENT_TYPE_INFO = 0x00, 423 CXL_EVENT_TYPE_WARN, 424 CXL_EVENT_TYPE_FAIL, 425 CXL_EVENT_TYPE_FATAL, 426 CXL_EVENT_TYPE_MAX 427 }; 428 429 /* 430 * Clear Event Records input payload 431 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 432 */ 433 struct cxl_mbox_clear_event_payload { 434 u8 event_log; /* enum cxl_event_log_type */ 435 u8 clear_flags; 436 u8 nr_recs; 437 u8 reserved[3]; 438 __le16 handles[]; 439 } __packed; 440 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 441 442 /* 443 * General Media Event Record 444 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 445 */ 446 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 447 struct cxl_event_gen_media { 448 struct cxl_event_record_hdr hdr; 449 __le64 phys_addr; 450 u8 descriptor; 451 u8 type; 452 u8 transaction_type; 453 u8 validity_flags[2]; 454 u8 channel; 455 u8 rank; 456 u8 device[3]; 457 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 458 u8 reserved[46]; 459 } __packed; 460 461 /* 462 * DRAM Event Record - DER 463 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 464 */ 465 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 466 struct cxl_event_dram { 467 struct cxl_event_record_hdr hdr; 468 __le64 phys_addr; 469 u8 descriptor; 470 u8 type; 471 u8 transaction_type; 472 u8 validity_flags[2]; 473 u8 channel; 474 u8 rank; 475 u8 nibble_mask[3]; 476 u8 bank_group; 477 u8 bank; 478 u8 row[3]; 479 u8 column[2]; 480 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 481 u8 reserved[0x17]; 482 } __packed; 483 484 /* 485 * Get Health Info Record 486 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 487 */ 488 struct cxl_get_health_info { 489 u8 health_status; 490 u8 media_status; 491 u8 add_status; 492 u8 life_used; 493 u8 device_temp[2]; 494 u8 dirty_shutdown_cnt[4]; 495 u8 cor_vol_err_cnt[4]; 496 u8 cor_per_err_cnt[4]; 497 } __packed; 498 499 /* 500 * Memory Module Event Record 501 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 502 */ 503 struct cxl_event_mem_module { 504 struct cxl_event_record_hdr hdr; 505 u8 event_type; 506 struct cxl_get_health_info info; 507 u8 reserved[0x3d]; 508 } __packed; 509 510 struct cxl_mbox_get_partition_info { 511 __le64 active_volatile_cap; 512 __le64 active_persistent_cap; 513 __le64 next_volatile_cap; 514 __le64 next_persistent_cap; 515 } __packed; 516 517 struct cxl_mbox_get_lsa { 518 __le32 offset; 519 __le32 length; 520 } __packed; 521 522 struct cxl_mbox_set_lsa { 523 __le32 offset; 524 __le32 reserved; 525 u8 data[]; 526 } __packed; 527 528 struct cxl_mbox_set_partition_info { 529 __le64 volatile_capacity; 530 u8 flags; 531 } __packed; 532 533 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 534 535 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 536 struct cxl_mbox_set_timestamp_in { 537 __le64 timestamp; 538 539 } __packed; 540 541 /** 542 * struct cxl_mem_command - Driver representation of a memory device command 543 * @info: Command information as it exists for the UAPI 544 * @opcode: The actual bits used for the mailbox protocol 545 * @flags: Set of flags effecting driver behavior. 546 * 547 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 548 * will be enabled by the driver regardless of what hardware may have 549 * advertised. 550 * 551 * The cxl_mem_command is the driver's internal representation of commands that 552 * are supported by the driver. Some of these commands may not be supported by 553 * the hardware. The driver will use @info to validate the fields passed in by 554 * the user then submit the @opcode to the hardware. 555 * 556 * See struct cxl_command_info. 557 */ 558 struct cxl_mem_command { 559 struct cxl_command_info info; 560 enum cxl_opcode opcode; 561 u32 flags; 562 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 563 }; 564 565 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 566 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 567 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 568 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 569 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 570 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 571 572 /* set passphrase input payload */ 573 struct cxl_set_pass { 574 u8 type; 575 u8 reserved[31]; 576 /* CXL field using NVDIMM define, same length */ 577 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 578 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 579 } __packed; 580 581 /* disable passphrase input payload */ 582 struct cxl_disable_pass { 583 u8 type; 584 u8 reserved[31]; 585 u8 pass[NVDIMM_PASSPHRASE_LEN]; 586 } __packed; 587 588 /* passphrase secure erase payload */ 589 struct cxl_pass_erase { 590 u8 type; 591 u8 reserved[31]; 592 u8 pass[NVDIMM_PASSPHRASE_LEN]; 593 } __packed; 594 595 enum { 596 CXL_PMEM_SEC_PASS_MASTER = 0, 597 CXL_PMEM_SEC_PASS_USER, 598 }; 599 600 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds, 601 struct cxl_mbox_cmd *cmd); 602 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 603 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 604 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 605 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 606 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 607 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 608 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 609 void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status); 610 int cxl_set_timestamp(struct cxl_dev_state *cxlds); 611 612 #ifdef CONFIG_CXL_SUSPEND 613 void cxl_mem_active_inc(void); 614 void cxl_mem_active_dec(void); 615 #else 616 static inline void cxl_mem_active_inc(void) 617 { 618 } 619 static inline void cxl_mem_active_dec(void) 620 { 621 } 622 #endif 623 624 struct cxl_hdm { 625 struct cxl_component_regs regs; 626 unsigned int decoder_count; 627 unsigned int target_count; 628 unsigned int interleave_mask; 629 struct cxl_port *port; 630 }; 631 632 struct seq_file; 633 struct dentry *cxl_debugfs_create_dir(const char *dir); 634 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 635 #endif /* __CXL_MEM_H__ */ 636