1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include <linux/rcuwait.h> 9 #include "cxl.h" 10 11 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 12 #define CXLMDEV_STATUS_OFFSET 0x0 13 #define CXLMDEV_DEV_FATAL BIT(0) 14 #define CXLMDEV_FW_HALT BIT(1) 15 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 16 #define CXLMDEV_MS_NOT_READY 0 17 #define CXLMDEV_MS_READY 1 18 #define CXLMDEV_MS_ERROR 2 19 #define CXLMDEV_MS_DISABLED 3 20 #define CXLMDEV_READY(status) \ 21 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 22 CXLMDEV_MS_READY) 23 #define CXLMDEV_MBOX_IF_READY BIT(4) 24 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 25 #define CXLMDEV_RESET_NEEDED_NOT 0 26 #define CXLMDEV_RESET_NEEDED_COLD 1 27 #define CXLMDEV_RESET_NEEDED_WARM 2 28 #define CXLMDEV_RESET_NEEDED_HOT 3 29 #define CXLMDEV_RESET_NEEDED_CXL 4 30 #define CXLMDEV_RESET_NEEDED(status) \ 31 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 32 CXLMDEV_RESET_NEEDED_NOT) 33 34 /** 35 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 36 * @dev: driver core device object 37 * @cdev: char dev core object for ioctl operations 38 * @cxlds: The device state backing this device 39 * @detach_work: active memdev lost a port in its ancestry 40 * @cxl_nvb: coordinate removal of @cxl_nvd if present 41 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 42 * @endpoint: connection to the CXL port topology for this memory device 43 * @id: id number of this memdev instance. 44 * @depth: endpoint port depth 45 */ 46 struct cxl_memdev { 47 struct device dev; 48 struct cdev cdev; 49 struct cxl_dev_state *cxlds; 50 struct work_struct detach_work; 51 struct cxl_nvdimm_bridge *cxl_nvb; 52 struct cxl_nvdimm *cxl_nvd; 53 struct cxl_port *endpoint; 54 int id; 55 int depth; 56 }; 57 58 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 59 { 60 return container_of(dev, struct cxl_memdev, dev); 61 } 62 63 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 64 { 65 return to_cxl_port(cxled->cxld.dev.parent); 66 } 67 68 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 69 { 70 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 71 } 72 73 static inline struct cxl_memdev * 74 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 75 { 76 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 77 78 return to_cxl_memdev(port->uport_dev); 79 } 80 81 bool is_cxl_memdev(const struct device *dev); 82 static inline bool is_cxl_endpoint(struct cxl_port *port) 83 { 84 return is_cxl_memdev(port->uport_dev); 85 } 86 87 struct cxl_memdev *devm_cxl_add_memdev(struct device *host, 88 struct cxl_dev_state *cxlds); 89 int devm_cxl_sanitize_setup_notifier(struct device *host, 90 struct cxl_memdev *cxlmd); 91 struct cxl_memdev_state; 92 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 93 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 94 resource_size_t base, resource_size_t len, 95 resource_size_t skipped); 96 97 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 98 struct cxl_memdev *cxlmd) 99 { 100 if (!port) 101 return NULL; 102 103 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 104 } 105 106 /** 107 * struct cxl_mbox_cmd - A command to be submitted to hardware. 108 * @opcode: (input) The command set and command submitted to hardware. 109 * @payload_in: (input) Pointer to the input payload. 110 * @payload_out: (output) Pointer to the output payload. Must be allocated by 111 * the caller. 112 * @size_in: (input) Number of bytes to load from @payload_in. 113 * @size_out: (input) Max number of bytes loaded into @payload_out. 114 * (output) Number of bytes generated by the device. For fixed size 115 * outputs commands this is always expected to be deterministic. For 116 * variable sized output commands, it tells the exact number of bytes 117 * written. 118 * @min_out: (input) internal command output payload size validation 119 * @poll_count: (input) Number of timeouts to attempt. 120 * @poll_interval_ms: (input) Time between mailbox background command polling 121 * interval timeouts. 122 * @return_code: (output) Error code returned from hardware. 123 * 124 * This is the primary mechanism used to send commands to the hardware. 125 * All the fields except @payload_* correspond exactly to the fields described in 126 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 127 * @payload_out are written to, and read from the Command Payload Registers 128 * defined in CXL 2.0 8.2.8.4.8. 129 */ 130 struct cxl_mbox_cmd { 131 u16 opcode; 132 void *payload_in; 133 void *payload_out; 134 size_t size_in; 135 size_t size_out; 136 size_t min_out; 137 int poll_count; 138 int poll_interval_ms; 139 u16 return_code; 140 }; 141 142 /* 143 * Per CXL 3.0 Section 8.2.8.4.5.1 144 */ 145 #define CMD_CMD_RC_TABLE \ 146 C(SUCCESS, 0, NULL), \ 147 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 148 C(INPUT, -ENXIO, "cmd input was invalid"), \ 149 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 150 C(INTERNAL, -ENXIO, "internal device error"), \ 151 C(RETRY, -ENXIO, "temporary error, retry once"), \ 152 C(BUSY, -ENXIO, "ongoing background operation"), \ 153 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 154 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 155 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 156 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 157 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 158 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 159 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 160 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 161 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 162 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 163 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 164 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 165 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 166 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 167 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 168 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 169 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 170 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 171 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 172 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 173 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 174 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 175 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 176 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 177 178 #undef C 179 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 180 enum { CMD_CMD_RC_TABLE }; 181 #undef C 182 #define C(a, b, c) { b, c } 183 struct cxl_mbox_cmd_rc { 184 int err; 185 const char *desc; 186 }; 187 188 static const 189 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 190 #undef C 191 192 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 193 { 194 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 195 } 196 197 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 198 { 199 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 200 } 201 202 /* 203 * CXL 2.0 - Memory capacity multiplier 204 * See Section 8.2.9.5 205 * 206 * Volatile, Persistent, and Partition capacities are specified to be in 207 * multiples of 256MB - define a multiplier to convert to/from bytes. 208 */ 209 #define CXL_CAPACITY_MULTIPLIER SZ_256M 210 211 /* 212 * Event Interrupt Policy 213 * 214 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 215 */ 216 enum cxl_event_int_mode { 217 CXL_INT_NONE = 0x00, 218 CXL_INT_MSI_MSIX = 0x01, 219 CXL_INT_FW = 0x02 220 }; 221 struct cxl_event_interrupt_policy { 222 u8 info_settings; 223 u8 warn_settings; 224 u8 failure_settings; 225 u8 fatal_settings; 226 } __packed; 227 228 /** 229 * struct cxl_event_state - Event log driver state 230 * 231 * @buf: Buffer to receive event data 232 * @log_lock: Serialize event_buf and log use 233 */ 234 struct cxl_event_state { 235 struct cxl_get_event_payload *buf; 236 struct mutex log_lock; 237 }; 238 239 /* Device enabled poison commands */ 240 enum poison_cmd_enabled_bits { 241 CXL_POISON_ENABLED_LIST, 242 CXL_POISON_ENABLED_INJECT, 243 CXL_POISON_ENABLED_CLEAR, 244 CXL_POISON_ENABLED_SCAN_CAPS, 245 CXL_POISON_ENABLED_SCAN_MEDIA, 246 CXL_POISON_ENABLED_SCAN_RESULTS, 247 CXL_POISON_ENABLED_MAX 248 }; 249 250 /* Device enabled security commands */ 251 enum security_cmd_enabled_bits { 252 CXL_SEC_ENABLED_SANITIZE, 253 CXL_SEC_ENABLED_SECURE_ERASE, 254 CXL_SEC_ENABLED_GET_SECURITY_STATE, 255 CXL_SEC_ENABLED_SET_PASSPHRASE, 256 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 257 CXL_SEC_ENABLED_UNLOCK, 258 CXL_SEC_ENABLED_FREEZE_SECURITY, 259 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 260 CXL_SEC_ENABLED_MAX 261 }; 262 263 /** 264 * struct cxl_poison_state - Driver poison state info 265 * 266 * @max_errors: Maximum media error records held in device cache 267 * @enabled_cmds: All poison commands enabled in the CEL 268 * @list_out: The poison list payload returned by device 269 * @lock: Protect reads of the poison list 270 * 271 * Reads of the poison list are synchronized to ensure that a reader 272 * does not get an incomplete list because their request overlapped 273 * (was interrupted or preceded by) another read request of the same 274 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 275 */ 276 struct cxl_poison_state { 277 u32 max_errors; 278 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 279 struct cxl_mbox_poison_out *list_out; 280 struct mutex lock; /* Protect reads of poison list */ 281 }; 282 283 /* 284 * Get FW Info 285 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 286 */ 287 struct cxl_mbox_get_fw_info { 288 u8 num_slots; 289 u8 slot_info; 290 u8 activation_cap; 291 u8 reserved[13]; 292 char slot_1_revision[16]; 293 char slot_2_revision[16]; 294 char slot_3_revision[16]; 295 char slot_4_revision[16]; 296 } __packed; 297 298 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 299 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 300 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 301 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 302 303 /* 304 * Transfer FW Input Payload 305 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 306 */ 307 struct cxl_mbox_transfer_fw { 308 u8 action; 309 u8 slot; 310 u8 reserved[2]; 311 __le32 offset; 312 u8 reserved2[0x78]; 313 u8 data[]; 314 } __packed; 315 316 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 317 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 318 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 319 #define CXL_FW_TRANSFER_ACTION_END 0x3 320 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 321 322 /* 323 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 324 * and for each part transferred in a Transfer FW command. 325 */ 326 #define CXL_FW_TRANSFER_ALIGNMENT 128 327 328 /* 329 * Activate FW Input Payload 330 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 331 */ 332 struct cxl_mbox_activate_fw { 333 u8 action; 334 u8 slot; 335 } __packed; 336 337 #define CXL_FW_ACTIVATE_ONLINE 0x0 338 #define CXL_FW_ACTIVATE_OFFLINE 0x1 339 340 /* FW state bits */ 341 #define CXL_FW_STATE_BITS 32 342 #define CXL_FW_CANCEL 0 343 344 /** 345 * struct cxl_fw_state - Firmware upload / activation state 346 * 347 * @state: fw_uploader state bitmask 348 * @oneshot: whether the fw upload fits in a single transfer 349 * @num_slots: Number of FW slots available 350 * @cur_slot: Slot number currently active 351 * @next_slot: Slot number for the new firmware 352 */ 353 struct cxl_fw_state { 354 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 355 bool oneshot; 356 int num_slots; 357 int cur_slot; 358 int next_slot; 359 }; 360 361 /** 362 * struct cxl_security_state - Device security state 363 * 364 * @state: state of last security operation 365 * @enabled_cmds: All security commands enabled in the CEL 366 * @poll_tmo_secs: polling timeout 367 * @sanitize_active: sanitize completion pending 368 * @poll_dwork: polling work item 369 * @sanitize_node: sanitation sysfs file to notify 370 */ 371 struct cxl_security_state { 372 unsigned long state; 373 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 374 int poll_tmo_secs; 375 bool sanitize_active; 376 struct delayed_work poll_dwork; 377 struct kernfs_node *sanitize_node; 378 }; 379 380 /* 381 * enum cxl_devtype - delineate type-2 from a generic type-3 device 382 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or 383 * HDM-DB, no requirement that this device implements a 384 * mailbox, or other memory-device-standard manageability 385 * flows. 386 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with 387 * HDM-H and class-mandatory memory device registers 388 */ 389 enum cxl_devtype { 390 CXL_DEVTYPE_DEVMEM, 391 CXL_DEVTYPE_CLASSMEM, 392 }; 393 394 /** 395 * struct cxl_dev_state - The driver device state 396 * 397 * cxl_dev_state represents the CXL driver/device state. It provides an 398 * interface to mailbox commands as well as some cached data about the device. 399 * Currently only memory devices are represented. 400 * 401 * @dev: The device associated with this CXL state 402 * @cxlmd: The device representing the CXL.mem capabilities of @dev 403 * @regs: Parsed register blocks 404 * @cxl_dvsec: Offset to the PCIe device DVSEC 405 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 406 * @media_ready: Indicate whether the device media is usable 407 * @dpa_res: Overall DPA resource tree for the device 408 * @pmem_res: Active Persistent memory capacity configuration 409 * @ram_res: Active Volatile memory capacity configuration 410 * @component_reg_phys: register base of component registers 411 * @serial: PCIe Device Serial Number 412 * @type: Generic Memory Class device or Vendor Specific Memory device 413 */ 414 struct cxl_dev_state { 415 struct device *dev; 416 struct cxl_memdev *cxlmd; 417 struct cxl_regs regs; 418 int cxl_dvsec; 419 bool rcd; 420 bool media_ready; 421 struct resource dpa_res; 422 struct resource pmem_res; 423 struct resource ram_res; 424 resource_size_t component_reg_phys; 425 u64 serial; 426 enum cxl_devtype type; 427 }; 428 429 /** 430 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 431 * 432 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 433 * common memory device functionality like the presence of a mailbox and 434 * the functionality related to that like Identify Memory Device and Get 435 * Partition Info 436 * @cxlds: Core driver state common across Type-2 and Type-3 devices 437 * @payload_size: Size of space for payload 438 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 439 * @lsa_size: Size of Label Storage Area 440 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 441 * @mbox_mutex: Mutex to synchronize mailbox access. 442 * @firmware_version: Firmware version for the memory device. 443 * @enabled_cmds: Hardware commands found enabled in CEL. 444 * @exclusive_cmds: Commands that are kernel-internal only 445 * @total_bytes: sum of all possible capacities 446 * @volatile_only_bytes: hard volatile capacity 447 * @persistent_only_bytes: hard persistent capacity 448 * @partition_align_bytes: alignment size for partition-able capacity 449 * @active_volatile_bytes: sum of hard + soft volatile 450 * @active_persistent_bytes: sum of hard + soft persistent 451 * @next_volatile_bytes: volatile capacity change pending device reset 452 * @next_persistent_bytes: persistent capacity change pending device reset 453 * @event: event log driver state 454 * @poison: poison driver state info 455 * @security: security driver state info 456 * @fw: firmware upload / activation state 457 * @mbox_send: @dev specific transport for transmitting mailbox commands 458 * 459 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 460 * details on capacity parameters. 461 */ 462 struct cxl_memdev_state { 463 struct cxl_dev_state cxlds; 464 size_t payload_size; 465 size_t lsa_size; 466 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 467 char firmware_version[0x10]; 468 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 469 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 470 u64 total_bytes; 471 u64 volatile_only_bytes; 472 u64 persistent_only_bytes; 473 u64 partition_align_bytes; 474 u64 active_volatile_bytes; 475 u64 active_persistent_bytes; 476 u64 next_volatile_bytes; 477 u64 next_persistent_bytes; 478 struct cxl_event_state event; 479 struct cxl_poison_state poison; 480 struct cxl_security_state security; 481 struct cxl_fw_state fw; 482 483 struct rcuwait mbox_wait; 484 int (*mbox_send)(struct cxl_memdev_state *mds, 485 struct cxl_mbox_cmd *cmd); 486 }; 487 488 static inline struct cxl_memdev_state * 489 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 490 { 491 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 492 return NULL; 493 return container_of(cxlds, struct cxl_memdev_state, cxlds); 494 } 495 496 enum cxl_opcode { 497 CXL_MBOX_OP_INVALID = 0x0000, 498 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 499 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 500 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 501 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 502 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 503 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 504 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 505 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 506 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 507 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 508 CXL_MBOX_OP_GET_LOG = 0x0401, 509 CXL_MBOX_OP_IDENTIFY = 0x4000, 510 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 511 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 512 CXL_MBOX_OP_GET_LSA = 0x4102, 513 CXL_MBOX_OP_SET_LSA = 0x4103, 514 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 515 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 516 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 517 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 518 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 519 CXL_MBOX_OP_GET_POISON = 0x4300, 520 CXL_MBOX_OP_INJECT_POISON = 0x4301, 521 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 522 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 523 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 524 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 525 CXL_MBOX_OP_SANITIZE = 0x4400, 526 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 527 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 528 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 529 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 530 CXL_MBOX_OP_UNLOCK = 0x4503, 531 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 532 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 533 CXL_MBOX_OP_MAX = 0x10000 534 }; 535 536 #define DEFINE_CXL_CEL_UUID \ 537 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 538 0x3b, 0x3f, 0x17) 539 540 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 541 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 542 0x40, 0x3d, 0x86) 543 544 struct cxl_mbox_get_supported_logs { 545 __le16 entries; 546 u8 rsvd[6]; 547 struct cxl_gsl_entry { 548 uuid_t uuid; 549 __le32 size; 550 } __packed entry[]; 551 } __packed; 552 553 struct cxl_cel_entry { 554 __le16 opcode; 555 __le16 effect; 556 } __packed; 557 558 struct cxl_mbox_get_log { 559 uuid_t uuid; 560 __le32 offset; 561 __le32 length; 562 } __packed; 563 564 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 565 struct cxl_mbox_identify { 566 char fw_revision[0x10]; 567 __le64 total_capacity; 568 __le64 volatile_capacity; 569 __le64 persistent_capacity; 570 __le64 partition_align; 571 __le16 info_event_log_size; 572 __le16 warning_event_log_size; 573 __le16 failure_event_log_size; 574 __le16 fatal_event_log_size; 575 __le32 lsa_size; 576 u8 poison_list_max_mer[3]; 577 __le16 inject_poison_limit; 578 u8 poison_caps; 579 u8 qos_telemetry_caps; 580 } __packed; 581 582 /* 583 * Common Event Record Format 584 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 585 */ 586 struct cxl_event_record_hdr { 587 uuid_t id; 588 u8 length; 589 u8 flags[3]; 590 __le16 handle; 591 __le16 related_handle; 592 __le64 timestamp; 593 u8 maint_op_class; 594 u8 reserved[15]; 595 } __packed; 596 597 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 598 struct cxl_event_record_raw { 599 struct cxl_event_record_hdr hdr; 600 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 601 } __packed; 602 603 /* 604 * Get Event Records output payload 605 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 606 */ 607 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 608 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 609 struct cxl_get_event_payload { 610 u8 flags; 611 u8 reserved1; 612 __le16 overflow_err_count; 613 __le64 first_overflow_timestamp; 614 __le64 last_overflow_timestamp; 615 __le16 record_count; 616 u8 reserved2[10]; 617 struct cxl_event_record_raw records[]; 618 } __packed; 619 620 /* 621 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 622 */ 623 enum cxl_event_log_type { 624 CXL_EVENT_TYPE_INFO = 0x00, 625 CXL_EVENT_TYPE_WARN, 626 CXL_EVENT_TYPE_FAIL, 627 CXL_EVENT_TYPE_FATAL, 628 CXL_EVENT_TYPE_MAX 629 }; 630 631 /* 632 * Clear Event Records input payload 633 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 634 */ 635 struct cxl_mbox_clear_event_payload { 636 u8 event_log; /* enum cxl_event_log_type */ 637 u8 clear_flags; 638 u8 nr_recs; 639 u8 reserved[3]; 640 __le16 handles[]; 641 } __packed; 642 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 643 644 /* 645 * General Media Event Record 646 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 647 */ 648 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 649 struct cxl_event_gen_media { 650 struct cxl_event_record_hdr hdr; 651 __le64 phys_addr; 652 u8 descriptor; 653 u8 type; 654 u8 transaction_type; 655 u8 validity_flags[2]; 656 u8 channel; 657 u8 rank; 658 u8 device[3]; 659 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 660 u8 reserved[46]; 661 } __packed; 662 663 /* 664 * DRAM Event Record - DER 665 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 666 */ 667 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 668 struct cxl_event_dram { 669 struct cxl_event_record_hdr hdr; 670 __le64 phys_addr; 671 u8 descriptor; 672 u8 type; 673 u8 transaction_type; 674 u8 validity_flags[2]; 675 u8 channel; 676 u8 rank; 677 u8 nibble_mask[3]; 678 u8 bank_group; 679 u8 bank; 680 u8 row[3]; 681 u8 column[2]; 682 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 683 u8 reserved[0x17]; 684 } __packed; 685 686 /* 687 * Get Health Info Record 688 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 689 */ 690 struct cxl_get_health_info { 691 u8 health_status; 692 u8 media_status; 693 u8 add_status; 694 u8 life_used; 695 u8 device_temp[2]; 696 u8 dirty_shutdown_cnt[4]; 697 u8 cor_vol_err_cnt[4]; 698 u8 cor_per_err_cnt[4]; 699 } __packed; 700 701 /* 702 * Memory Module Event Record 703 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 704 */ 705 struct cxl_event_mem_module { 706 struct cxl_event_record_hdr hdr; 707 u8 event_type; 708 struct cxl_get_health_info info; 709 u8 reserved[0x3d]; 710 } __packed; 711 712 struct cxl_mbox_get_partition_info { 713 __le64 active_volatile_cap; 714 __le64 active_persistent_cap; 715 __le64 next_volatile_cap; 716 __le64 next_persistent_cap; 717 } __packed; 718 719 struct cxl_mbox_get_lsa { 720 __le32 offset; 721 __le32 length; 722 } __packed; 723 724 struct cxl_mbox_set_lsa { 725 __le32 offset; 726 __le32 reserved; 727 u8 data[]; 728 } __packed; 729 730 struct cxl_mbox_set_partition_info { 731 __le64 volatile_capacity; 732 u8 flags; 733 } __packed; 734 735 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 736 737 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 738 struct cxl_mbox_set_timestamp_in { 739 __le64 timestamp; 740 741 } __packed; 742 743 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 744 struct cxl_mbox_poison_in { 745 __le64 offset; 746 __le64 length; 747 } __packed; 748 749 struct cxl_mbox_poison_out { 750 u8 flags; 751 u8 rsvd1; 752 __le64 overflow_ts; 753 __le16 count; 754 u8 rsvd2[20]; 755 struct cxl_poison_record { 756 __le64 address; 757 __le32 length; 758 __le32 rsvd; 759 } __packed record[]; 760 } __packed; 761 762 /* 763 * Get Poison List address field encodes the starting 764 * address of poison, and the source of the poison. 765 */ 766 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 767 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 768 769 /* Get Poison List record length is in units of 64 bytes */ 770 #define CXL_POISON_LEN_MULT 64 771 772 /* Kernel defined maximum for a list of poison errors */ 773 #define CXL_POISON_LIST_MAX 1024 774 775 /* Get Poison List: Payload out flags */ 776 #define CXL_POISON_FLAG_MORE BIT(0) 777 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 778 #define CXL_POISON_FLAG_SCANNING BIT(2) 779 780 /* Get Poison List: Poison Source */ 781 #define CXL_POISON_SOURCE_UNKNOWN 0 782 #define CXL_POISON_SOURCE_EXTERNAL 1 783 #define CXL_POISON_SOURCE_INTERNAL 2 784 #define CXL_POISON_SOURCE_INJECTED 3 785 #define CXL_POISON_SOURCE_VENDOR 7 786 787 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 788 struct cxl_mbox_inject_poison { 789 __le64 address; 790 }; 791 792 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 793 struct cxl_mbox_clear_poison { 794 __le64 address; 795 u8 write_data[CXL_POISON_LEN_MULT]; 796 } __packed; 797 798 /** 799 * struct cxl_mem_command - Driver representation of a memory device command 800 * @info: Command information as it exists for the UAPI 801 * @opcode: The actual bits used for the mailbox protocol 802 * @flags: Set of flags effecting driver behavior. 803 * 804 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 805 * will be enabled by the driver regardless of what hardware may have 806 * advertised. 807 * 808 * The cxl_mem_command is the driver's internal representation of commands that 809 * are supported by the driver. Some of these commands may not be supported by 810 * the hardware. The driver will use @info to validate the fields passed in by 811 * the user then submit the @opcode to the hardware. 812 * 813 * See struct cxl_command_info. 814 */ 815 struct cxl_mem_command { 816 struct cxl_command_info info; 817 enum cxl_opcode opcode; 818 u32 flags; 819 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 820 }; 821 822 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 823 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 824 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 825 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 826 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 827 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 828 829 /* set passphrase input payload */ 830 struct cxl_set_pass { 831 u8 type; 832 u8 reserved[31]; 833 /* CXL field using NVDIMM define, same length */ 834 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 835 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 836 } __packed; 837 838 /* disable passphrase input payload */ 839 struct cxl_disable_pass { 840 u8 type; 841 u8 reserved[31]; 842 u8 pass[NVDIMM_PASSPHRASE_LEN]; 843 } __packed; 844 845 /* passphrase secure erase payload */ 846 struct cxl_pass_erase { 847 u8 type; 848 u8 reserved[31]; 849 u8 pass[NVDIMM_PASSPHRASE_LEN]; 850 } __packed; 851 852 enum { 853 CXL_PMEM_SEC_PASS_MASTER = 0, 854 CXL_PMEM_SEC_PASS_USER, 855 }; 856 857 int cxl_internal_send_cmd(struct cxl_memdev_state *mds, 858 struct cxl_mbox_cmd *cmd); 859 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 860 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 861 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 862 int cxl_mem_create_range_info(struct cxl_memdev_state *mds); 863 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev); 864 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 865 unsigned long *cmds); 866 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 867 unsigned long *cmds); 868 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 869 int cxl_set_timestamp(struct cxl_memdev_state *mds); 870 int cxl_poison_state_init(struct cxl_memdev_state *mds); 871 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 872 struct cxl_region *cxlr); 873 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 874 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 875 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 876 877 #ifdef CONFIG_CXL_SUSPEND 878 void cxl_mem_active_inc(void); 879 void cxl_mem_active_dec(void); 880 #else 881 static inline void cxl_mem_active_inc(void) 882 { 883 } 884 static inline void cxl_mem_active_dec(void) 885 { 886 } 887 #endif 888 889 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 890 891 /** 892 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 893 * @regs: mapped registers, see devm_cxl_setup_hdm() 894 * @decoder_count: number of decoders for this port 895 * @target_count: for switch decoders, max downstream port targets 896 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 897 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 898 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 899 */ 900 struct cxl_hdm { 901 struct cxl_component_regs regs; 902 unsigned int decoder_count; 903 unsigned int target_count; 904 unsigned int interleave_mask; 905 unsigned long iw_cap_mask; 906 struct cxl_port *port; 907 }; 908 909 struct seq_file; 910 struct dentry *cxl_debugfs_create_dir(const char *dir); 911 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 912 #endif /* __CXL_MEM_H__ */ 913