1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include "cxl.h" 8 9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 10 #define CXLMDEV_STATUS_OFFSET 0x0 11 #define CXLMDEV_DEV_FATAL BIT(0) 12 #define CXLMDEV_FW_HALT BIT(1) 13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 14 #define CXLMDEV_MS_NOT_READY 0 15 #define CXLMDEV_MS_READY 1 16 #define CXLMDEV_MS_ERROR 2 17 #define CXLMDEV_MS_DISABLED 3 18 #define CXLMDEV_READY(status) \ 19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 20 CXLMDEV_MS_READY) 21 #define CXLMDEV_MBOX_IF_READY BIT(4) 22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 23 #define CXLMDEV_RESET_NEEDED_NOT 0 24 #define CXLMDEV_RESET_NEEDED_COLD 1 25 #define CXLMDEV_RESET_NEEDED_WARM 2 26 #define CXLMDEV_RESET_NEEDED_HOT 3 27 #define CXLMDEV_RESET_NEEDED_CXL 4 28 #define CXLMDEV_RESET_NEEDED(status) \ 29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 30 CXLMDEV_RESET_NEEDED_NOT) 31 32 /** 33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 34 * @dev: driver core device object 35 * @cdev: char dev core object for ioctl operations 36 * @cxlds: The device state backing this device 37 * @detach_work: active memdev lost a port in its ancestry 38 * @id: id number of this memdev instance. 39 */ 40 struct cxl_memdev { 41 struct device dev; 42 struct cdev cdev; 43 struct cxl_dev_state *cxlds; 44 struct work_struct detach_work; 45 int id; 46 }; 47 48 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 49 { 50 return container_of(dev, struct cxl_memdev, dev); 51 } 52 53 bool is_cxl_memdev(struct device *dev); 54 static inline bool is_cxl_endpoint(struct cxl_port *port) 55 { 56 return is_cxl_memdev(port->uport); 57 } 58 59 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 60 61 /** 62 * struct cxl_mbox_cmd - A command to be submitted to hardware. 63 * @opcode: (input) The command set and command submitted to hardware. 64 * @payload_in: (input) Pointer to the input payload. 65 * @payload_out: (output) Pointer to the output payload. Must be allocated by 66 * the caller. 67 * @size_in: (input) Number of bytes to load from @payload_in. 68 * @size_out: (input) Max number of bytes loaded into @payload_out. 69 * (output) Number of bytes generated by the device. For fixed size 70 * outputs commands this is always expected to be deterministic. For 71 * variable sized output commands, it tells the exact number of bytes 72 * written. 73 * @return_code: (output) Error code returned from hardware. 74 * 75 * This is the primary mechanism used to send commands to the hardware. 76 * All the fields except @payload_* correspond exactly to the fields described in 77 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 78 * @payload_out are written to, and read from the Command Payload Registers 79 * defined in CXL 2.0 8.2.8.4.8. 80 */ 81 struct cxl_mbox_cmd { 82 u16 opcode; 83 void *payload_in; 84 void *payload_out; 85 size_t size_in; 86 size_t size_out; 87 u16 return_code; 88 #define CXL_MBOX_SUCCESS 0 89 }; 90 91 /* 92 * CXL 2.0 - Memory capacity multiplier 93 * See Section 8.2.9.5 94 * 95 * Volatile, Persistent, and Partition capacities are specified to be in 96 * multiples of 256MB - define a multiplier to convert to/from bytes. 97 */ 98 #define CXL_CAPACITY_MULTIPLIER SZ_256M 99 100 /** 101 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 102 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE 103 * @ranges: Number of active HDM ranges this device uses. 104 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 105 */ 106 struct cxl_endpoint_dvsec_info { 107 bool mem_enabled; 108 int ranges; 109 struct range dvsec_range[2]; 110 }; 111 112 /** 113 * struct cxl_dev_state - The driver device state 114 * 115 * cxl_dev_state represents the CXL driver/device state. It provides an 116 * interface to mailbox commands as well as some cached data about the device. 117 * Currently only memory devices are represented. 118 * 119 * @dev: The device associated with this CXL state 120 * @regs: Parsed register blocks 121 * @cxl_dvsec: Offset to the PCIe device DVSEC 122 * @payload_size: Size of space for payload 123 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 124 * @lsa_size: Size of Label Storage Area 125 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 126 * @mbox_mutex: Mutex to synchronize mailbox access. 127 * @firmware_version: Firmware version for the memory device. 128 * @enabled_cmds: Hardware commands found enabled in CEL. 129 * @exclusive_cmds: Commands that are kernel-internal only 130 * @pmem_range: Active Persistent memory capacity configuration 131 * @ram_range: Active Volatile memory capacity configuration 132 * @total_bytes: sum of all possible capacities 133 * @volatile_only_bytes: hard volatile capacity 134 * @persistent_only_bytes: hard persistent capacity 135 * @partition_align_bytes: alignment size for partition-able capacity 136 * @active_volatile_bytes: sum of hard + soft volatile 137 * @active_persistent_bytes: sum of hard + soft persistent 138 * @next_volatile_bytes: volatile capacity change pending device reset 139 * @next_persistent_bytes: persistent capacity change pending device reset 140 * @component_reg_phys: register base of component registers 141 * @info: Cached DVSEC information about the device. 142 * @serial: PCIe Device Serial Number 143 * @mbox_send: @dev specific transport for transmitting mailbox commands 144 * @wait_media_ready: @dev specific method to await media ready 145 * 146 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 147 * details on capacity parameters. 148 */ 149 struct cxl_dev_state { 150 struct device *dev; 151 152 struct cxl_regs regs; 153 int cxl_dvsec; 154 155 size_t payload_size; 156 size_t lsa_size; 157 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 158 char firmware_version[0x10]; 159 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 160 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 161 162 struct range pmem_range; 163 struct range ram_range; 164 u64 total_bytes; 165 u64 volatile_only_bytes; 166 u64 persistent_only_bytes; 167 u64 partition_align_bytes; 168 169 u64 active_volatile_bytes; 170 u64 active_persistent_bytes; 171 u64 next_volatile_bytes; 172 u64 next_persistent_bytes; 173 174 resource_size_t component_reg_phys; 175 struct cxl_endpoint_dvsec_info info; 176 u64 serial; 177 178 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 179 int (*wait_media_ready)(struct cxl_dev_state *cxlds); 180 }; 181 182 enum cxl_opcode { 183 CXL_MBOX_OP_INVALID = 0x0000, 184 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 185 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 186 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 187 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 188 CXL_MBOX_OP_GET_LOG = 0x0401, 189 CXL_MBOX_OP_IDENTIFY = 0x4000, 190 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 191 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 192 CXL_MBOX_OP_GET_LSA = 0x4102, 193 CXL_MBOX_OP_SET_LSA = 0x4103, 194 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 195 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 196 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 197 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 198 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 199 CXL_MBOX_OP_GET_POISON = 0x4300, 200 CXL_MBOX_OP_INJECT_POISON = 0x4301, 201 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 202 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 203 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 204 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 205 CXL_MBOX_OP_MAX = 0x10000 206 }; 207 208 #define DEFINE_CXL_CEL_UUID \ 209 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 210 0x3b, 0x3f, 0x17) 211 212 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 213 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 214 0x40, 0x3d, 0x86) 215 216 struct cxl_mbox_get_supported_logs { 217 __le16 entries; 218 u8 rsvd[6]; 219 struct cxl_gsl_entry { 220 uuid_t uuid; 221 __le32 size; 222 } __packed entry[]; 223 } __packed; 224 225 struct cxl_cel_entry { 226 __le16 opcode; 227 __le16 effect; 228 } __packed; 229 230 struct cxl_mbox_get_log { 231 uuid_t uuid; 232 __le32 offset; 233 __le32 length; 234 } __packed; 235 236 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 237 struct cxl_mbox_identify { 238 char fw_revision[0x10]; 239 __le64 total_capacity; 240 __le64 volatile_capacity; 241 __le64 persistent_capacity; 242 __le64 partition_align; 243 __le16 info_event_log_size; 244 __le16 warning_event_log_size; 245 __le16 failure_event_log_size; 246 __le16 fatal_event_log_size; 247 __le32 lsa_size; 248 u8 poison_list_max_mer[3]; 249 __le16 inject_poison_limit; 250 u8 poison_caps; 251 u8 qos_telemetry_caps; 252 } __packed; 253 254 struct cxl_mbox_get_lsa { 255 u32 offset; 256 u32 length; 257 } __packed; 258 259 struct cxl_mbox_set_lsa { 260 u32 offset; 261 u32 reserved; 262 u8 data[]; 263 } __packed; 264 265 /** 266 * struct cxl_mem_command - Driver representation of a memory device command 267 * @info: Command information as it exists for the UAPI 268 * @opcode: The actual bits used for the mailbox protocol 269 * @flags: Set of flags effecting driver behavior. 270 * 271 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 272 * will be enabled by the driver regardless of what hardware may have 273 * advertised. 274 * 275 * The cxl_mem_command is the driver's internal representation of commands that 276 * are supported by the driver. Some of these commands may not be supported by 277 * the hardware. The driver will use @info to validate the fields passed in by 278 * the user then submit the @opcode to the hardware. 279 * 280 * See struct cxl_command_info. 281 */ 282 struct cxl_mem_command { 283 struct cxl_command_info info; 284 enum cxl_opcode opcode; 285 u32 flags; 286 #define CXL_CMD_FLAG_NONE 0 287 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 288 }; 289 290 int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in, 291 size_t in_size, void *out, size_t out_size); 292 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 293 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 294 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 295 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 296 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 297 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 298 299 struct cxl_hdm { 300 struct cxl_component_regs regs; 301 unsigned int decoder_count; 302 unsigned int target_count; 303 unsigned int interleave_mask; 304 struct cxl_port *port; 305 }; 306 #endif /* __CXL_MEM_H__ */ 307