1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/io.h> 10 11 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 12 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 13 #define CXLDEV_CAP_ARRAY_CAP_ID 0 14 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 15 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 16 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 17 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 18 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 19 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 20 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 21 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 22 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 23 24 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 25 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 26 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 27 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 28 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 29 #define CXLDEV_MBOX_CMD_OFFSET 0x08 30 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 31 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 32 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 33 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 34 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 35 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 36 37 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 38 #define CXLMDEV_STATUS_OFFSET 0x0 39 #define CXLMDEV_DEV_FATAL BIT(0) 40 #define CXLMDEV_FW_HALT BIT(1) 41 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 42 #define CXLMDEV_MS_NOT_READY 0 43 #define CXLMDEV_MS_READY 1 44 #define CXLMDEV_MS_ERROR 2 45 #define CXLMDEV_MS_DISABLED 3 46 #define CXLMDEV_READY(status) \ 47 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 48 CXLMDEV_MS_READY) 49 #define CXLMDEV_MBOX_IF_READY BIT(4) 50 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 51 #define CXLMDEV_RESET_NEEDED_NOT 0 52 #define CXLMDEV_RESET_NEEDED_COLD 1 53 #define CXLMDEV_RESET_NEEDED_WARM 2 54 #define CXLMDEV_RESET_NEEDED_HOT 3 55 #define CXLMDEV_RESET_NEEDED_CXL 4 56 #define CXLMDEV_RESET_NEEDED(status) \ 57 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 58 CXLMDEV_RESET_NEEDED_NOT) 59 60 struct cxl_memdev; 61 /** 62 * struct cxl_mem - A CXL memory device 63 * @pdev: The PCI device associated with this CXL device. 64 * @regs: IO mappings to the device's MMIO 65 * @status_regs: CXL 2.0 8.2.8.3 Device Status Registers 66 * @mbox_regs: CXL 2.0 8.2.8.4 Mailbox Registers 67 * @memdev_regs: CXL 2.0 8.2.8.5 Memory Device Registers 68 * @payload_size: Size of space for payload 69 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 70 * @mbox_mutex: Mutex to synchronize mailbox access. 71 * @firmware_version: Firmware version for the memory device. 72 * @enabled_commands: Hardware commands found enabled in CEL. 73 * @pmem_range: Persistent memory capacity information. 74 * @ram_range: Volatile memory capacity information. 75 */ 76 struct cxl_mem { 77 struct pci_dev *pdev; 78 void __iomem *regs; 79 struct cxl_memdev *cxlmd; 80 81 void __iomem *status_regs; 82 void __iomem *mbox_regs; 83 void __iomem *memdev_regs; 84 85 size_t payload_size; 86 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 87 char firmware_version[0x10]; 88 unsigned long *enabled_cmds; 89 90 struct range pmem_range; 91 struct range ram_range; 92 }; 93 94 extern struct bus_type cxl_bus_type; 95 #endif /* __CXL_H__ */ 96