1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #include <linux/io-64-nonatomic-lo-hi.h> 5 #include <linux/firmware.h> 6 #include <linux/device.h> 7 #include <linux/slab.h> 8 #include <linux/idr.h> 9 #include <linux/pci.h> 10 #include <cxlmem.h> 11 #include "trace.h" 12 #include "core.h" 13 14 static DECLARE_RWSEM(cxl_memdev_rwsem); 15 16 /* 17 * An entire PCI topology full of devices should be enough for any 18 * config 19 */ 20 #define CXL_MEM_MAX_DEVS 65536 21 22 static int cxl_mem_major; 23 static DEFINE_IDA(cxl_memdev_ida); 24 25 static void cxl_memdev_release(struct device *dev) 26 { 27 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 28 29 ida_free(&cxl_memdev_ida, cxlmd->id); 30 kfree(cxlmd); 31 } 32 33 static char *cxl_memdev_devnode(const struct device *dev, umode_t *mode, kuid_t *uid, 34 kgid_t *gid) 35 { 36 return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev)); 37 } 38 39 static ssize_t firmware_version_show(struct device *dev, 40 struct device_attribute *attr, char *buf) 41 { 42 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 43 struct cxl_dev_state *cxlds = cxlmd->cxlds; 44 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 45 46 if (!mds) 47 return sysfs_emit(buf, "\n"); 48 return sysfs_emit(buf, "%.16s\n", mds->firmware_version); 49 } 50 static DEVICE_ATTR_RO(firmware_version); 51 52 static ssize_t payload_max_show(struct device *dev, 53 struct device_attribute *attr, char *buf) 54 { 55 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 56 struct cxl_dev_state *cxlds = cxlmd->cxlds; 57 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 58 59 if (!mds) 60 return sysfs_emit(buf, "\n"); 61 return sysfs_emit(buf, "%zu\n", mds->payload_size); 62 } 63 static DEVICE_ATTR_RO(payload_max); 64 65 static ssize_t label_storage_size_show(struct device *dev, 66 struct device_attribute *attr, char *buf) 67 { 68 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 69 struct cxl_dev_state *cxlds = cxlmd->cxlds; 70 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 71 72 if (!mds) 73 return sysfs_emit(buf, "\n"); 74 return sysfs_emit(buf, "%zu\n", mds->lsa_size); 75 } 76 static DEVICE_ATTR_RO(label_storage_size); 77 78 static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr, 79 char *buf) 80 { 81 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 82 struct cxl_dev_state *cxlds = cxlmd->cxlds; 83 unsigned long long len = resource_size(&cxlds->ram_res); 84 85 return sysfs_emit(buf, "%#llx\n", len); 86 } 87 88 static struct device_attribute dev_attr_ram_size = 89 __ATTR(size, 0444, ram_size_show, NULL); 90 91 static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, 92 char *buf) 93 { 94 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 95 struct cxl_dev_state *cxlds = cxlmd->cxlds; 96 unsigned long long len = resource_size(&cxlds->pmem_res); 97 98 return sysfs_emit(buf, "%#llx\n", len); 99 } 100 101 static struct device_attribute dev_attr_pmem_size = 102 __ATTR(size, 0444, pmem_size_show, NULL); 103 104 static ssize_t serial_show(struct device *dev, struct device_attribute *attr, 105 char *buf) 106 { 107 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 108 struct cxl_dev_state *cxlds = cxlmd->cxlds; 109 110 return sysfs_emit(buf, "%#llx\n", cxlds->serial); 111 } 112 static DEVICE_ATTR_RO(serial); 113 114 static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr, 115 char *buf) 116 { 117 return sprintf(buf, "%d\n", dev_to_node(dev)); 118 } 119 static DEVICE_ATTR_RO(numa_node); 120 121 static ssize_t security_state_show(struct device *dev, 122 struct device_attribute *attr, 123 char *buf) 124 { 125 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 126 struct cxl_dev_state *cxlds = cxlmd->cxlds; 127 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 128 unsigned long state = mds->security.state; 129 int rc = 0; 130 131 /* sync with latest submission state */ 132 mutex_lock(&mds->mbox_mutex); 133 if (mds->security.sanitize_active) 134 rc = sysfs_emit(buf, "sanitize\n"); 135 mutex_unlock(&mds->mbox_mutex); 136 if (rc) 137 return rc; 138 139 if (!(state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) 140 return sysfs_emit(buf, "disabled\n"); 141 if (state & CXL_PMEM_SEC_STATE_FROZEN || 142 state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT || 143 state & CXL_PMEM_SEC_STATE_USER_PLIMIT) 144 return sysfs_emit(buf, "frozen\n"); 145 if (state & CXL_PMEM_SEC_STATE_LOCKED) 146 return sysfs_emit(buf, "locked\n"); 147 else 148 return sysfs_emit(buf, "unlocked\n"); 149 } 150 static struct device_attribute dev_attr_security_state = 151 __ATTR(state, 0444, security_state_show, NULL); 152 153 static ssize_t security_sanitize_store(struct device *dev, 154 struct device_attribute *attr, 155 const char *buf, size_t len) 156 { 157 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 158 bool sanitize; 159 ssize_t rc; 160 161 if (kstrtobool(buf, &sanitize) || !sanitize) 162 return -EINVAL; 163 164 rc = cxl_mem_sanitize(cxlmd, CXL_MBOX_OP_SANITIZE); 165 if (rc) 166 return rc; 167 168 return len; 169 } 170 static struct device_attribute dev_attr_security_sanitize = 171 __ATTR(sanitize, 0200, NULL, security_sanitize_store); 172 173 static ssize_t security_erase_store(struct device *dev, 174 struct device_attribute *attr, 175 const char *buf, size_t len) 176 { 177 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 178 ssize_t rc; 179 bool erase; 180 181 if (kstrtobool(buf, &erase) || !erase) 182 return -EINVAL; 183 184 rc = cxl_mem_sanitize(cxlmd, CXL_MBOX_OP_SECURE_ERASE); 185 if (rc) 186 return rc; 187 188 return len; 189 } 190 static struct device_attribute dev_attr_security_erase = 191 __ATTR(erase, 0200, NULL, security_erase_store); 192 193 static int cxl_get_poison_by_memdev(struct cxl_memdev *cxlmd) 194 { 195 struct cxl_dev_state *cxlds = cxlmd->cxlds; 196 u64 offset, length; 197 int rc = 0; 198 199 /* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */ 200 if (resource_size(&cxlds->pmem_res)) { 201 offset = cxlds->pmem_res.start; 202 length = resource_size(&cxlds->pmem_res); 203 rc = cxl_mem_get_poison(cxlmd, offset, length, NULL); 204 if (rc) 205 return rc; 206 } 207 if (resource_size(&cxlds->ram_res)) { 208 offset = cxlds->ram_res.start; 209 length = resource_size(&cxlds->ram_res); 210 rc = cxl_mem_get_poison(cxlmd, offset, length, NULL); 211 /* 212 * Invalid Physical Address is not an error for 213 * volatile addresses. Device support is optional. 214 */ 215 if (rc == -EFAULT) 216 rc = 0; 217 } 218 return rc; 219 } 220 221 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd) 222 { 223 struct cxl_port *port; 224 int rc; 225 226 port = cxlmd->endpoint; 227 if (!port || !is_cxl_endpoint(port)) 228 return -EINVAL; 229 230 rc = down_read_interruptible(&cxl_region_rwsem); 231 if (rc) 232 return rc; 233 234 rc = down_read_interruptible(&cxl_dpa_rwsem); 235 if (rc) { 236 up_read(&cxl_region_rwsem); 237 return rc; 238 } 239 240 if (cxl_num_decoders_committed(port) == 0) { 241 /* No regions mapped to this memdev */ 242 rc = cxl_get_poison_by_memdev(cxlmd); 243 } else { 244 /* Regions mapped, collect poison by endpoint */ 245 rc = cxl_get_poison_by_endpoint(port); 246 } 247 up_read(&cxl_dpa_rwsem); 248 up_read(&cxl_region_rwsem); 249 250 return rc; 251 } 252 EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL); 253 254 static int cxl_validate_poison_dpa(struct cxl_memdev *cxlmd, u64 dpa) 255 { 256 struct cxl_dev_state *cxlds = cxlmd->cxlds; 257 258 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 259 return 0; 260 261 if (!resource_size(&cxlds->dpa_res)) { 262 dev_dbg(cxlds->dev, "device has no dpa resource\n"); 263 return -EINVAL; 264 } 265 if (dpa < cxlds->dpa_res.start || dpa > cxlds->dpa_res.end) { 266 dev_dbg(cxlds->dev, "dpa:0x%llx not in resource:%pR\n", 267 dpa, &cxlds->dpa_res); 268 return -EINVAL; 269 } 270 if (!IS_ALIGNED(dpa, 64)) { 271 dev_dbg(cxlds->dev, "dpa:0x%llx is not 64-byte aligned\n", dpa); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa) 279 { 280 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); 281 struct cxl_mbox_inject_poison inject; 282 struct cxl_poison_record record; 283 struct cxl_mbox_cmd mbox_cmd; 284 struct cxl_region *cxlr; 285 int rc; 286 287 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 288 return 0; 289 290 rc = down_read_interruptible(&cxl_region_rwsem); 291 if (rc) 292 return rc; 293 294 rc = down_read_interruptible(&cxl_dpa_rwsem); 295 if (rc) { 296 up_read(&cxl_region_rwsem); 297 return rc; 298 } 299 300 rc = cxl_validate_poison_dpa(cxlmd, dpa); 301 if (rc) 302 goto out; 303 304 inject.address = cpu_to_le64(dpa); 305 mbox_cmd = (struct cxl_mbox_cmd) { 306 .opcode = CXL_MBOX_OP_INJECT_POISON, 307 .size_in = sizeof(inject), 308 .payload_in = &inject, 309 }; 310 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 311 if (rc) 312 goto out; 313 314 cxlr = cxl_dpa_to_region(cxlmd, dpa); 315 if (cxlr) 316 dev_warn_once(mds->cxlds.dev, 317 "poison inject dpa:%#llx region: %s\n", dpa, 318 dev_name(&cxlr->dev)); 319 320 record = (struct cxl_poison_record) { 321 .address = cpu_to_le64(dpa), 322 .length = cpu_to_le32(1), 323 }; 324 trace_cxl_poison(cxlmd, cxlr, &record, 0, 0, CXL_POISON_TRACE_INJECT); 325 out: 326 up_read(&cxl_dpa_rwsem); 327 up_read(&cxl_region_rwsem); 328 329 return rc; 330 } 331 EXPORT_SYMBOL_NS_GPL(cxl_inject_poison, CXL); 332 333 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa) 334 { 335 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); 336 struct cxl_mbox_clear_poison clear; 337 struct cxl_poison_record record; 338 struct cxl_mbox_cmd mbox_cmd; 339 struct cxl_region *cxlr; 340 int rc; 341 342 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 343 return 0; 344 345 rc = down_read_interruptible(&cxl_region_rwsem); 346 if (rc) 347 return rc; 348 349 rc = down_read_interruptible(&cxl_dpa_rwsem); 350 if (rc) { 351 up_read(&cxl_region_rwsem); 352 return rc; 353 } 354 355 rc = cxl_validate_poison_dpa(cxlmd, dpa); 356 if (rc) 357 goto out; 358 359 /* 360 * In CXL 3.0 Spec 8.2.9.8.4.3, the Clear Poison mailbox command 361 * is defined to accept 64 bytes of write-data, along with the 362 * address to clear. This driver uses zeroes as write-data. 363 */ 364 clear = (struct cxl_mbox_clear_poison) { 365 .address = cpu_to_le64(dpa) 366 }; 367 368 mbox_cmd = (struct cxl_mbox_cmd) { 369 .opcode = CXL_MBOX_OP_CLEAR_POISON, 370 .size_in = sizeof(clear), 371 .payload_in = &clear, 372 }; 373 374 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 375 if (rc) 376 goto out; 377 378 cxlr = cxl_dpa_to_region(cxlmd, dpa); 379 if (cxlr) 380 dev_warn_once(mds->cxlds.dev, 381 "poison clear dpa:%#llx region: %s\n", dpa, 382 dev_name(&cxlr->dev)); 383 384 record = (struct cxl_poison_record) { 385 .address = cpu_to_le64(dpa), 386 .length = cpu_to_le32(1), 387 }; 388 trace_cxl_poison(cxlmd, cxlr, &record, 0, 0, CXL_POISON_TRACE_CLEAR); 389 out: 390 up_read(&cxl_dpa_rwsem); 391 up_read(&cxl_region_rwsem); 392 393 return rc; 394 } 395 EXPORT_SYMBOL_NS_GPL(cxl_clear_poison, CXL); 396 397 static struct attribute *cxl_memdev_attributes[] = { 398 &dev_attr_serial.attr, 399 &dev_attr_firmware_version.attr, 400 &dev_attr_payload_max.attr, 401 &dev_attr_label_storage_size.attr, 402 &dev_attr_numa_node.attr, 403 NULL, 404 }; 405 406 static struct attribute *cxl_memdev_pmem_attributes[] = { 407 &dev_attr_pmem_size.attr, 408 NULL, 409 }; 410 411 static struct attribute *cxl_memdev_ram_attributes[] = { 412 &dev_attr_ram_size.attr, 413 NULL, 414 }; 415 416 static struct attribute *cxl_memdev_security_attributes[] = { 417 &dev_attr_security_state.attr, 418 &dev_attr_security_sanitize.attr, 419 &dev_attr_security_erase.attr, 420 NULL, 421 }; 422 423 static umode_t cxl_memdev_visible(struct kobject *kobj, struct attribute *a, 424 int n) 425 { 426 if (!IS_ENABLED(CONFIG_NUMA) && a == &dev_attr_numa_node.attr) 427 return 0; 428 return a->mode; 429 } 430 431 static struct attribute_group cxl_memdev_attribute_group = { 432 .attrs = cxl_memdev_attributes, 433 .is_visible = cxl_memdev_visible, 434 }; 435 436 static struct attribute_group cxl_memdev_ram_attribute_group = { 437 .name = "ram", 438 .attrs = cxl_memdev_ram_attributes, 439 }; 440 441 static struct attribute_group cxl_memdev_pmem_attribute_group = { 442 .name = "pmem", 443 .attrs = cxl_memdev_pmem_attributes, 444 }; 445 446 static umode_t cxl_memdev_security_visible(struct kobject *kobj, 447 struct attribute *a, int n) 448 { 449 struct device *dev = kobj_to_dev(kobj); 450 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 451 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); 452 453 if (a == &dev_attr_security_sanitize.attr && 454 !test_bit(CXL_SEC_ENABLED_SANITIZE, mds->security.enabled_cmds)) 455 return 0; 456 457 if (a == &dev_attr_security_erase.attr && 458 !test_bit(CXL_SEC_ENABLED_SECURE_ERASE, mds->security.enabled_cmds)) 459 return 0; 460 461 return a->mode; 462 } 463 464 static struct attribute_group cxl_memdev_security_attribute_group = { 465 .name = "security", 466 .attrs = cxl_memdev_security_attributes, 467 .is_visible = cxl_memdev_security_visible, 468 }; 469 470 static const struct attribute_group *cxl_memdev_attribute_groups[] = { 471 &cxl_memdev_attribute_group, 472 &cxl_memdev_ram_attribute_group, 473 &cxl_memdev_pmem_attribute_group, 474 &cxl_memdev_security_attribute_group, 475 NULL, 476 }; 477 478 static const struct device_type cxl_memdev_type = { 479 .name = "cxl_memdev", 480 .release = cxl_memdev_release, 481 .devnode = cxl_memdev_devnode, 482 .groups = cxl_memdev_attribute_groups, 483 }; 484 485 bool is_cxl_memdev(const struct device *dev) 486 { 487 return dev->type == &cxl_memdev_type; 488 } 489 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL); 490 491 /** 492 * set_exclusive_cxl_commands() - atomically disable user cxl commands 493 * @mds: The device state to operate on 494 * @cmds: bitmap of commands to mark exclusive 495 * 496 * Grab the cxl_memdev_rwsem in write mode to flush in-flight 497 * invocations of the ioctl path and then disable future execution of 498 * commands with the command ids set in @cmds. 499 */ 500 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 501 unsigned long *cmds) 502 { 503 down_write(&cxl_memdev_rwsem); 504 bitmap_or(mds->exclusive_cmds, mds->exclusive_cmds, cmds, 505 CXL_MEM_COMMAND_ID_MAX); 506 up_write(&cxl_memdev_rwsem); 507 } 508 EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL); 509 510 /** 511 * clear_exclusive_cxl_commands() - atomically enable user cxl commands 512 * @mds: The device state to modify 513 * @cmds: bitmap of commands to mark available for userspace 514 */ 515 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 516 unsigned long *cmds) 517 { 518 down_write(&cxl_memdev_rwsem); 519 bitmap_andnot(mds->exclusive_cmds, mds->exclusive_cmds, cmds, 520 CXL_MEM_COMMAND_ID_MAX); 521 up_write(&cxl_memdev_rwsem); 522 } 523 EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL); 524 525 static void cxl_memdev_shutdown(struct device *dev) 526 { 527 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 528 529 down_write(&cxl_memdev_rwsem); 530 cxlmd->cxlds = NULL; 531 up_write(&cxl_memdev_rwsem); 532 } 533 534 static void cxl_memdev_unregister(void *_cxlmd) 535 { 536 struct cxl_memdev *cxlmd = _cxlmd; 537 struct device *dev = &cxlmd->dev; 538 539 cdev_device_del(&cxlmd->cdev, dev); 540 cxl_memdev_shutdown(dev); 541 put_device(dev); 542 } 543 544 static void detach_memdev(struct work_struct *work) 545 { 546 struct cxl_memdev *cxlmd; 547 548 cxlmd = container_of(work, typeof(*cxlmd), detach_work); 549 device_release_driver(&cxlmd->dev); 550 put_device(&cxlmd->dev); 551 } 552 553 static struct lock_class_key cxl_memdev_key; 554 555 static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds, 556 const struct file_operations *fops) 557 { 558 struct cxl_memdev *cxlmd; 559 struct device *dev; 560 struct cdev *cdev; 561 int rc; 562 563 cxlmd = kzalloc(sizeof(*cxlmd), GFP_KERNEL); 564 if (!cxlmd) 565 return ERR_PTR(-ENOMEM); 566 567 rc = ida_alloc_max(&cxl_memdev_ida, CXL_MEM_MAX_DEVS - 1, GFP_KERNEL); 568 if (rc < 0) 569 goto err; 570 cxlmd->id = rc; 571 cxlmd->depth = -1; 572 573 dev = &cxlmd->dev; 574 device_initialize(dev); 575 lockdep_set_class(&dev->mutex, &cxl_memdev_key); 576 dev->parent = cxlds->dev; 577 dev->bus = &cxl_bus_type; 578 dev->devt = MKDEV(cxl_mem_major, cxlmd->id); 579 dev->type = &cxl_memdev_type; 580 device_set_pm_not_required(dev); 581 INIT_WORK(&cxlmd->detach_work, detach_memdev); 582 583 cdev = &cxlmd->cdev; 584 cdev_init(cdev, fops); 585 return cxlmd; 586 587 err: 588 kfree(cxlmd); 589 return ERR_PTR(rc); 590 } 591 592 static long __cxl_memdev_ioctl(struct cxl_memdev *cxlmd, unsigned int cmd, 593 unsigned long arg) 594 { 595 switch (cmd) { 596 case CXL_MEM_QUERY_COMMANDS: 597 return cxl_query_cmd(cxlmd, (void __user *)arg); 598 case CXL_MEM_SEND_COMMAND: 599 return cxl_send_cmd(cxlmd, (void __user *)arg); 600 default: 601 return -ENOTTY; 602 } 603 } 604 605 static long cxl_memdev_ioctl(struct file *file, unsigned int cmd, 606 unsigned long arg) 607 { 608 struct cxl_memdev *cxlmd = file->private_data; 609 struct cxl_dev_state *cxlds; 610 int rc = -ENXIO; 611 612 down_read(&cxl_memdev_rwsem); 613 cxlds = cxlmd->cxlds; 614 if (cxlds && cxlds->type == CXL_DEVTYPE_CLASSMEM) 615 rc = __cxl_memdev_ioctl(cxlmd, cmd, arg); 616 up_read(&cxl_memdev_rwsem); 617 618 return rc; 619 } 620 621 static int cxl_memdev_open(struct inode *inode, struct file *file) 622 { 623 struct cxl_memdev *cxlmd = 624 container_of(inode->i_cdev, typeof(*cxlmd), cdev); 625 626 get_device(&cxlmd->dev); 627 file->private_data = cxlmd; 628 629 return 0; 630 } 631 632 static int cxl_memdev_release_file(struct inode *inode, struct file *file) 633 { 634 struct cxl_memdev *cxlmd = 635 container_of(inode->i_cdev, typeof(*cxlmd), cdev); 636 637 put_device(&cxlmd->dev); 638 639 return 0; 640 } 641 642 /** 643 * cxl_mem_get_fw_info - Get Firmware info 644 * @mds: The device data for the operation 645 * 646 * Retrieve firmware info for the device specified. 647 * 648 * Return: 0 if no error: or the result of the mailbox command. 649 * 650 * See CXL-3.0 8.2.9.3.1 Get FW Info 651 */ 652 static int cxl_mem_get_fw_info(struct cxl_memdev_state *mds) 653 { 654 struct cxl_mbox_get_fw_info info; 655 struct cxl_mbox_cmd mbox_cmd; 656 int rc; 657 658 mbox_cmd = (struct cxl_mbox_cmd) { 659 .opcode = CXL_MBOX_OP_GET_FW_INFO, 660 .size_out = sizeof(info), 661 .payload_out = &info, 662 }; 663 664 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 665 if (rc < 0) 666 return rc; 667 668 mds->fw.num_slots = info.num_slots; 669 mds->fw.cur_slot = FIELD_GET(CXL_FW_INFO_SLOT_INFO_CUR_MASK, 670 info.slot_info); 671 672 return 0; 673 } 674 675 /** 676 * cxl_mem_activate_fw - Activate Firmware 677 * @mds: The device data for the operation 678 * @slot: slot number to activate 679 * 680 * Activate firmware in a given slot for the device specified. 681 * 682 * Return: 0 if no error: or the result of the mailbox command. 683 * 684 * See CXL-3.0 8.2.9.3.3 Activate FW 685 */ 686 static int cxl_mem_activate_fw(struct cxl_memdev_state *mds, int slot) 687 { 688 struct cxl_mbox_activate_fw activate; 689 struct cxl_mbox_cmd mbox_cmd; 690 691 if (slot == 0 || slot > mds->fw.num_slots) 692 return -EINVAL; 693 694 mbox_cmd = (struct cxl_mbox_cmd) { 695 .opcode = CXL_MBOX_OP_ACTIVATE_FW, 696 .size_in = sizeof(activate), 697 .payload_in = &activate, 698 }; 699 700 /* Only offline activation supported for now */ 701 activate.action = CXL_FW_ACTIVATE_OFFLINE; 702 activate.slot = slot; 703 704 return cxl_internal_send_cmd(mds, &mbox_cmd); 705 } 706 707 /** 708 * cxl_mem_abort_fw_xfer - Abort an in-progress FW transfer 709 * @mds: The device data for the operation 710 * 711 * Abort an in-progress firmware transfer for the device specified. 712 * 713 * Return: 0 if no error: or the result of the mailbox command. 714 * 715 * See CXL-3.0 8.2.9.3.2 Transfer FW 716 */ 717 static int cxl_mem_abort_fw_xfer(struct cxl_memdev_state *mds) 718 { 719 struct cxl_mbox_transfer_fw *transfer; 720 struct cxl_mbox_cmd mbox_cmd; 721 int rc; 722 723 transfer = kzalloc(struct_size(transfer, data, 0), GFP_KERNEL); 724 if (!transfer) 725 return -ENOMEM; 726 727 /* Set a 1s poll interval and a total wait time of 30s */ 728 mbox_cmd = (struct cxl_mbox_cmd) { 729 .opcode = CXL_MBOX_OP_TRANSFER_FW, 730 .size_in = sizeof(*transfer), 731 .payload_in = transfer, 732 .poll_interval_ms = 1000, 733 .poll_count = 30, 734 }; 735 736 transfer->action = CXL_FW_TRANSFER_ACTION_ABORT; 737 738 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 739 kfree(transfer); 740 return rc; 741 } 742 743 static void cxl_fw_cleanup(struct fw_upload *fwl) 744 { 745 struct cxl_memdev_state *mds = fwl->dd_handle; 746 747 mds->fw.next_slot = 0; 748 } 749 750 static int cxl_fw_do_cancel(struct fw_upload *fwl) 751 { 752 struct cxl_memdev_state *mds = fwl->dd_handle; 753 struct cxl_dev_state *cxlds = &mds->cxlds; 754 struct cxl_memdev *cxlmd = cxlds->cxlmd; 755 int rc; 756 757 rc = cxl_mem_abort_fw_xfer(mds); 758 if (rc < 0) 759 dev_err(&cxlmd->dev, "Error aborting FW transfer: %d\n", rc); 760 761 return FW_UPLOAD_ERR_CANCELED; 762 } 763 764 static enum fw_upload_err cxl_fw_prepare(struct fw_upload *fwl, const u8 *data, 765 u32 size) 766 { 767 struct cxl_memdev_state *mds = fwl->dd_handle; 768 struct cxl_mbox_transfer_fw *transfer; 769 770 if (!size) 771 return FW_UPLOAD_ERR_INVALID_SIZE; 772 773 mds->fw.oneshot = struct_size(transfer, data, size) < 774 mds->payload_size; 775 776 if (cxl_mem_get_fw_info(mds)) 777 return FW_UPLOAD_ERR_HW_ERROR; 778 779 /* 780 * So far no state has been changed, hence no other cleanup is 781 * necessary. Simply return the cancelled status. 782 */ 783 if (test_and_clear_bit(CXL_FW_CANCEL, mds->fw.state)) 784 return FW_UPLOAD_ERR_CANCELED; 785 786 return FW_UPLOAD_ERR_NONE; 787 } 788 789 static enum fw_upload_err cxl_fw_write(struct fw_upload *fwl, const u8 *data, 790 u32 offset, u32 size, u32 *written) 791 { 792 struct cxl_memdev_state *mds = fwl->dd_handle; 793 struct cxl_dev_state *cxlds = &mds->cxlds; 794 struct cxl_memdev *cxlmd = cxlds->cxlmd; 795 struct cxl_mbox_transfer_fw *transfer; 796 struct cxl_mbox_cmd mbox_cmd; 797 u32 cur_size, remaining; 798 size_t size_in; 799 int rc; 800 801 *written = 0; 802 803 /* Offset has to be aligned to 128B (CXL-3.0 8.2.9.3.2 Table 8-57) */ 804 if (!IS_ALIGNED(offset, CXL_FW_TRANSFER_ALIGNMENT)) { 805 dev_err(&cxlmd->dev, 806 "misaligned offset for FW transfer slice (%u)\n", 807 offset); 808 return FW_UPLOAD_ERR_RW_ERROR; 809 } 810 811 /* 812 * Pick transfer size based on mds->payload_size @size must bw 128-byte 813 * aligned, ->payload_size is a power of 2 starting at 256 bytes, and 814 * sizeof(*transfer) is 128. These constraints imply that @cur_size 815 * will always be 128b aligned. 816 */ 817 cur_size = min_t(size_t, size, mds->payload_size - sizeof(*transfer)); 818 819 remaining = size - cur_size; 820 size_in = struct_size(transfer, data, cur_size); 821 822 if (test_and_clear_bit(CXL_FW_CANCEL, mds->fw.state)) 823 return cxl_fw_do_cancel(fwl); 824 825 /* 826 * Slot numbers are 1-indexed 827 * cur_slot is the 0-indexed next_slot (i.e. 'cur_slot - 1 + 1') 828 * Check for rollover using modulo, and 1-index it by adding 1 829 */ 830 mds->fw.next_slot = (mds->fw.cur_slot % mds->fw.num_slots) + 1; 831 832 /* Do the transfer via mailbox cmd */ 833 transfer = kzalloc(size_in, GFP_KERNEL); 834 if (!transfer) 835 return FW_UPLOAD_ERR_RW_ERROR; 836 837 transfer->offset = cpu_to_le32(offset / CXL_FW_TRANSFER_ALIGNMENT); 838 memcpy(transfer->data, data + offset, cur_size); 839 if (mds->fw.oneshot) { 840 transfer->action = CXL_FW_TRANSFER_ACTION_FULL; 841 transfer->slot = mds->fw.next_slot; 842 } else { 843 if (offset == 0) { 844 transfer->action = CXL_FW_TRANSFER_ACTION_INITIATE; 845 } else if (remaining == 0) { 846 transfer->action = CXL_FW_TRANSFER_ACTION_END; 847 transfer->slot = mds->fw.next_slot; 848 } else { 849 transfer->action = CXL_FW_TRANSFER_ACTION_CONTINUE; 850 } 851 } 852 853 mbox_cmd = (struct cxl_mbox_cmd) { 854 .opcode = CXL_MBOX_OP_TRANSFER_FW, 855 .size_in = size_in, 856 .payload_in = transfer, 857 .poll_interval_ms = 1000, 858 .poll_count = 30, 859 }; 860 861 rc = cxl_internal_send_cmd(mds, &mbox_cmd); 862 if (rc < 0) { 863 rc = FW_UPLOAD_ERR_RW_ERROR; 864 goto out_free; 865 } 866 867 *written = cur_size; 868 869 /* Activate FW if oneshot or if the last slice was written */ 870 if (mds->fw.oneshot || remaining == 0) { 871 dev_dbg(&cxlmd->dev, "Activating firmware slot: %d\n", 872 mds->fw.next_slot); 873 rc = cxl_mem_activate_fw(mds, mds->fw.next_slot); 874 if (rc < 0) { 875 dev_err(&cxlmd->dev, "Error activating firmware: %d\n", 876 rc); 877 rc = FW_UPLOAD_ERR_HW_ERROR; 878 goto out_free; 879 } 880 } 881 882 rc = FW_UPLOAD_ERR_NONE; 883 884 out_free: 885 kfree(transfer); 886 return rc; 887 } 888 889 static enum fw_upload_err cxl_fw_poll_complete(struct fw_upload *fwl) 890 { 891 struct cxl_memdev_state *mds = fwl->dd_handle; 892 893 /* 894 * cxl_internal_send_cmd() handles background operations synchronously. 895 * No need to wait for completions here - any errors would've been 896 * reported and handled during the ->write() call(s). 897 * Just check if a cancel request was received, and return success. 898 */ 899 if (test_and_clear_bit(CXL_FW_CANCEL, mds->fw.state)) 900 return cxl_fw_do_cancel(fwl); 901 902 return FW_UPLOAD_ERR_NONE; 903 } 904 905 static void cxl_fw_cancel(struct fw_upload *fwl) 906 { 907 struct cxl_memdev_state *mds = fwl->dd_handle; 908 909 set_bit(CXL_FW_CANCEL, mds->fw.state); 910 } 911 912 static const struct fw_upload_ops cxl_memdev_fw_ops = { 913 .prepare = cxl_fw_prepare, 914 .write = cxl_fw_write, 915 .poll_complete = cxl_fw_poll_complete, 916 .cancel = cxl_fw_cancel, 917 .cleanup = cxl_fw_cleanup, 918 }; 919 920 static void cxl_remove_fw_upload(void *fwl) 921 { 922 firmware_upload_unregister(fwl); 923 } 924 925 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds) 926 { 927 struct cxl_dev_state *cxlds = &mds->cxlds; 928 struct device *dev = &cxlds->cxlmd->dev; 929 struct fw_upload *fwl; 930 931 if (!test_bit(CXL_MEM_COMMAND_ID_GET_FW_INFO, mds->enabled_cmds)) 932 return 0; 933 934 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev), 935 &cxl_memdev_fw_ops, mds); 936 if (IS_ERR(fwl)) 937 return PTR_ERR(fwl); 938 return devm_add_action_or_reset(host, cxl_remove_fw_upload, fwl); 939 } 940 EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_fw_upload, CXL); 941 942 static const struct file_operations cxl_memdev_fops = { 943 .owner = THIS_MODULE, 944 .unlocked_ioctl = cxl_memdev_ioctl, 945 .open = cxl_memdev_open, 946 .release = cxl_memdev_release_file, 947 .compat_ioctl = compat_ptr_ioctl, 948 .llseek = noop_llseek, 949 }; 950 951 struct cxl_memdev *devm_cxl_add_memdev(struct device *host, 952 struct cxl_dev_state *cxlds) 953 { 954 struct cxl_memdev *cxlmd; 955 struct device *dev; 956 struct cdev *cdev; 957 int rc; 958 959 cxlmd = cxl_memdev_alloc(cxlds, &cxl_memdev_fops); 960 if (IS_ERR(cxlmd)) 961 return cxlmd; 962 963 dev = &cxlmd->dev; 964 rc = dev_set_name(dev, "mem%d", cxlmd->id); 965 if (rc) 966 goto err; 967 968 /* 969 * Activate ioctl operations, no cxl_memdev_rwsem manipulation 970 * needed as this is ordered with cdev_add() publishing the device. 971 */ 972 cxlmd->cxlds = cxlds; 973 cxlds->cxlmd = cxlmd; 974 975 cdev = &cxlmd->cdev; 976 rc = cdev_device_add(cdev, dev); 977 if (rc) 978 goto err; 979 980 rc = devm_add_action_or_reset(host, cxl_memdev_unregister, cxlmd); 981 if (rc) 982 return ERR_PTR(rc); 983 return cxlmd; 984 985 err: 986 /* 987 * The cdev was briefly live, shutdown any ioctl operations that 988 * saw that state. 989 */ 990 cxl_memdev_shutdown(dev); 991 put_device(dev); 992 return ERR_PTR(rc); 993 } 994 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL); 995 996 static void sanitize_teardown_notifier(void *data) 997 { 998 struct cxl_memdev_state *mds = data; 999 struct kernfs_node *state; 1000 1001 /* 1002 * Prevent new irq triggered invocations of the workqueue and 1003 * flush inflight invocations. 1004 */ 1005 mutex_lock(&mds->mbox_mutex); 1006 state = mds->security.sanitize_node; 1007 mds->security.sanitize_node = NULL; 1008 mutex_unlock(&mds->mbox_mutex); 1009 1010 cancel_delayed_work_sync(&mds->security.poll_dwork); 1011 sysfs_put(state); 1012 } 1013 1014 int devm_cxl_sanitize_setup_notifier(struct device *host, 1015 struct cxl_memdev *cxlmd) 1016 { 1017 struct cxl_dev_state *cxlds = cxlmd->cxlds; 1018 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 1019 struct kernfs_node *sec; 1020 1021 if (!test_bit(CXL_SEC_ENABLED_SANITIZE, mds->security.enabled_cmds)) 1022 return 0; 1023 1024 /* 1025 * Note, the expectation is that @cxlmd would have failed to be 1026 * created if these sysfs_get_dirent calls fail. 1027 */ 1028 sec = sysfs_get_dirent(cxlmd->dev.kobj.sd, "security"); 1029 if (!sec) 1030 return -ENOENT; 1031 mds->security.sanitize_node = sysfs_get_dirent(sec, "state"); 1032 sysfs_put(sec); 1033 if (!mds->security.sanitize_node) 1034 return -ENOENT; 1035 1036 return devm_add_action_or_reset(host, sanitize_teardown_notifier, mds); 1037 } 1038 EXPORT_SYMBOL_NS_GPL(devm_cxl_sanitize_setup_notifier, CXL); 1039 1040 __init int cxl_memdev_init(void) 1041 { 1042 dev_t devt; 1043 int rc; 1044 1045 rc = alloc_chrdev_region(&devt, 0, CXL_MEM_MAX_DEVS, "cxl"); 1046 if (rc) 1047 return rc; 1048 1049 cxl_mem_major = MAJOR(devt); 1050 1051 return 0; 1052 } 1053 1054 void cxl_memdev_exit(void) 1055 { 1056 unregister_chrdev_region(MKDEV(cxl_mem_major, 0), CXL_MEM_MAX_DEVS); 1057 } 1058