1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 help 6 CXL is a bus that is electrically compatible with PCI Express, but 7 layers three protocols on that signalling (CXL.io, CXL.cache, and 8 CXL.mem). The CXL.cache protocol allows devices to hold cachelines 9 locally, the CXL.mem protocol allows devices to be fully coherent 10 memory targets, the CXL.io protocol is equivalent to PCI Express. 11 Say 'y' to enable support for the configuration and management of 12 devices supporting these protocols. 13 14if CXL_BUS 15 16config CXL_PCI 17 tristate "PCI manageability" 18 default CXL_BUS 19 help 20 The CXL specification defines a "CXL memory device" sub-class in the 21 PCI "memory controller" base class of devices. Device's identified by 22 this class code provide support for volatile and / or persistent 23 memory to be mapped into the system address map (Host-managed Device 24 Memory (HDM)). 25 26 Say 'y/m' to enable a driver that will attach to CXL memory expander 27 devices enumerated by the memory device class code for configuration 28 and management primarily via the mailbox interface. See Chapter 2.3 29 Type 3 CXL Device in the CXL 2.0 specification for more details. 30 31 If unsure say 'm'. 32 33config CXL_MEM_RAW_COMMANDS 34 bool "RAW Command Interface for Memory Devices" 35 depends on CXL_PCI 36 help 37 Enable CXL RAW command interface. 38 39 The CXL driver ioctl interface may assign a kernel ioctl command 40 number for each specification defined opcode. At any given point in 41 time the number of opcodes that the specification defines and a device 42 may implement may exceed the kernel's set of associated ioctl function 43 numbers. The mismatch is either by omission, specification is too new, 44 or by design. When prototyping new hardware, or developing / debugging 45 the driver it is useful to be able to submit any possible command to 46 the hardware, even commands that may crash the kernel due to their 47 potential impact to memory currently in use by the kernel. 48 49 If developing CXL hardware or the driver say Y, otherwise say N. 50 51config CXL_ACPI 52 tristate "CXL ACPI: Platform Support" 53 depends on ACPI 54 default CXL_BUS 55 select ACPI_TABLE_LIB 56 help 57 Enable support for host managed device memory (HDM) resources 58 published by a platform's ACPI CXL memory layout description. See 59 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 60 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 61 (https://www.computeexpresslink.org/spec-landing). The CXL core 62 consumes these resource to publish the root of a cxl_port decode 63 hierarchy to map regions that represent System RAM, or Persistent 64 Memory regions to be managed by LIBNVDIMM. 65 66 If unsure say 'm'. 67 68config CXL_PMEM 69 tristate "CXL PMEM: Persistent Memory Support" 70 depends on LIBNVDIMM 71 default CXL_BUS 72 help 73 In addition to typical memory resources a platform may also advertise 74 support for persistent memory attached via CXL. This support is 75 managed via a bridge driver from CXL to the LIBNVDIMM system 76 subsystem. Say 'y/m' to enable support for enumerating and 77 provisioning the persistent memory capacity of CXL memory expanders. 78 79 If unsure say 'm'. 80 81config CXL_MEM 82 tristate "CXL: Memory Expansion" 83 depends on CXL_PCI 84 default CXL_BUS 85 help 86 The CXL.mem protocol allows a device to act as a provider of "System 87 RAM" and/or "Persistent Memory" that is fully coherent as if the 88 memory were attached to the typical CPU memory controller. This is 89 known as HDM "Host-managed Device Memory". 90 91 Say 'y/m' to enable a driver that will attach to CXL.mem devices for 92 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0 93 specification for a detailed description of HDM. 94 95 If unsure say 'm'. 96 97config CXL_PORT 98 default CXL_BUS 99 tristate 100 101endif 102