1 /* 2 * Freescale SEC (talitos) device register and descriptor header defines 3 * 4 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 #define TALITOS_TIMEOUT 100000 32 #define TALITOS1_MAX_DATA_LEN 32768 33 #define TALITOS2_MAX_DATA_LEN 65535 34 35 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f) 36 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf) 37 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf) 38 39 /* descriptor pointer entry */ 40 struct talitos_ptr { 41 union { 42 struct { /* SEC2 format */ 43 __be16 len; /* length */ 44 u8 j_extent; /* jump to sg link table and/or extent*/ 45 u8 eptr; /* extended address */ 46 }; 47 struct { /* SEC1 format */ 48 __be16 res; 49 __be16 len1; /* length */ 50 }; 51 }; 52 __be32 ptr; /* address */ 53 }; 54 55 /* descriptor */ 56 struct talitos_desc { 57 __be32 hdr; /* header high bits */ 58 union { 59 __be32 hdr_lo; /* header low bits */ 60 __be32 hdr1; /* header for SEC1 */ 61 }; 62 struct talitos_ptr ptr[7]; /* ptr/len pair array */ 63 __be32 next_desc; /* next descriptor (SEC1) */ 64 }; 65 66 #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32)) 67 68 /** 69 * talitos_request - descriptor submission request 70 * @desc: descriptor pointer (kernel virtual) 71 * @dma_desc: descriptor's physical bus address 72 * @callback: whom to call when descriptor processing is done 73 * @context: caller context (optional) 74 */ 75 struct talitos_request { 76 struct talitos_desc *desc; 77 dma_addr_t dma_desc; 78 void (*callback) (struct device *dev, struct talitos_desc *desc, 79 void *context, int error); 80 void *context; 81 }; 82 83 /* per-channel fifo management */ 84 struct talitos_channel { 85 void __iomem *reg; 86 87 /* request fifo */ 88 struct talitos_request *fifo; 89 90 /* number of requests pending in channel h/w fifo */ 91 atomic_t submit_count ____cacheline_aligned; 92 93 /* request submission (head) lock */ 94 spinlock_t head_lock ____cacheline_aligned; 95 /* index to next free descriptor request */ 96 int head; 97 98 /* request release (tail) lock */ 99 spinlock_t tail_lock ____cacheline_aligned; 100 /* index to next in-progress/done descriptor request */ 101 int tail; 102 }; 103 104 struct talitos_private { 105 struct device *dev; 106 struct platform_device *ofdev; 107 void __iomem *reg; 108 void __iomem *reg_deu; 109 void __iomem *reg_aesu; 110 void __iomem *reg_mdeu; 111 void __iomem *reg_afeu; 112 void __iomem *reg_rngu; 113 void __iomem *reg_pkeu; 114 void __iomem *reg_keu; 115 void __iomem *reg_crcu; 116 int irq[2]; 117 118 /* SEC global registers lock */ 119 spinlock_t reg_lock ____cacheline_aligned; 120 121 /* SEC version geometry (from device tree node) */ 122 unsigned int num_channels; 123 unsigned int chfifo_len; 124 unsigned int exec_units; 125 unsigned int desc_types; 126 127 /* SEC Compatibility info */ 128 unsigned long features; 129 130 /* 131 * length of the request fifo 132 * fifo_len is chfifo_len rounded up to next power of 2 133 * so we can use bitwise ops to wrap 134 */ 135 unsigned int fifo_len; 136 137 struct talitos_channel *chan; 138 139 /* next channel to be assigned next incoming descriptor */ 140 atomic_t last_chan ____cacheline_aligned; 141 142 /* request callback tasklet */ 143 struct tasklet_struct done_task[2]; 144 145 /* list of registered algorithms */ 146 struct list_head alg_list; 147 148 /* hwrng device */ 149 struct hwrng rng; 150 bool rng_registered; 151 }; 152 153 extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, 154 void (*callback)(struct device *dev, 155 struct talitos_desc *desc, 156 void *context, int error), 157 void *context); 158 159 /* .features flag */ 160 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001 161 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 162 #define TALITOS_FTR_SHA224_HWINIT 0x00000004 163 #define TALITOS_FTR_HMAC_OK 0x00000008 164 #define TALITOS_FTR_SEC1 0x00000010 165 166 /* 167 * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are 168 * defined, we check the features which are set according to the device tree. 169 * Otherwise, we answer true or false directly 170 */ 171 static inline bool has_ftr_sec1(struct talitos_private *priv) 172 { 173 #if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2) 174 return priv->features & TALITOS_FTR_SEC1 ? true : false; 175 #elif defined(CONFIG_CRYPTO_DEV_TALITOS1) 176 return true; 177 #else 178 return false; 179 #endif 180 } 181 182 /* 183 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register 184 */ 185 186 #define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16)) 187 #define ISR2_FORMAT(x) (((x) << 4) | (x)) 188 189 /* global register offset addresses */ 190 #define TALITOS_MCR 0x1030 /* master control register */ 191 #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */ 192 #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */ 193 #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */ 194 #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */ 195 #define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */ 196 #define TALITOS2_MCR_SWR 0x1 /* s/w reset */ 197 #define TALITOS_MCR_LO 0x1034 198 #define TALITOS_IMR 0x1008 /* interrupt mask register */ 199 /* enable channel IRQs */ 200 #define TALITOS1_IMR_INIT ISR1_FORMAT(0xf) 201 #define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */ 202 /* enable channel IRQs */ 203 #define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000) 204 #define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */ 205 #define TALITOS_IMR_LO 0x100C 206 #define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */ 207 #define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */ 208 #define TALITOS_ISR 0x1010 /* interrupt status register */ 209 #define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */ 210 #define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */ 211 #define TALITOS1_ISR_CH_0_ERR (2 << 28) /* ch 0 errors mask */ 212 #define TALITOS1_ISR_CH_0_DONE (1 << 28) /* ch 0 done mask */ 213 #define TALITOS1_ISR_TEA_ERR 0x00000040 214 #define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */ 215 #define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */ 216 #define TALITOS2_ISR_CH_0_ERR 2 /* ch 0 errors mask */ 217 #define TALITOS2_ISR_CH_0_DONE 1 /* ch 0 done mask */ 218 #define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */ 219 #define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */ 220 #define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */ 221 #define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */ 222 #define TALITOS_ISR_LO 0x1014 223 #define TALITOS_ICR 0x1018 /* interrupt clear register */ 224 #define TALITOS_ICR_LO 0x101C 225 226 /* channel register address stride */ 227 #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */ 228 #define TALITOS1_CH_STRIDE 0x1000 229 #define TALITOS2_CH_STRIDE 0x100 230 231 /* channel configuration register */ 232 #define TALITOS_CCCR 0x8 233 #define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */ 234 #define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */ 235 #define TALITOS_CCCR_LO 0xc 236 #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */ 237 #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */ 238 #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */ 239 #define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */ 240 #define TALITOS_CCCR_LO_NT 0x4 /* notification type */ 241 #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */ 242 #define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */ 243 244 /* CCPSR: channel pointer status register */ 245 #define TALITOS_CCPSR 0x10 246 #define TALITOS_CCPSR_LO 0x14 247 #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */ 248 #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */ 249 #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */ 250 #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */ 251 #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */ 252 #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */ 253 #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */ 254 #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */ 255 #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */ 256 #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */ 257 #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */ 258 #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */ 259 260 /* channel fetch fifo register */ 261 #define TALITOS_FF 0x48 262 #define TALITOS_FF_LO 0x4c 263 264 /* current descriptor pointer register */ 265 #define TALITOS_CDPR 0x40 266 #define TALITOS_CDPR_LO 0x44 267 268 /* descriptor buffer register */ 269 #define TALITOS_DESCBUF 0x80 270 #define TALITOS_DESCBUF_LO 0x84 271 272 /* gather link table */ 273 #define TALITOS_GATHER 0xc0 274 #define TALITOS_GATHER_LO 0xc4 275 276 /* scatter link table */ 277 #define TALITOS_SCATTER 0xe0 278 #define TALITOS_SCATTER_LO 0xe4 279 280 /* execution unit registers base */ 281 #define TALITOS2_DEU 0x2000 282 #define TALITOS2_AESU 0x4000 283 #define TALITOS2_MDEU 0x6000 284 #define TALITOS2_AFEU 0x8000 285 #define TALITOS2_RNGU 0xa000 286 #define TALITOS2_PKEU 0xc000 287 #define TALITOS2_KEU 0xe000 288 #define TALITOS2_CRCU 0xf000 289 290 #define TALITOS12_AESU 0x4000 291 #define TALITOS12_DEU 0x5000 292 #define TALITOS12_MDEU 0x6000 293 294 #define TALITOS10_AFEU 0x8000 295 #define TALITOS10_DEU 0xa000 296 #define TALITOS10_MDEU 0xc000 297 #define TALITOS10_RNGU 0xe000 298 #define TALITOS10_PKEU 0x10000 299 #define TALITOS10_AESU 0x12000 300 301 /* execution unit interrupt status registers */ 302 #define TALITOS_EUDSR 0x10 /* data size */ 303 #define TALITOS_EUDSR_LO 0x14 304 #define TALITOS_EURCR 0x18 /* reset control*/ 305 #define TALITOS_EURCR_LO 0x1c 306 #define TALITOS_EUSR 0x28 /* rng status */ 307 #define TALITOS_EUSR_LO 0x2c 308 #define TALITOS_EUISR 0x30 309 #define TALITOS_EUISR_LO 0x34 310 #define TALITOS_EUICR 0x38 /* int. control */ 311 #define TALITOS_EUICR_LO 0x3c 312 #define TALITOS_EU_FIFO 0x800 /* output FIFO */ 313 #define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */ 314 /* DES unit */ 315 #define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */ 316 /* message digest unit */ 317 #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */ 318 /* random number unit */ 319 #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */ 320 #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */ 321 #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */ 322 323 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28 324 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48 325 326 /* 327 * talitos descriptor header (hdr) bits 328 */ 329 330 /* written back when done */ 331 #define DESC_HDR_DONE cpu_to_be32(0xff000000) 332 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000) 333 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000) 334 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000) 335 336 /* primary execution unit select */ 337 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000) 338 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000) 339 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000) 340 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000) 341 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000) 342 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000) 343 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000) 344 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000) 345 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000) 346 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000) 347 348 /* primary execution unit mode (MODE0) and derivatives */ 349 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000) 350 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000) 351 #define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000) 352 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000) 353 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000) 354 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000) 355 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000) 356 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000) 357 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000) 358 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000) 359 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000) 360 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000) 361 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000) 362 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000) 363 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000) 364 #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \ 365 DESC_HDR_MODE0_MDEU_HMAC) 366 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \ 367 DESC_HDR_MODE0_MDEU_HMAC) 368 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \ 369 DESC_HDR_MODE0_MDEU_HMAC) 370 371 /* secondary execution unit select (SEL1) */ 372 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000) 373 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000) 374 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000) 375 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000) 376 377 /* secondary execution unit mode (MODE1) and derivatives */ 378 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000) 379 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000) 380 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800) 381 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400) 382 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300) 383 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200) 384 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100) 385 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000) 386 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000) 387 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200) 388 #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \ 389 DESC_HDR_MODE1_MDEU_HMAC) 390 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \ 391 DESC_HDR_MODE1_MDEU_HMAC) 392 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \ 393 DESC_HDR_MODE1_MDEU_HMAC) 394 #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \ 395 DESC_HDR_MODE1_MDEU_HMAC) 396 #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \ 397 DESC_HDR_MODE1_MDEU_HMAC) 398 #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \ 399 DESC_HDR_MODE1_MDEU_HMAC) 400 401 /* direction of overall data flow (DIR) */ 402 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002) 403 404 /* request done notification (DN) */ 405 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001) 406 407 /* descriptor types */ 408 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3) 409 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3) 410 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3) 411 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3) 412 413 /* link table extent field bits */ 414 #define DESC_PTR_LNKTBL_JUMP 0x80 415 #define DESC_PTR_LNKTBL_RETURN 0x02 416 #define DESC_PTR_LNKTBL_NEXT 0x01 417