1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This file is part of STM32 Crypto driver for Linux. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/crypto.h> 11 #include <linux/delay.h> 12 #include <linux/dmaengine.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <crypto/engine.h> 24 #include <crypto/hash.h> 25 #include <crypto/md5.h> 26 #include <crypto/scatterwalk.h> 27 #include <crypto/sha.h> 28 #include <crypto/internal/hash.h> 29 30 #define HASH_CR 0x00 31 #define HASH_DIN 0x04 32 #define HASH_STR 0x08 33 #define HASH_IMR 0x20 34 #define HASH_SR 0x24 35 #define HASH_CSR(x) (0x0F8 + ((x) * 0x04)) 36 #define HASH_HREG(x) (0x310 + ((x) * 0x04)) 37 #define HASH_HWCFGR 0x3F0 38 #define HASH_VER 0x3F4 39 #define HASH_ID 0x3F8 40 41 /* Control Register */ 42 #define HASH_CR_INIT BIT(2) 43 #define HASH_CR_DMAE BIT(3) 44 #define HASH_CR_DATATYPE_POS 4 45 #define HASH_CR_MODE BIT(6) 46 #define HASH_CR_MDMAT BIT(13) 47 #define HASH_CR_DMAA BIT(14) 48 #define HASH_CR_LKEY BIT(16) 49 50 #define HASH_CR_ALGO_SHA1 0x0 51 #define HASH_CR_ALGO_MD5 0x80 52 #define HASH_CR_ALGO_SHA224 0x40000 53 #define HASH_CR_ALGO_SHA256 0x40080 54 55 /* Interrupt */ 56 #define HASH_DINIE BIT(0) 57 #define HASH_DCIE BIT(1) 58 59 /* Interrupt Mask */ 60 #define HASH_MASK_CALC_COMPLETION BIT(0) 61 #define HASH_MASK_DATA_INPUT BIT(1) 62 63 /* Context swap register */ 64 #define HASH_CSR_REGISTER_NUMBER 53 65 66 /* Status Flags */ 67 #define HASH_SR_DATA_INPUT_READY BIT(0) 68 #define HASH_SR_OUTPUT_READY BIT(1) 69 #define HASH_SR_DMA_ACTIVE BIT(2) 70 #define HASH_SR_BUSY BIT(3) 71 72 /* STR Register */ 73 #define HASH_STR_NBLW_MASK GENMASK(4, 0) 74 #define HASH_STR_DCAL BIT(8) 75 76 #define HASH_FLAGS_INIT BIT(0) 77 #define HASH_FLAGS_OUTPUT_READY BIT(1) 78 #define HASH_FLAGS_CPU BIT(2) 79 #define HASH_FLAGS_DMA_READY BIT(3) 80 #define HASH_FLAGS_DMA_ACTIVE BIT(4) 81 #define HASH_FLAGS_HMAC_INIT BIT(5) 82 #define HASH_FLAGS_HMAC_FINAL BIT(6) 83 #define HASH_FLAGS_HMAC_KEY BIT(7) 84 85 #define HASH_FLAGS_FINAL BIT(15) 86 #define HASH_FLAGS_FINUP BIT(16) 87 #define HASH_FLAGS_ALGO_MASK GENMASK(21, 18) 88 #define HASH_FLAGS_MD5 BIT(18) 89 #define HASH_FLAGS_SHA1 BIT(19) 90 #define HASH_FLAGS_SHA224 BIT(20) 91 #define HASH_FLAGS_SHA256 BIT(21) 92 #define HASH_FLAGS_ERRORS BIT(22) 93 #define HASH_FLAGS_HMAC BIT(23) 94 95 #define HASH_OP_UPDATE 1 96 #define HASH_OP_FINAL 2 97 98 enum stm32_hash_data_format { 99 HASH_DATA_32_BITS = 0x0, 100 HASH_DATA_16_BITS = 0x1, 101 HASH_DATA_8_BITS = 0x2, 102 HASH_DATA_1_BIT = 0x3 103 }; 104 105 #define HASH_BUFLEN 256 106 #define HASH_LONG_KEY 64 107 #define HASH_MAX_KEY_SIZE (SHA256_BLOCK_SIZE * 8) 108 #define HASH_QUEUE_LENGTH 16 109 #define HASH_DMA_THRESHOLD 50 110 111 #define HASH_AUTOSUSPEND_DELAY 50 112 113 struct stm32_hash_ctx { 114 struct crypto_engine_ctx enginectx; 115 struct stm32_hash_dev *hdev; 116 unsigned long flags; 117 118 u8 key[HASH_MAX_KEY_SIZE]; 119 int keylen; 120 }; 121 122 struct stm32_hash_request_ctx { 123 struct stm32_hash_dev *hdev; 124 unsigned long flags; 125 unsigned long op; 126 127 u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32)); 128 size_t digcnt; 129 size_t bufcnt; 130 size_t buflen; 131 132 /* DMA */ 133 struct scatterlist *sg; 134 unsigned int offset; 135 unsigned int total; 136 struct scatterlist sg_key; 137 138 dma_addr_t dma_addr; 139 size_t dma_ct; 140 int nents; 141 142 u8 data_type; 143 144 u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32)); 145 146 /* Export Context */ 147 u32 *hw_context; 148 }; 149 150 struct stm32_hash_algs_info { 151 struct ahash_alg *algs_list; 152 size_t size; 153 }; 154 155 struct stm32_hash_pdata { 156 struct stm32_hash_algs_info *algs_info; 157 size_t algs_info_size; 158 }; 159 160 struct stm32_hash_dev { 161 struct list_head list; 162 struct device *dev; 163 struct clk *clk; 164 struct reset_control *rst; 165 void __iomem *io_base; 166 phys_addr_t phys_base; 167 u32 dma_mode; 168 u32 dma_maxburst; 169 170 struct ahash_request *req; 171 struct crypto_engine *engine; 172 173 int err; 174 unsigned long flags; 175 176 struct dma_chan *dma_lch; 177 struct completion dma_completion; 178 179 const struct stm32_hash_pdata *pdata; 180 }; 181 182 struct stm32_hash_drv { 183 struct list_head dev_list; 184 spinlock_t lock; /* List protection access */ 185 }; 186 187 static struct stm32_hash_drv stm32_hash = { 188 .dev_list = LIST_HEAD_INIT(stm32_hash.dev_list), 189 .lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock), 190 }; 191 192 static void stm32_hash_dma_callback(void *param); 193 194 static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset) 195 { 196 return readl_relaxed(hdev->io_base + offset); 197 } 198 199 static inline void stm32_hash_write(struct stm32_hash_dev *hdev, 200 u32 offset, u32 value) 201 { 202 writel_relaxed(value, hdev->io_base + offset); 203 } 204 205 static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev) 206 { 207 u32 status; 208 209 return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status, 210 !(status & HASH_SR_BUSY), 10, 10000); 211 } 212 213 static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length) 214 { 215 u32 reg; 216 217 reg = stm32_hash_read(hdev, HASH_STR); 218 reg &= ~(HASH_STR_NBLW_MASK); 219 reg |= (8U * ((length) % 4U)); 220 stm32_hash_write(hdev, HASH_STR, reg); 221 } 222 223 static int stm32_hash_write_key(struct stm32_hash_dev *hdev) 224 { 225 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req); 226 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); 227 u32 reg; 228 int keylen = ctx->keylen; 229 void *key = ctx->key; 230 231 if (keylen) { 232 stm32_hash_set_nblw(hdev, keylen); 233 234 while (keylen > 0) { 235 stm32_hash_write(hdev, HASH_DIN, *(u32 *)key); 236 keylen -= 4; 237 key += 4; 238 } 239 240 reg = stm32_hash_read(hdev, HASH_STR); 241 reg |= HASH_STR_DCAL; 242 stm32_hash_write(hdev, HASH_STR, reg); 243 244 return -EINPROGRESS; 245 } 246 247 return 0; 248 } 249 250 static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev) 251 { 252 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req); 253 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req); 254 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); 255 256 u32 reg = HASH_CR_INIT; 257 258 if (!(hdev->flags & HASH_FLAGS_INIT)) { 259 switch (rctx->flags & HASH_FLAGS_ALGO_MASK) { 260 case HASH_FLAGS_MD5: 261 reg |= HASH_CR_ALGO_MD5; 262 break; 263 case HASH_FLAGS_SHA1: 264 reg |= HASH_CR_ALGO_SHA1; 265 break; 266 case HASH_FLAGS_SHA224: 267 reg |= HASH_CR_ALGO_SHA224; 268 break; 269 case HASH_FLAGS_SHA256: 270 reg |= HASH_CR_ALGO_SHA256; 271 break; 272 default: 273 reg |= HASH_CR_ALGO_MD5; 274 } 275 276 reg |= (rctx->data_type << HASH_CR_DATATYPE_POS); 277 278 if (rctx->flags & HASH_FLAGS_HMAC) { 279 hdev->flags |= HASH_FLAGS_HMAC; 280 reg |= HASH_CR_MODE; 281 if (ctx->keylen > HASH_LONG_KEY) 282 reg |= HASH_CR_LKEY; 283 } 284 285 stm32_hash_write(hdev, HASH_IMR, HASH_DCIE); 286 287 stm32_hash_write(hdev, HASH_CR, reg); 288 289 hdev->flags |= HASH_FLAGS_INIT; 290 291 dev_dbg(hdev->dev, "Write Control %x\n", reg); 292 } 293 } 294 295 static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx) 296 { 297 size_t count; 298 299 while ((rctx->bufcnt < rctx->buflen) && rctx->total) { 300 count = min(rctx->sg->length - rctx->offset, rctx->total); 301 count = min(count, rctx->buflen - rctx->bufcnt); 302 303 if (count <= 0) { 304 if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) { 305 rctx->sg = sg_next(rctx->sg); 306 continue; 307 } else { 308 break; 309 } 310 } 311 312 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg, 313 rctx->offset, count, 0); 314 315 rctx->bufcnt += count; 316 rctx->offset += count; 317 rctx->total -= count; 318 319 if (rctx->offset == rctx->sg->length) { 320 rctx->sg = sg_next(rctx->sg); 321 if (rctx->sg) 322 rctx->offset = 0; 323 else 324 rctx->total = 0; 325 } 326 } 327 } 328 329 static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev, 330 const u8 *buf, size_t length, int final) 331 { 332 unsigned int count, len32; 333 const u32 *buffer = (const u32 *)buf; 334 u32 reg; 335 336 if (final) 337 hdev->flags |= HASH_FLAGS_FINAL; 338 339 len32 = DIV_ROUND_UP(length, sizeof(u32)); 340 341 dev_dbg(hdev->dev, "%s: length: %d, final: %x len32 %i\n", 342 __func__, length, final, len32); 343 344 hdev->flags |= HASH_FLAGS_CPU; 345 346 stm32_hash_write_ctrl(hdev); 347 348 if (stm32_hash_wait_busy(hdev)) 349 return -ETIMEDOUT; 350 351 if ((hdev->flags & HASH_FLAGS_HMAC) && 352 (hdev->flags & ~HASH_FLAGS_HMAC_KEY)) { 353 hdev->flags |= HASH_FLAGS_HMAC_KEY; 354 stm32_hash_write_key(hdev); 355 if (stm32_hash_wait_busy(hdev)) 356 return -ETIMEDOUT; 357 } 358 359 for (count = 0; count < len32; count++) 360 stm32_hash_write(hdev, HASH_DIN, buffer[count]); 361 362 if (final) { 363 stm32_hash_set_nblw(hdev, length); 364 reg = stm32_hash_read(hdev, HASH_STR); 365 reg |= HASH_STR_DCAL; 366 stm32_hash_write(hdev, HASH_STR, reg); 367 if (hdev->flags & HASH_FLAGS_HMAC) { 368 if (stm32_hash_wait_busy(hdev)) 369 return -ETIMEDOUT; 370 stm32_hash_write_key(hdev); 371 } 372 return -EINPROGRESS; 373 } 374 375 return 0; 376 } 377 378 static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev) 379 { 380 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req); 381 int bufcnt, err = 0, final; 382 383 dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags); 384 385 final = (rctx->flags & HASH_FLAGS_FINUP); 386 387 while ((rctx->total >= rctx->buflen) || 388 (rctx->bufcnt + rctx->total >= rctx->buflen)) { 389 stm32_hash_append_sg(rctx); 390 bufcnt = rctx->bufcnt; 391 rctx->bufcnt = 0; 392 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0); 393 } 394 395 stm32_hash_append_sg(rctx); 396 397 if (final) { 398 bufcnt = rctx->bufcnt; 399 rctx->bufcnt = 0; 400 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 401 (rctx->flags & HASH_FLAGS_FINUP)); 402 } 403 404 return err; 405 } 406 407 static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev, 408 struct scatterlist *sg, int length, int mdma) 409 { 410 struct dma_async_tx_descriptor *in_desc; 411 dma_cookie_t cookie; 412 u32 reg; 413 int err; 414 415 in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1, 416 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | 417 DMA_CTRL_ACK); 418 if (!in_desc) { 419 dev_err(hdev->dev, "dmaengine_prep_slave error\n"); 420 return -ENOMEM; 421 } 422 423 reinit_completion(&hdev->dma_completion); 424 in_desc->callback = stm32_hash_dma_callback; 425 in_desc->callback_param = hdev; 426 427 hdev->flags |= HASH_FLAGS_FINAL; 428 hdev->flags |= HASH_FLAGS_DMA_ACTIVE; 429 430 reg = stm32_hash_read(hdev, HASH_CR); 431 432 if (mdma) 433 reg |= HASH_CR_MDMAT; 434 else 435 reg &= ~HASH_CR_MDMAT; 436 437 reg |= HASH_CR_DMAE; 438 439 stm32_hash_write(hdev, HASH_CR, reg); 440 441 stm32_hash_set_nblw(hdev, length); 442 443 cookie = dmaengine_submit(in_desc); 444 err = dma_submit_error(cookie); 445 if (err) 446 return -ENOMEM; 447 448 dma_async_issue_pending(hdev->dma_lch); 449 450 if (!wait_for_completion_interruptible_timeout(&hdev->dma_completion, 451 msecs_to_jiffies(100))) 452 err = -ETIMEDOUT; 453 454 if (dma_async_is_tx_complete(hdev->dma_lch, cookie, 455 NULL, NULL) != DMA_COMPLETE) 456 err = -ETIMEDOUT; 457 458 if (err) { 459 dev_err(hdev->dev, "DMA Error %i\n", err); 460 dmaengine_terminate_all(hdev->dma_lch); 461 return err; 462 } 463 464 return -EINPROGRESS; 465 } 466 467 static void stm32_hash_dma_callback(void *param) 468 { 469 struct stm32_hash_dev *hdev = param; 470 471 complete(&hdev->dma_completion); 472 473 hdev->flags |= HASH_FLAGS_DMA_READY; 474 } 475 476 static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev) 477 { 478 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req); 479 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req); 480 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); 481 int err; 482 483 if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) { 484 err = stm32_hash_write_key(hdev); 485 if (stm32_hash_wait_busy(hdev)) 486 return -ETIMEDOUT; 487 } else { 488 if (!(hdev->flags & HASH_FLAGS_HMAC_KEY)) 489 sg_init_one(&rctx->sg_key, ctx->key, 490 ALIGN(ctx->keylen, sizeof(u32))); 491 492 rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1, 493 DMA_TO_DEVICE); 494 if (rctx->dma_ct == 0) { 495 dev_err(hdev->dev, "dma_map_sg error\n"); 496 return -ENOMEM; 497 } 498 499 err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0); 500 501 dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE); 502 } 503 504 return err; 505 } 506 507 static int stm32_hash_dma_init(struct stm32_hash_dev *hdev) 508 { 509 struct dma_slave_config dma_conf; 510 int err; 511 512 memset(&dma_conf, 0, sizeof(dma_conf)); 513 514 dma_conf.direction = DMA_MEM_TO_DEV; 515 dma_conf.dst_addr = hdev->phys_base + HASH_DIN; 516 dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 517 dma_conf.src_maxburst = hdev->dma_maxburst; 518 dma_conf.dst_maxburst = hdev->dma_maxburst; 519 dma_conf.device_fc = false; 520 521 hdev->dma_lch = dma_request_slave_channel(hdev->dev, "in"); 522 if (!hdev->dma_lch) { 523 dev_err(hdev->dev, "Couldn't acquire a slave DMA channel.\n"); 524 return -EBUSY; 525 } 526 527 err = dmaengine_slave_config(hdev->dma_lch, &dma_conf); 528 if (err) { 529 dma_release_channel(hdev->dma_lch); 530 hdev->dma_lch = NULL; 531 dev_err(hdev->dev, "Couldn't configure DMA slave.\n"); 532 return err; 533 } 534 535 init_completion(&hdev->dma_completion); 536 537 return 0; 538 } 539 540 static int stm32_hash_dma_send(struct stm32_hash_dev *hdev) 541 { 542 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req); 543 struct scatterlist sg[1], *tsg; 544 int err = 0, len = 0, reg, ncp = 0; 545 unsigned int i; 546 u32 *buffer = (void *)rctx->buffer; 547 548 rctx->sg = hdev->req->src; 549 rctx->total = hdev->req->nbytes; 550 551 rctx->nents = sg_nents(rctx->sg); 552 553 if (rctx->nents < 0) 554 return -EINVAL; 555 556 stm32_hash_write_ctrl(hdev); 557 558 if (hdev->flags & HASH_FLAGS_HMAC) { 559 err = stm32_hash_hmac_dma_send(hdev); 560 if (err != -EINPROGRESS) 561 return err; 562 } 563 564 for_each_sg(rctx->sg, tsg, rctx->nents, i) { 565 len = sg->length; 566 567 sg[0] = *tsg; 568 if (sg_is_last(sg)) { 569 if (hdev->dma_mode == 1) { 570 len = (ALIGN(sg->length, 16) - 16); 571 572 ncp = sg_pcopy_to_buffer( 573 rctx->sg, rctx->nents, 574 rctx->buffer, sg->length - len, 575 rctx->total - sg->length + len); 576 577 sg->length = len; 578 } else { 579 if (!(IS_ALIGNED(sg->length, sizeof(u32)))) { 580 len = sg->length; 581 sg->length = ALIGN(sg->length, 582 sizeof(u32)); 583 } 584 } 585 } 586 587 rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1, 588 DMA_TO_DEVICE); 589 if (rctx->dma_ct == 0) { 590 dev_err(hdev->dev, "dma_map_sg error\n"); 591 return -ENOMEM; 592 } 593 594 err = stm32_hash_xmit_dma(hdev, sg, len, 595 !sg_is_last(sg)); 596 597 dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE); 598 599 if (err == -ENOMEM) 600 return err; 601 } 602 603 if (hdev->dma_mode == 1) { 604 if (stm32_hash_wait_busy(hdev)) 605 return -ETIMEDOUT; 606 reg = stm32_hash_read(hdev, HASH_CR); 607 reg &= ~HASH_CR_DMAE; 608 reg |= HASH_CR_DMAA; 609 stm32_hash_write(hdev, HASH_CR, reg); 610 611 if (ncp) { 612 memset(buffer + ncp, 0, 613 DIV_ROUND_UP(ncp, sizeof(u32)) - ncp); 614 writesl(hdev->io_base + HASH_DIN, buffer, 615 DIV_ROUND_UP(ncp, sizeof(u32))); 616 } 617 stm32_hash_set_nblw(hdev, ncp); 618 reg = stm32_hash_read(hdev, HASH_STR); 619 reg |= HASH_STR_DCAL; 620 stm32_hash_write(hdev, HASH_STR, reg); 621 err = -EINPROGRESS; 622 } 623 624 if (hdev->flags & HASH_FLAGS_HMAC) { 625 if (stm32_hash_wait_busy(hdev)) 626 return -ETIMEDOUT; 627 err = stm32_hash_hmac_dma_send(hdev); 628 } 629 630 return err; 631 } 632 633 static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx) 634 { 635 struct stm32_hash_dev *hdev = NULL, *tmp; 636 637 spin_lock_bh(&stm32_hash.lock); 638 if (!ctx->hdev) { 639 list_for_each_entry(tmp, &stm32_hash.dev_list, list) { 640 hdev = tmp; 641 break; 642 } 643 ctx->hdev = hdev; 644 } else { 645 hdev = ctx->hdev; 646 } 647 648 spin_unlock_bh(&stm32_hash.lock); 649 650 return hdev; 651 } 652 653 static bool stm32_hash_dma_aligned_data(struct ahash_request *req) 654 { 655 struct scatterlist *sg; 656 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 657 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 658 int i; 659 660 if (req->nbytes <= HASH_DMA_THRESHOLD) 661 return false; 662 663 if (sg_nents(req->src) > 1) { 664 if (hdev->dma_mode == 1) 665 return false; 666 for_each_sg(req->src, sg, sg_nents(req->src), i) { 667 if ((!IS_ALIGNED(sg->length, sizeof(u32))) && 668 (!sg_is_last(sg))) 669 return false; 670 } 671 } 672 673 if (req->src->offset % 4) 674 return false; 675 676 return true; 677 } 678 679 static int stm32_hash_init(struct ahash_request *req) 680 { 681 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 682 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); 683 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 684 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 685 686 rctx->hdev = hdev; 687 688 rctx->flags = HASH_FLAGS_CPU; 689 690 rctx->digcnt = crypto_ahash_digestsize(tfm); 691 switch (rctx->digcnt) { 692 case MD5_DIGEST_SIZE: 693 rctx->flags |= HASH_FLAGS_MD5; 694 break; 695 case SHA1_DIGEST_SIZE: 696 rctx->flags |= HASH_FLAGS_SHA1; 697 break; 698 case SHA224_DIGEST_SIZE: 699 rctx->flags |= HASH_FLAGS_SHA224; 700 break; 701 case SHA256_DIGEST_SIZE: 702 rctx->flags |= HASH_FLAGS_SHA256; 703 break; 704 default: 705 return -EINVAL; 706 } 707 708 rctx->bufcnt = 0; 709 rctx->buflen = HASH_BUFLEN; 710 rctx->total = 0; 711 rctx->offset = 0; 712 rctx->data_type = HASH_DATA_8_BITS; 713 714 memset(rctx->buffer, 0, HASH_BUFLEN); 715 716 if (ctx->flags & HASH_FLAGS_HMAC) 717 rctx->flags |= HASH_FLAGS_HMAC; 718 719 dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags); 720 721 return 0; 722 } 723 724 static int stm32_hash_update_req(struct stm32_hash_dev *hdev) 725 { 726 return stm32_hash_update_cpu(hdev); 727 } 728 729 static int stm32_hash_final_req(struct stm32_hash_dev *hdev) 730 { 731 struct ahash_request *req = hdev->req; 732 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 733 int err; 734 int buflen = rctx->bufcnt; 735 736 rctx->bufcnt = 0; 737 738 if (!(rctx->flags & HASH_FLAGS_CPU)) 739 err = stm32_hash_dma_send(hdev); 740 else 741 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1); 742 743 744 return err; 745 } 746 747 static void stm32_hash_copy_hash(struct ahash_request *req) 748 { 749 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 750 u32 *hash = (u32 *)rctx->digest; 751 unsigned int i, hashsize; 752 753 switch (rctx->flags & HASH_FLAGS_ALGO_MASK) { 754 case HASH_FLAGS_MD5: 755 hashsize = MD5_DIGEST_SIZE; 756 break; 757 case HASH_FLAGS_SHA1: 758 hashsize = SHA1_DIGEST_SIZE; 759 break; 760 case HASH_FLAGS_SHA224: 761 hashsize = SHA224_DIGEST_SIZE; 762 break; 763 case HASH_FLAGS_SHA256: 764 hashsize = SHA256_DIGEST_SIZE; 765 break; 766 default: 767 return; 768 } 769 770 for (i = 0; i < hashsize / sizeof(u32); i++) 771 hash[i] = be32_to_cpu(stm32_hash_read(rctx->hdev, 772 HASH_HREG(i))); 773 } 774 775 static int stm32_hash_finish(struct ahash_request *req) 776 { 777 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 778 779 if (!req->result) 780 return -EINVAL; 781 782 memcpy(req->result, rctx->digest, rctx->digcnt); 783 784 return 0; 785 } 786 787 static void stm32_hash_finish_req(struct ahash_request *req, int err) 788 { 789 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 790 struct stm32_hash_dev *hdev = rctx->hdev; 791 792 if (!err && (HASH_FLAGS_FINAL & hdev->flags)) { 793 stm32_hash_copy_hash(req); 794 err = stm32_hash_finish(req); 795 hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU | 796 HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY | 797 HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC | 798 HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL | 799 HASH_FLAGS_HMAC_KEY); 800 } else { 801 rctx->flags |= HASH_FLAGS_ERRORS; 802 } 803 804 pm_runtime_mark_last_busy(hdev->dev); 805 pm_runtime_put_autosuspend(hdev->dev); 806 807 crypto_finalize_hash_request(hdev->engine, req, err); 808 } 809 810 static int stm32_hash_hw_init(struct stm32_hash_dev *hdev, 811 struct stm32_hash_request_ctx *rctx) 812 { 813 pm_runtime_get_sync(hdev->dev); 814 815 if (!(HASH_FLAGS_INIT & hdev->flags)) { 816 stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT); 817 stm32_hash_write(hdev, HASH_STR, 0); 818 stm32_hash_write(hdev, HASH_DIN, 0); 819 stm32_hash_write(hdev, HASH_IMR, 0); 820 hdev->err = 0; 821 } 822 823 return 0; 824 } 825 826 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq); 827 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq); 828 829 static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev, 830 struct ahash_request *req) 831 { 832 return crypto_transfer_hash_request_to_engine(hdev->engine, req); 833 } 834 835 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq) 836 { 837 struct ahash_request *req = container_of(areq, struct ahash_request, 838 base); 839 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 840 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 841 struct stm32_hash_request_ctx *rctx; 842 843 if (!hdev) 844 return -ENODEV; 845 846 hdev->req = req; 847 848 rctx = ahash_request_ctx(req); 849 850 dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n", 851 rctx->op, req->nbytes); 852 853 return stm32_hash_hw_init(hdev, rctx); 854 } 855 856 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq) 857 { 858 struct ahash_request *req = container_of(areq, struct ahash_request, 859 base); 860 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 861 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 862 struct stm32_hash_request_ctx *rctx; 863 int err = 0; 864 865 if (!hdev) 866 return -ENODEV; 867 868 hdev->req = req; 869 870 rctx = ahash_request_ctx(req); 871 872 if (rctx->op == HASH_OP_UPDATE) 873 err = stm32_hash_update_req(hdev); 874 else if (rctx->op == HASH_OP_FINAL) 875 err = stm32_hash_final_req(hdev); 876 877 if (err != -EINPROGRESS) 878 /* done task will not finish it, so do it here */ 879 stm32_hash_finish_req(req, err); 880 881 return 0; 882 } 883 884 static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op) 885 { 886 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 887 struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm); 888 struct stm32_hash_dev *hdev = ctx->hdev; 889 890 rctx->op = op; 891 892 return stm32_hash_handle_queue(hdev, req); 893 } 894 895 static int stm32_hash_update(struct ahash_request *req) 896 { 897 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 898 899 if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU)) 900 return 0; 901 902 rctx->total = req->nbytes; 903 rctx->sg = req->src; 904 rctx->offset = 0; 905 906 if ((rctx->bufcnt + rctx->total < rctx->buflen)) { 907 stm32_hash_append_sg(rctx); 908 return 0; 909 } 910 911 return stm32_hash_enqueue(req, HASH_OP_UPDATE); 912 } 913 914 static int stm32_hash_final(struct ahash_request *req) 915 { 916 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 917 918 rctx->flags |= HASH_FLAGS_FINUP; 919 920 return stm32_hash_enqueue(req, HASH_OP_FINAL); 921 } 922 923 static int stm32_hash_finup(struct ahash_request *req) 924 { 925 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 926 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 927 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 928 int err1, err2; 929 930 rctx->flags |= HASH_FLAGS_FINUP; 931 932 if (hdev->dma_lch && stm32_hash_dma_aligned_data(req)) 933 rctx->flags &= ~HASH_FLAGS_CPU; 934 935 err1 = stm32_hash_update(req); 936 937 if (err1 == -EINPROGRESS || err1 == -EBUSY) 938 return err1; 939 940 /* 941 * final() has to be always called to cleanup resources 942 * even if update() failed, except EINPROGRESS 943 */ 944 err2 = stm32_hash_final(req); 945 946 return err1 ?: err2; 947 } 948 949 static int stm32_hash_digest(struct ahash_request *req) 950 { 951 return stm32_hash_init(req) ?: stm32_hash_finup(req); 952 } 953 954 static int stm32_hash_export(struct ahash_request *req, void *out) 955 { 956 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 957 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 958 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 959 u32 *preg; 960 unsigned int i; 961 962 pm_runtime_get_sync(hdev->dev); 963 964 while ((stm32_hash_read(hdev, HASH_SR) & HASH_SR_BUSY)) 965 cpu_relax(); 966 967 rctx->hw_context = kmalloc_array(3 + HASH_CSR_REGISTER_NUMBER, 968 sizeof(u32), 969 GFP_KERNEL); 970 971 preg = rctx->hw_context; 972 973 *preg++ = stm32_hash_read(hdev, HASH_IMR); 974 *preg++ = stm32_hash_read(hdev, HASH_STR); 975 *preg++ = stm32_hash_read(hdev, HASH_CR); 976 for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++) 977 *preg++ = stm32_hash_read(hdev, HASH_CSR(i)); 978 979 pm_runtime_mark_last_busy(hdev->dev); 980 pm_runtime_put_autosuspend(hdev->dev); 981 982 memcpy(out, rctx, sizeof(*rctx)); 983 984 return 0; 985 } 986 987 static int stm32_hash_import(struct ahash_request *req, const void *in) 988 { 989 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req); 990 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); 991 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx); 992 const u32 *preg = in; 993 u32 reg; 994 unsigned int i; 995 996 memcpy(rctx, in, sizeof(*rctx)); 997 998 preg = rctx->hw_context; 999 1000 pm_runtime_get_sync(hdev->dev); 1001 1002 stm32_hash_write(hdev, HASH_IMR, *preg++); 1003 stm32_hash_write(hdev, HASH_STR, *preg++); 1004 stm32_hash_write(hdev, HASH_CR, *preg); 1005 reg = *preg++ | HASH_CR_INIT; 1006 stm32_hash_write(hdev, HASH_CR, reg); 1007 1008 for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++) 1009 stm32_hash_write(hdev, HASH_CSR(i), *preg++); 1010 1011 pm_runtime_mark_last_busy(hdev->dev); 1012 pm_runtime_put_autosuspend(hdev->dev); 1013 1014 kfree(rctx->hw_context); 1015 1016 return 0; 1017 } 1018 1019 static int stm32_hash_setkey(struct crypto_ahash *tfm, 1020 const u8 *key, unsigned int keylen) 1021 { 1022 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); 1023 1024 if (keylen <= HASH_MAX_KEY_SIZE) { 1025 memcpy(ctx->key, key, keylen); 1026 ctx->keylen = keylen; 1027 } else { 1028 return -ENOMEM; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm, 1035 const char *algs_hmac_name) 1036 { 1037 struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm); 1038 1039 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1040 sizeof(struct stm32_hash_request_ctx)); 1041 1042 ctx->keylen = 0; 1043 1044 if (algs_hmac_name) 1045 ctx->flags |= HASH_FLAGS_HMAC; 1046 1047 ctx->enginectx.op.do_one_request = stm32_hash_one_request; 1048 ctx->enginectx.op.prepare_request = stm32_hash_prepare_req; 1049 ctx->enginectx.op.unprepare_request = NULL; 1050 return 0; 1051 } 1052 1053 static int stm32_hash_cra_init(struct crypto_tfm *tfm) 1054 { 1055 return stm32_hash_cra_init_algs(tfm, NULL); 1056 } 1057 1058 static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm) 1059 { 1060 return stm32_hash_cra_init_algs(tfm, "md5"); 1061 } 1062 1063 static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm) 1064 { 1065 return stm32_hash_cra_init_algs(tfm, "sha1"); 1066 } 1067 1068 static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm) 1069 { 1070 return stm32_hash_cra_init_algs(tfm, "sha224"); 1071 } 1072 1073 static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm) 1074 { 1075 return stm32_hash_cra_init_algs(tfm, "sha256"); 1076 } 1077 1078 static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id) 1079 { 1080 struct stm32_hash_dev *hdev = dev_id; 1081 1082 if (HASH_FLAGS_CPU & hdev->flags) { 1083 if (HASH_FLAGS_OUTPUT_READY & hdev->flags) { 1084 hdev->flags &= ~HASH_FLAGS_OUTPUT_READY; 1085 goto finish; 1086 } 1087 } else if (HASH_FLAGS_DMA_READY & hdev->flags) { 1088 if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) { 1089 hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE; 1090 goto finish; 1091 } 1092 } 1093 1094 return IRQ_HANDLED; 1095 1096 finish: 1097 /* Finish current request */ 1098 stm32_hash_finish_req(hdev->req, 0); 1099 1100 return IRQ_HANDLED; 1101 } 1102 1103 static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id) 1104 { 1105 struct stm32_hash_dev *hdev = dev_id; 1106 u32 reg; 1107 1108 reg = stm32_hash_read(hdev, HASH_SR); 1109 if (reg & HASH_SR_OUTPUT_READY) { 1110 reg &= ~HASH_SR_OUTPUT_READY; 1111 stm32_hash_write(hdev, HASH_SR, reg); 1112 hdev->flags |= HASH_FLAGS_OUTPUT_READY; 1113 /* Disable IT*/ 1114 stm32_hash_write(hdev, HASH_IMR, 0); 1115 return IRQ_WAKE_THREAD; 1116 } 1117 1118 return IRQ_NONE; 1119 } 1120 1121 static struct ahash_alg algs_md5_sha1[] = { 1122 { 1123 .init = stm32_hash_init, 1124 .update = stm32_hash_update, 1125 .final = stm32_hash_final, 1126 .finup = stm32_hash_finup, 1127 .digest = stm32_hash_digest, 1128 .export = stm32_hash_export, 1129 .import = stm32_hash_import, 1130 .halg = { 1131 .digestsize = MD5_DIGEST_SIZE, 1132 .statesize = sizeof(struct stm32_hash_request_ctx), 1133 .base = { 1134 .cra_name = "md5", 1135 .cra_driver_name = "stm32-md5", 1136 .cra_priority = 200, 1137 .cra_flags = CRYPTO_ALG_ASYNC | 1138 CRYPTO_ALG_KERN_DRIVER_ONLY, 1139 .cra_blocksize = MD5_HMAC_BLOCK_SIZE, 1140 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1141 .cra_alignmask = 3, 1142 .cra_init = stm32_hash_cra_init, 1143 .cra_module = THIS_MODULE, 1144 } 1145 } 1146 }, 1147 { 1148 .init = stm32_hash_init, 1149 .update = stm32_hash_update, 1150 .final = stm32_hash_final, 1151 .finup = stm32_hash_finup, 1152 .digest = stm32_hash_digest, 1153 .export = stm32_hash_export, 1154 .import = stm32_hash_import, 1155 .setkey = stm32_hash_setkey, 1156 .halg = { 1157 .digestsize = MD5_DIGEST_SIZE, 1158 .statesize = sizeof(struct stm32_hash_request_ctx), 1159 .base = { 1160 .cra_name = "hmac(md5)", 1161 .cra_driver_name = "stm32-hmac-md5", 1162 .cra_priority = 200, 1163 .cra_flags = CRYPTO_ALG_ASYNC | 1164 CRYPTO_ALG_KERN_DRIVER_ONLY, 1165 .cra_blocksize = MD5_HMAC_BLOCK_SIZE, 1166 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1167 .cra_alignmask = 3, 1168 .cra_init = stm32_hash_cra_md5_init, 1169 .cra_module = THIS_MODULE, 1170 } 1171 } 1172 }, 1173 { 1174 .init = stm32_hash_init, 1175 .update = stm32_hash_update, 1176 .final = stm32_hash_final, 1177 .finup = stm32_hash_finup, 1178 .digest = stm32_hash_digest, 1179 .export = stm32_hash_export, 1180 .import = stm32_hash_import, 1181 .halg = { 1182 .digestsize = SHA1_DIGEST_SIZE, 1183 .statesize = sizeof(struct stm32_hash_request_ctx), 1184 .base = { 1185 .cra_name = "sha1", 1186 .cra_driver_name = "stm32-sha1", 1187 .cra_priority = 200, 1188 .cra_flags = CRYPTO_ALG_ASYNC | 1189 CRYPTO_ALG_KERN_DRIVER_ONLY, 1190 .cra_blocksize = SHA1_BLOCK_SIZE, 1191 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1192 .cra_alignmask = 3, 1193 .cra_init = stm32_hash_cra_init, 1194 .cra_module = THIS_MODULE, 1195 } 1196 } 1197 }, 1198 { 1199 .init = stm32_hash_init, 1200 .update = stm32_hash_update, 1201 .final = stm32_hash_final, 1202 .finup = stm32_hash_finup, 1203 .digest = stm32_hash_digest, 1204 .export = stm32_hash_export, 1205 .import = stm32_hash_import, 1206 .setkey = stm32_hash_setkey, 1207 .halg = { 1208 .digestsize = SHA1_DIGEST_SIZE, 1209 .statesize = sizeof(struct stm32_hash_request_ctx), 1210 .base = { 1211 .cra_name = "hmac(sha1)", 1212 .cra_driver_name = "stm32-hmac-sha1", 1213 .cra_priority = 200, 1214 .cra_flags = CRYPTO_ALG_ASYNC | 1215 CRYPTO_ALG_KERN_DRIVER_ONLY, 1216 .cra_blocksize = SHA1_BLOCK_SIZE, 1217 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1218 .cra_alignmask = 3, 1219 .cra_init = stm32_hash_cra_sha1_init, 1220 .cra_module = THIS_MODULE, 1221 } 1222 } 1223 }, 1224 }; 1225 1226 static struct ahash_alg algs_sha224_sha256[] = { 1227 { 1228 .init = stm32_hash_init, 1229 .update = stm32_hash_update, 1230 .final = stm32_hash_final, 1231 .finup = stm32_hash_finup, 1232 .digest = stm32_hash_digest, 1233 .export = stm32_hash_export, 1234 .import = stm32_hash_import, 1235 .halg = { 1236 .digestsize = SHA224_DIGEST_SIZE, 1237 .statesize = sizeof(struct stm32_hash_request_ctx), 1238 .base = { 1239 .cra_name = "sha224", 1240 .cra_driver_name = "stm32-sha224", 1241 .cra_priority = 200, 1242 .cra_flags = CRYPTO_ALG_ASYNC | 1243 CRYPTO_ALG_KERN_DRIVER_ONLY, 1244 .cra_blocksize = SHA224_BLOCK_SIZE, 1245 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1246 .cra_alignmask = 3, 1247 .cra_init = stm32_hash_cra_init, 1248 .cra_module = THIS_MODULE, 1249 } 1250 } 1251 }, 1252 { 1253 .init = stm32_hash_init, 1254 .update = stm32_hash_update, 1255 .final = stm32_hash_final, 1256 .finup = stm32_hash_finup, 1257 .digest = stm32_hash_digest, 1258 .setkey = stm32_hash_setkey, 1259 .export = stm32_hash_export, 1260 .import = stm32_hash_import, 1261 .halg = { 1262 .digestsize = SHA224_DIGEST_SIZE, 1263 .statesize = sizeof(struct stm32_hash_request_ctx), 1264 .base = { 1265 .cra_name = "hmac(sha224)", 1266 .cra_driver_name = "stm32-hmac-sha224", 1267 .cra_priority = 200, 1268 .cra_flags = CRYPTO_ALG_ASYNC | 1269 CRYPTO_ALG_KERN_DRIVER_ONLY, 1270 .cra_blocksize = SHA224_BLOCK_SIZE, 1271 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1272 .cra_alignmask = 3, 1273 .cra_init = stm32_hash_cra_sha224_init, 1274 .cra_module = THIS_MODULE, 1275 } 1276 } 1277 }, 1278 { 1279 .init = stm32_hash_init, 1280 .update = stm32_hash_update, 1281 .final = stm32_hash_final, 1282 .finup = stm32_hash_finup, 1283 .digest = stm32_hash_digest, 1284 .export = stm32_hash_export, 1285 .import = stm32_hash_import, 1286 .halg = { 1287 .digestsize = SHA256_DIGEST_SIZE, 1288 .statesize = sizeof(struct stm32_hash_request_ctx), 1289 .base = { 1290 .cra_name = "sha256", 1291 .cra_driver_name = "stm32-sha256", 1292 .cra_priority = 200, 1293 .cra_flags = CRYPTO_ALG_ASYNC | 1294 CRYPTO_ALG_KERN_DRIVER_ONLY, 1295 .cra_blocksize = SHA256_BLOCK_SIZE, 1296 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1297 .cra_alignmask = 3, 1298 .cra_init = stm32_hash_cra_init, 1299 .cra_module = THIS_MODULE, 1300 } 1301 } 1302 }, 1303 { 1304 .init = stm32_hash_init, 1305 .update = stm32_hash_update, 1306 .final = stm32_hash_final, 1307 .finup = stm32_hash_finup, 1308 .digest = stm32_hash_digest, 1309 .export = stm32_hash_export, 1310 .import = stm32_hash_import, 1311 .setkey = stm32_hash_setkey, 1312 .halg = { 1313 .digestsize = SHA256_DIGEST_SIZE, 1314 .statesize = sizeof(struct stm32_hash_request_ctx), 1315 .base = { 1316 .cra_name = "hmac(sha256)", 1317 .cra_driver_name = "stm32-hmac-sha256", 1318 .cra_priority = 200, 1319 .cra_flags = CRYPTO_ALG_ASYNC | 1320 CRYPTO_ALG_KERN_DRIVER_ONLY, 1321 .cra_blocksize = SHA256_BLOCK_SIZE, 1322 .cra_ctxsize = sizeof(struct stm32_hash_ctx), 1323 .cra_alignmask = 3, 1324 .cra_init = stm32_hash_cra_sha256_init, 1325 .cra_module = THIS_MODULE, 1326 } 1327 } 1328 }, 1329 }; 1330 1331 static int stm32_hash_register_algs(struct stm32_hash_dev *hdev) 1332 { 1333 unsigned int i, j; 1334 int err; 1335 1336 for (i = 0; i < hdev->pdata->algs_info_size; i++) { 1337 for (j = 0; j < hdev->pdata->algs_info[i].size; j++) { 1338 err = crypto_register_ahash( 1339 &hdev->pdata->algs_info[i].algs_list[j]); 1340 if (err) 1341 goto err_algs; 1342 } 1343 } 1344 1345 return 0; 1346 err_algs: 1347 dev_err(hdev->dev, "Algo %d : %d failed\n", i, j); 1348 for (; i--; ) { 1349 for (; j--;) 1350 crypto_unregister_ahash( 1351 &hdev->pdata->algs_info[i].algs_list[j]); 1352 } 1353 1354 return err; 1355 } 1356 1357 static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev) 1358 { 1359 unsigned int i, j; 1360 1361 for (i = 0; i < hdev->pdata->algs_info_size; i++) { 1362 for (j = 0; j < hdev->pdata->algs_info[i].size; j++) 1363 crypto_unregister_ahash( 1364 &hdev->pdata->algs_info[i].algs_list[j]); 1365 } 1366 1367 return 0; 1368 } 1369 1370 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = { 1371 { 1372 .algs_list = algs_md5_sha1, 1373 .size = ARRAY_SIZE(algs_md5_sha1), 1374 }, 1375 }; 1376 1377 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = { 1378 .algs_info = stm32_hash_algs_info_stm32f4, 1379 .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4), 1380 }; 1381 1382 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = { 1383 { 1384 .algs_list = algs_md5_sha1, 1385 .size = ARRAY_SIZE(algs_md5_sha1), 1386 }, 1387 { 1388 .algs_list = algs_sha224_sha256, 1389 .size = ARRAY_SIZE(algs_sha224_sha256), 1390 }, 1391 }; 1392 1393 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = { 1394 .algs_info = stm32_hash_algs_info_stm32f7, 1395 .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7), 1396 }; 1397 1398 static const struct of_device_id stm32_hash_of_match[] = { 1399 { 1400 .compatible = "st,stm32f456-hash", 1401 .data = &stm32_hash_pdata_stm32f4, 1402 }, 1403 { 1404 .compatible = "st,stm32f756-hash", 1405 .data = &stm32_hash_pdata_stm32f7, 1406 }, 1407 {}, 1408 }; 1409 1410 MODULE_DEVICE_TABLE(of, stm32_hash_of_match); 1411 1412 static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev, 1413 struct device *dev) 1414 { 1415 hdev->pdata = of_device_get_match_data(dev); 1416 if (!hdev->pdata) { 1417 dev_err(dev, "no compatible OF match\n"); 1418 return -EINVAL; 1419 } 1420 1421 if (of_property_read_u32(dev->of_node, "dma-maxburst", 1422 &hdev->dma_maxburst)) { 1423 dev_info(dev, "dma-maxburst not specified, using 0\n"); 1424 hdev->dma_maxburst = 0; 1425 } 1426 1427 return 0; 1428 } 1429 1430 static int stm32_hash_probe(struct platform_device *pdev) 1431 { 1432 struct stm32_hash_dev *hdev; 1433 struct device *dev = &pdev->dev; 1434 struct resource *res; 1435 int ret, irq; 1436 1437 hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL); 1438 if (!hdev) 1439 return -ENOMEM; 1440 1441 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1442 hdev->io_base = devm_ioremap_resource(dev, res); 1443 if (IS_ERR(hdev->io_base)) 1444 return PTR_ERR(hdev->io_base); 1445 1446 hdev->phys_base = res->start; 1447 1448 ret = stm32_hash_get_of_match(hdev, dev); 1449 if (ret) 1450 return ret; 1451 1452 irq = platform_get_irq(pdev, 0); 1453 if (irq < 0) { 1454 dev_err(dev, "Cannot get IRQ resource\n"); 1455 return irq; 1456 } 1457 1458 ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler, 1459 stm32_hash_irq_thread, IRQF_ONESHOT, 1460 dev_name(dev), hdev); 1461 if (ret) { 1462 dev_err(dev, "Cannot grab IRQ\n"); 1463 return ret; 1464 } 1465 1466 hdev->clk = devm_clk_get(&pdev->dev, NULL); 1467 if (IS_ERR(hdev->clk)) { 1468 dev_err(dev, "failed to get clock for hash (%lu)\n", 1469 PTR_ERR(hdev->clk)); 1470 return PTR_ERR(hdev->clk); 1471 } 1472 1473 ret = clk_prepare_enable(hdev->clk); 1474 if (ret) { 1475 dev_err(dev, "failed to enable hash clock (%d)\n", ret); 1476 return ret; 1477 } 1478 1479 pm_runtime_set_autosuspend_delay(dev, HASH_AUTOSUSPEND_DELAY); 1480 pm_runtime_use_autosuspend(dev); 1481 1482 pm_runtime_get_noresume(dev); 1483 pm_runtime_set_active(dev); 1484 pm_runtime_enable(dev); 1485 1486 hdev->rst = devm_reset_control_get(&pdev->dev, NULL); 1487 if (!IS_ERR(hdev->rst)) { 1488 reset_control_assert(hdev->rst); 1489 udelay(2); 1490 reset_control_deassert(hdev->rst); 1491 } 1492 1493 hdev->dev = dev; 1494 1495 platform_set_drvdata(pdev, hdev); 1496 1497 ret = stm32_hash_dma_init(hdev); 1498 if (ret) 1499 dev_dbg(dev, "DMA mode not available\n"); 1500 1501 spin_lock(&stm32_hash.lock); 1502 list_add_tail(&hdev->list, &stm32_hash.dev_list); 1503 spin_unlock(&stm32_hash.lock); 1504 1505 /* Initialize crypto engine */ 1506 hdev->engine = crypto_engine_alloc_init(dev, 1); 1507 if (!hdev->engine) { 1508 ret = -ENOMEM; 1509 goto err_engine; 1510 } 1511 1512 ret = crypto_engine_start(hdev->engine); 1513 if (ret) 1514 goto err_engine_start; 1515 1516 hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR); 1517 1518 /* Register algos */ 1519 ret = stm32_hash_register_algs(hdev); 1520 if (ret) 1521 goto err_algs; 1522 1523 dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n", 1524 stm32_hash_read(hdev, HASH_VER), hdev->dma_mode); 1525 1526 pm_runtime_put_sync(dev); 1527 1528 return 0; 1529 1530 err_algs: 1531 err_engine_start: 1532 crypto_engine_exit(hdev->engine); 1533 err_engine: 1534 spin_lock(&stm32_hash.lock); 1535 list_del(&hdev->list); 1536 spin_unlock(&stm32_hash.lock); 1537 1538 if (hdev->dma_lch) 1539 dma_release_channel(hdev->dma_lch); 1540 1541 pm_runtime_disable(dev); 1542 pm_runtime_put_noidle(dev); 1543 1544 clk_disable_unprepare(hdev->clk); 1545 1546 return ret; 1547 } 1548 1549 static int stm32_hash_remove(struct platform_device *pdev) 1550 { 1551 struct stm32_hash_dev *hdev; 1552 int ret; 1553 1554 hdev = platform_get_drvdata(pdev); 1555 if (!hdev) 1556 return -ENODEV; 1557 1558 ret = pm_runtime_get_sync(hdev->dev); 1559 if (ret < 0) 1560 return ret; 1561 1562 stm32_hash_unregister_algs(hdev); 1563 1564 crypto_engine_exit(hdev->engine); 1565 1566 spin_lock(&stm32_hash.lock); 1567 list_del(&hdev->list); 1568 spin_unlock(&stm32_hash.lock); 1569 1570 if (hdev->dma_lch) 1571 dma_release_channel(hdev->dma_lch); 1572 1573 pm_runtime_disable(hdev->dev); 1574 pm_runtime_put_noidle(hdev->dev); 1575 1576 clk_disable_unprepare(hdev->clk); 1577 1578 return 0; 1579 } 1580 1581 #ifdef CONFIG_PM 1582 static int stm32_hash_runtime_suspend(struct device *dev) 1583 { 1584 struct stm32_hash_dev *hdev = dev_get_drvdata(dev); 1585 1586 clk_disable_unprepare(hdev->clk); 1587 1588 return 0; 1589 } 1590 1591 static int stm32_hash_runtime_resume(struct device *dev) 1592 { 1593 struct stm32_hash_dev *hdev = dev_get_drvdata(dev); 1594 int ret; 1595 1596 ret = clk_prepare_enable(hdev->clk); 1597 if (ret) { 1598 dev_err(hdev->dev, "Failed to prepare_enable clock\n"); 1599 return ret; 1600 } 1601 1602 return 0; 1603 } 1604 #endif 1605 1606 static const struct dev_pm_ops stm32_hash_pm_ops = { 1607 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1608 pm_runtime_force_resume) 1609 SET_RUNTIME_PM_OPS(stm32_hash_runtime_suspend, 1610 stm32_hash_runtime_resume, NULL) 1611 }; 1612 1613 static struct platform_driver stm32_hash_driver = { 1614 .probe = stm32_hash_probe, 1615 .remove = stm32_hash_remove, 1616 .driver = { 1617 .name = "stm32-hash", 1618 .pm = &stm32_hash_pm_ops, 1619 .of_match_table = stm32_hash_of_match, 1620 } 1621 }; 1622 1623 module_platform_driver(stm32_hash_driver); 1624 1625 MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver"); 1626 MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>"); 1627 MODULE_LICENSE("GPL v2"); 1628