1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Cryptographic API. 4 // 5 // Support for Samsung S5PV210 and Exynos HW acceleration. 6 // 7 // Copyright (C) 2011 NetUP Inc. All rights reserved. 8 // Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved. 9 // 10 // Hash part based on omap-sham.c driver. 11 12 #include <linux/clk.h> 13 #include <linux/crypto.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/scatterlist.h> 25 26 #include <crypto/ctr.h> 27 #include <crypto/aes.h> 28 #include <crypto/algapi.h> 29 #include <crypto/scatterwalk.h> 30 31 #include <crypto/hash.h> 32 #include <crypto/md5.h> 33 #include <crypto/sha1.h> 34 #include <crypto/sha2.h> 35 #include <crypto/internal/hash.h> 36 37 #define _SBF(s, v) ((v) << (s)) 38 39 /* Feed control registers */ 40 #define SSS_REG_FCINTSTAT 0x0000 41 #define SSS_FCINTSTAT_HPARTINT BIT(7) 42 #define SSS_FCINTSTAT_HDONEINT BIT(5) 43 #define SSS_FCINTSTAT_BRDMAINT BIT(3) 44 #define SSS_FCINTSTAT_BTDMAINT BIT(2) 45 #define SSS_FCINTSTAT_HRDMAINT BIT(1) 46 #define SSS_FCINTSTAT_PKDMAINT BIT(0) 47 48 #define SSS_REG_FCINTENSET 0x0004 49 #define SSS_FCINTENSET_HPARTINTENSET BIT(7) 50 #define SSS_FCINTENSET_HDONEINTENSET BIT(5) 51 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3) 52 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2) 53 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1) 54 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0) 55 56 #define SSS_REG_FCINTENCLR 0x0008 57 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7) 58 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5) 59 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) 60 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) 61 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) 62 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) 63 64 #define SSS_REG_FCINTPEND 0x000C 65 #define SSS_FCINTPEND_HPARTINTP BIT(7) 66 #define SSS_FCINTPEND_HDONEINTP BIT(5) 67 #define SSS_FCINTPEND_BRDMAINTP BIT(3) 68 #define SSS_FCINTPEND_BTDMAINTP BIT(2) 69 #define SSS_FCINTPEND_HRDMAINTP BIT(1) 70 #define SSS_FCINTPEND_PKDMAINTP BIT(0) 71 72 #define SSS_REG_FCFIFOSTAT 0x0010 73 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) 74 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) 75 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) 76 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) 77 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) 78 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) 79 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) 80 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) 81 82 #define SSS_REG_FCFIFOCTRL 0x0014 83 #define SSS_FCFIFOCTRL_DESSEL BIT(2) 84 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) 85 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) 86 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) 87 #define SSS_HASHIN_MASK _SBF(0, 0x03) 88 89 #define SSS_REG_FCBRDMAS 0x0020 90 #define SSS_REG_FCBRDMAL 0x0024 91 #define SSS_REG_FCBRDMAC 0x0028 92 #define SSS_FCBRDMAC_BYTESWAP BIT(1) 93 #define SSS_FCBRDMAC_FLUSH BIT(0) 94 95 #define SSS_REG_FCBTDMAS 0x0030 96 #define SSS_REG_FCBTDMAL 0x0034 97 #define SSS_REG_FCBTDMAC 0x0038 98 #define SSS_FCBTDMAC_BYTESWAP BIT(1) 99 #define SSS_FCBTDMAC_FLUSH BIT(0) 100 101 #define SSS_REG_FCHRDMAS 0x0040 102 #define SSS_REG_FCHRDMAL 0x0044 103 #define SSS_REG_FCHRDMAC 0x0048 104 #define SSS_FCHRDMAC_BYTESWAP BIT(1) 105 #define SSS_FCHRDMAC_FLUSH BIT(0) 106 107 #define SSS_REG_FCPKDMAS 0x0050 108 #define SSS_REG_FCPKDMAL 0x0054 109 #define SSS_REG_FCPKDMAC 0x0058 110 #define SSS_FCPKDMAC_BYTESWAP BIT(3) 111 #define SSS_FCPKDMAC_DESCEND BIT(2) 112 #define SSS_FCPKDMAC_TRANSMIT BIT(1) 113 #define SSS_FCPKDMAC_FLUSH BIT(0) 114 115 #define SSS_REG_FCPKDMAO 0x005C 116 117 /* AES registers */ 118 #define SSS_REG_AES_CONTROL 0x00 119 #define SSS_AES_BYTESWAP_DI BIT(11) 120 #define SSS_AES_BYTESWAP_DO BIT(10) 121 #define SSS_AES_BYTESWAP_IV BIT(9) 122 #define SSS_AES_BYTESWAP_CNT BIT(8) 123 #define SSS_AES_BYTESWAP_KEY BIT(7) 124 #define SSS_AES_KEY_CHANGE_MODE BIT(6) 125 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) 126 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) 127 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) 128 #define SSS_AES_FIFO_MODE BIT(3) 129 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) 130 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) 131 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) 132 #define SSS_AES_MODE_DECRYPT BIT(0) 133 134 #define SSS_REG_AES_STATUS 0x04 135 #define SSS_AES_BUSY BIT(2) 136 #define SSS_AES_INPUT_READY BIT(1) 137 #define SSS_AES_OUTPUT_READY BIT(0) 138 139 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) 140 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) 141 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) 142 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) 143 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) 144 145 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) 146 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) 147 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) 148 149 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) 150 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ 151 SSS_AES_REG(dev, reg)) 152 153 /* HW engine modes */ 154 #define FLAGS_AES_DECRYPT BIT(0) 155 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) 156 #define FLAGS_AES_CBC _SBF(1, 0x01) 157 #define FLAGS_AES_CTR _SBF(1, 0x02) 158 159 #define AES_KEY_LEN 16 160 #define CRYPTO_QUEUE_LEN 1 161 162 /* HASH registers */ 163 #define SSS_REG_HASH_CTRL 0x00 164 165 #define SSS_HASH_USER_IV_EN BIT(5) 166 #define SSS_HASH_INIT_BIT BIT(4) 167 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00) 168 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01) 169 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02) 170 171 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03) 172 173 #define SSS_REG_HASH_CTRL_PAUSE 0x04 174 175 #define SSS_HASH_PAUSE BIT(0) 176 177 #define SSS_REG_HASH_CTRL_FIFO 0x08 178 179 #define SSS_HASH_FIFO_MODE_DMA BIT(0) 180 #define SSS_HASH_FIFO_MODE_CPU 0 181 182 #define SSS_REG_HASH_CTRL_SWAP 0x0C 183 184 #define SSS_HASH_BYTESWAP_DI BIT(3) 185 #define SSS_HASH_BYTESWAP_DO BIT(2) 186 #define SSS_HASH_BYTESWAP_IV BIT(1) 187 #define SSS_HASH_BYTESWAP_KEY BIT(0) 188 189 #define SSS_REG_HASH_STATUS 0x10 190 191 #define SSS_HASH_STATUS_MSG_DONE BIT(6) 192 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4) 193 #define SSS_HASH_STATUS_BUFFER_READY BIT(0) 194 195 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20 196 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24 197 198 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28 199 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C 200 201 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2)) 202 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2)) 203 204 #define HASH_BLOCK_SIZE 64 205 #define HASH_REG_SIZEOF 4 206 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF) 207 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF) 208 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF) 209 210 /* 211 * HASH bit numbers, used by device, setting in dev->hash_flags with 212 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(), 213 * to keep HASH state BUSY or FREE, or to signal state from irq_handler 214 * to hash_tasklet. SGS keep track of allocated memory for scatterlist 215 */ 216 #define HASH_FLAGS_BUSY 0 217 #define HASH_FLAGS_FINAL 1 218 #define HASH_FLAGS_DMA_ACTIVE 2 219 #define HASH_FLAGS_OUTPUT_READY 3 220 #define HASH_FLAGS_DMA_READY 4 221 #define HASH_FLAGS_SGS_COPIED 5 222 #define HASH_FLAGS_SGS_ALLOCED 6 223 224 /* HASH HW constants */ 225 #define BUFLEN HASH_BLOCK_SIZE 226 227 #define SSS_HASH_DMA_LEN_ALIGN 8 228 #define SSS_HASH_DMA_ALIGN_MASK (SSS_HASH_DMA_LEN_ALIGN - 1) 229 230 #define SSS_HASH_QUEUE_LENGTH 10 231 232 /** 233 * struct samsung_aes_variant - platform specific SSS driver data 234 * @aes_offset: AES register offset from SSS module's base. 235 * @hash_offset: HASH register offset from SSS module's base. 236 * @clk_names: names of clocks needed to run SSS IP 237 * 238 * Specifies platform specific configuration of SSS module. 239 * Note: A structure for driver specific platform data is used for future 240 * expansion of its usage. 241 */ 242 struct samsung_aes_variant { 243 unsigned int aes_offset; 244 unsigned int hash_offset; 245 const char *clk_names[2]; 246 }; 247 248 struct s5p_aes_reqctx { 249 unsigned long mode; 250 }; 251 252 struct s5p_aes_ctx { 253 struct s5p_aes_dev *dev; 254 255 u8 aes_key[AES_MAX_KEY_SIZE]; 256 u8 nonce[CTR_RFC3686_NONCE_SIZE]; 257 int keylen; 258 }; 259 260 /** 261 * struct s5p_aes_dev - Crypto device state container 262 * @dev: Associated device 263 * @clk: Clock for accessing hardware 264 * @pclk: APB bus clock necessary to access the hardware 265 * @ioaddr: Mapped IO memory region 266 * @aes_ioaddr: Per-varian offset for AES block IO memory 267 * @irq_fc: Feed control interrupt line 268 * @req: Crypto request currently handled by the device 269 * @ctx: Configuration for currently handled crypto request 270 * @sg_src: Scatter list with source data for currently handled block 271 * in device. This is DMA-mapped into device. 272 * @sg_dst: Scatter list with destination data for currently handled block 273 * in device. This is DMA-mapped into device. 274 * @sg_src_cpy: In case of unaligned access, copied scatter list 275 * with source data. 276 * @sg_dst_cpy: In case of unaligned access, copied scatter list 277 * with destination data. 278 * @tasklet: New request scheduling jib 279 * @queue: Crypto queue 280 * @busy: Indicates whether the device is currently handling some request 281 * thus it uses some of the fields from this state, like: 282 * req, ctx, sg_src/dst (and copies). This essentially 283 * protects against concurrent access to these fields. 284 * @lock: Lock for protecting both access to device hardware registers 285 * and fields related to current request (including the busy field). 286 * @res: Resources for hash. 287 * @io_hash_base: Per-variant offset for HASH block IO memory. 288 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags 289 * variable. 290 * @hash_flags: Flags for current HASH op. 291 * @hash_queue: Async hash queue. 292 * @hash_tasklet: New HASH request scheduling job. 293 * @xmit_buf: Buffer for current HASH request transfer into SSS block. 294 * @hash_req: Current request sending to SSS HASH block. 295 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block. 296 * @hash_sg_cnt: Counter for hash_sg_iter. 297 * 298 * @use_hash: true if HASH algs enabled 299 */ 300 struct s5p_aes_dev { 301 struct device *dev; 302 struct clk *clk; 303 struct clk *pclk; 304 void __iomem *ioaddr; 305 void __iomem *aes_ioaddr; 306 int irq_fc; 307 308 struct skcipher_request *req; 309 struct s5p_aes_ctx *ctx; 310 struct scatterlist *sg_src; 311 struct scatterlist *sg_dst; 312 313 struct scatterlist *sg_src_cpy; 314 struct scatterlist *sg_dst_cpy; 315 316 struct tasklet_struct tasklet; 317 struct crypto_queue queue; 318 bool busy; 319 spinlock_t lock; 320 321 struct resource *res; 322 void __iomem *io_hash_base; 323 324 spinlock_t hash_lock; /* protect hash_ vars */ 325 unsigned long hash_flags; 326 struct crypto_queue hash_queue; 327 struct tasklet_struct hash_tasklet; 328 329 u8 xmit_buf[BUFLEN]; 330 struct ahash_request *hash_req; 331 struct scatterlist *hash_sg_iter; 332 unsigned int hash_sg_cnt; 333 334 bool use_hash; 335 }; 336 337 /** 338 * struct s5p_hash_reqctx - HASH request context 339 * @dd: Associated device 340 * @op_update: Current request operation (OP_UPDATE or OP_FINAL) 341 * @digcnt: Number of bytes processed by HW (without buffer[] ones) 342 * @digest: Digest message or IV for partial result 343 * @nregs: Number of HW registers for digest or IV read/write 344 * @engine: Bits for selecting type of HASH in SSS block 345 * @sg: sg for DMA transfer 346 * @sg_len: Length of sg for DMA transfer 347 * @sgl: sg for joining buffer and req->src scatterlist 348 * @skip: Skip offset in req->src for current op 349 * @total: Total number of bytes for current request 350 * @finup: Keep state for finup or final. 351 * @error: Keep track of error. 352 * @bufcnt: Number of bytes holded in buffer[] 353 * @buffer: For byte(s) from end of req->src in UPDATE op 354 */ 355 struct s5p_hash_reqctx { 356 struct s5p_aes_dev *dd; 357 bool op_update; 358 359 u64 digcnt; 360 u8 digest[SHA256_DIGEST_SIZE]; 361 362 unsigned int nregs; /* digest_size / sizeof(reg) */ 363 u32 engine; 364 365 struct scatterlist *sg; 366 unsigned int sg_len; 367 struct scatterlist sgl[2]; 368 unsigned int skip; 369 unsigned int total; 370 bool finup; 371 bool error; 372 373 u32 bufcnt; 374 u8 buffer[]; 375 }; 376 377 /** 378 * struct s5p_hash_ctx - HASH transformation context 379 * @dd: Associated device 380 * @flags: Bits for algorithm HASH. 381 * @fallback: Software transformation for zero message or size < BUFLEN. 382 */ 383 struct s5p_hash_ctx { 384 struct s5p_aes_dev *dd; 385 unsigned long flags; 386 struct crypto_shash *fallback; 387 }; 388 389 static const struct samsung_aes_variant s5p_aes_data = { 390 .aes_offset = 0x4000, 391 .hash_offset = 0x6000, 392 .clk_names = { "secss", }, 393 }; 394 395 static const struct samsung_aes_variant exynos_aes_data = { 396 .aes_offset = 0x200, 397 .hash_offset = 0x400, 398 .clk_names = { "secss", }, 399 }; 400 401 static const struct samsung_aes_variant exynos5433_slim_aes_data = { 402 .aes_offset = 0x400, 403 .hash_offset = 0x800, 404 .clk_names = { "pclk", "aclk", }, 405 }; 406 407 static const struct of_device_id s5p_sss_dt_match[] = { 408 { 409 .compatible = "samsung,s5pv210-secss", 410 .data = &s5p_aes_data, 411 }, 412 { 413 .compatible = "samsung,exynos4210-secss", 414 .data = &exynos_aes_data, 415 }, 416 { 417 .compatible = "samsung,exynos5433-slim-sss", 418 .data = &exynos5433_slim_aes_data, 419 }, 420 { }, 421 }; 422 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); 423 424 static inline const struct samsung_aes_variant *find_s5p_sss_version 425 (const struct platform_device *pdev) 426 { 427 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) { 428 const struct of_device_id *match; 429 430 match = of_match_node(s5p_sss_dt_match, 431 pdev->dev.of_node); 432 return (const struct samsung_aes_variant *)match->data; 433 } 434 return (const struct samsung_aes_variant *) 435 platform_get_device_id(pdev)->driver_data; 436 } 437 438 static struct s5p_aes_dev *s5p_dev; 439 440 static void s5p_set_dma_indata(struct s5p_aes_dev *dev, 441 const struct scatterlist *sg) 442 { 443 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); 444 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); 445 } 446 447 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, 448 const struct scatterlist *sg) 449 { 450 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); 451 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); 452 } 453 454 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg) 455 { 456 int len; 457 458 if (!*sg) 459 return; 460 461 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 462 free_pages((unsigned long)sg_virt(*sg), get_order(len)); 463 464 kfree(*sg); 465 *sg = NULL; 466 } 467 468 static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg, 469 unsigned int nbytes, int out) 470 { 471 struct scatter_walk walk; 472 473 if (!nbytes) 474 return; 475 476 scatterwalk_start(&walk, sg); 477 scatterwalk_copychunks(buf, &walk, nbytes, out); 478 scatterwalk_done(&walk, out, 0); 479 } 480 481 static void s5p_sg_done(struct s5p_aes_dev *dev) 482 { 483 struct skcipher_request *req = dev->req; 484 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 485 486 if (dev->sg_dst_cpy) { 487 dev_dbg(dev->dev, 488 "Copying %d bytes of output data back to original place\n", 489 dev->req->cryptlen); 490 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst, 491 dev->req->cryptlen, 1); 492 } 493 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 494 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 495 if (reqctx->mode & FLAGS_AES_CBC) 496 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), AES_BLOCK_SIZE); 497 498 else if (reqctx->mode & FLAGS_AES_CTR) 499 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), AES_BLOCK_SIZE); 500 } 501 502 /* Calls the completion. Cannot be called with dev->lock hold. */ 503 static void s5p_aes_complete(struct skcipher_request *req, int err) 504 { 505 req->base.complete(&req->base, err); 506 } 507 508 static void s5p_unset_outdata(struct s5p_aes_dev *dev) 509 { 510 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); 511 } 512 513 static void s5p_unset_indata(struct s5p_aes_dev *dev) 514 { 515 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); 516 } 517 518 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src, 519 struct scatterlist **dst) 520 { 521 void *pages; 522 int len; 523 524 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC); 525 if (!*dst) 526 return -ENOMEM; 527 528 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 529 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len)); 530 if (!pages) { 531 kfree(*dst); 532 *dst = NULL; 533 return -ENOMEM; 534 } 535 536 s5p_sg_copy_buf(pages, src, dev->req->cryptlen, 0); 537 538 sg_init_table(*dst, 1); 539 sg_set_buf(*dst, pages, len); 540 541 return 0; 542 } 543 544 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) 545 { 546 if (!sg->length) 547 return -EINVAL; 548 549 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE)) 550 return -ENOMEM; 551 552 dev->sg_dst = sg; 553 554 return 0; 555 } 556 557 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) 558 { 559 if (!sg->length) 560 return -EINVAL; 561 562 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE)) 563 return -ENOMEM; 564 565 dev->sg_src = sg; 566 567 return 0; 568 } 569 570 /* 571 * Returns -ERRNO on error (mapping of new data failed). 572 * On success returns: 573 * - 0 if there is no more data, 574 * - 1 if new transmitting (output) data is ready and its address+length 575 * have to be written to device (by calling s5p_set_dma_outdata()). 576 */ 577 static int s5p_aes_tx(struct s5p_aes_dev *dev) 578 { 579 int ret = 0; 580 581 s5p_unset_outdata(dev); 582 583 if (!sg_is_last(dev->sg_dst)) { 584 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst)); 585 if (!ret) 586 ret = 1; 587 } 588 589 return ret; 590 } 591 592 /* 593 * Returns -ERRNO on error (mapping of new data failed). 594 * On success returns: 595 * - 0 if there is no more data, 596 * - 1 if new receiving (input) data is ready and its address+length 597 * have to be written to device (by calling s5p_set_dma_indata()). 598 */ 599 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/) 600 { 601 int ret = 0; 602 603 s5p_unset_indata(dev); 604 605 if (!sg_is_last(dev->sg_src)) { 606 ret = s5p_set_indata(dev, sg_next(dev->sg_src)); 607 if (!ret) 608 ret = 1; 609 } 610 611 return ret; 612 } 613 614 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset) 615 { 616 return __raw_readl(dd->io_hash_base + offset); 617 } 618 619 static inline void s5p_hash_write(struct s5p_aes_dev *dd, 620 u32 offset, u32 value) 621 { 622 __raw_writel(value, dd->io_hash_base + offset); 623 } 624 625 /** 626 * s5p_set_dma_hashdata() - start DMA with sg 627 * @dev: device 628 * @sg: scatterlist ready to DMA transmit 629 */ 630 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev, 631 const struct scatterlist *sg) 632 { 633 dev->hash_sg_cnt--; 634 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg)); 635 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */ 636 } 637 638 /** 639 * s5p_hash_rx() - get next hash_sg_iter 640 * @dev: device 641 * 642 * Return: 643 * 2 if there is no more data and it is UPDATE op 644 * 1 if new receiving (input) data is ready and can be written to device 645 * 0 if there is no more data and it is FINAL op 646 */ 647 static int s5p_hash_rx(struct s5p_aes_dev *dev) 648 { 649 if (dev->hash_sg_cnt > 0) { 650 dev->hash_sg_iter = sg_next(dev->hash_sg_iter); 651 return 1; 652 } 653 654 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags); 655 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags)) 656 return 0; 657 658 return 2; 659 } 660 661 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) 662 { 663 struct platform_device *pdev = dev_id; 664 struct s5p_aes_dev *dev = platform_get_drvdata(pdev); 665 struct skcipher_request *req; 666 int err_dma_tx = 0; 667 int err_dma_rx = 0; 668 int err_dma_hx = 0; 669 bool tx_end = false; 670 bool hx_end = false; 671 unsigned long flags; 672 u32 status, st_bits; 673 int err; 674 675 spin_lock_irqsave(&dev->lock, flags); 676 677 /* 678 * Handle rx or tx interrupt. If there is still data (scatterlist did not 679 * reach end), then map next scatterlist entry. 680 * In case of such mapping error, s5p_aes_complete() should be called. 681 * 682 * If there is no more data in tx scatter list, call s5p_aes_complete() 683 * and schedule new tasklet. 684 * 685 * Handle hx interrupt. If there is still data map next entry. 686 */ 687 status = SSS_READ(dev, FCINTSTAT); 688 if (status & SSS_FCINTSTAT_BRDMAINT) 689 err_dma_rx = s5p_aes_rx(dev); 690 691 if (status & SSS_FCINTSTAT_BTDMAINT) { 692 if (sg_is_last(dev->sg_dst)) 693 tx_end = true; 694 err_dma_tx = s5p_aes_tx(dev); 695 } 696 697 if (status & SSS_FCINTSTAT_HRDMAINT) 698 err_dma_hx = s5p_hash_rx(dev); 699 700 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT | 701 SSS_FCINTSTAT_HRDMAINT); 702 /* clear DMA bits */ 703 SSS_WRITE(dev, FCINTPEND, st_bits); 704 705 /* clear HASH irq bits */ 706 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) { 707 /* cannot have both HPART and HDONE */ 708 if (status & SSS_FCINTSTAT_HPARTINT) 709 st_bits = SSS_HASH_STATUS_PARTIAL_DONE; 710 711 if (status & SSS_FCINTSTAT_HDONEINT) 712 st_bits = SSS_HASH_STATUS_MSG_DONE; 713 714 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags); 715 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits); 716 hx_end = true; 717 /* when DONE or PART, do not handle HASH DMA */ 718 err_dma_hx = 0; 719 } 720 721 if (err_dma_rx < 0) { 722 err = err_dma_rx; 723 goto error; 724 } 725 if (err_dma_tx < 0) { 726 err = err_dma_tx; 727 goto error; 728 } 729 730 if (tx_end) { 731 s5p_sg_done(dev); 732 if (err_dma_hx == 1) 733 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 734 735 spin_unlock_irqrestore(&dev->lock, flags); 736 737 s5p_aes_complete(dev->req, 0); 738 /* Device is still busy */ 739 tasklet_schedule(&dev->tasklet); 740 } else { 741 /* 742 * Writing length of DMA block (either receiving or 743 * transmitting) will start the operation immediately, so this 744 * should be done at the end (even after clearing pending 745 * interrupts to not miss the interrupt). 746 */ 747 if (err_dma_tx == 1) 748 s5p_set_dma_outdata(dev, dev->sg_dst); 749 if (err_dma_rx == 1) 750 s5p_set_dma_indata(dev, dev->sg_src); 751 if (err_dma_hx == 1) 752 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 753 754 spin_unlock_irqrestore(&dev->lock, flags); 755 } 756 757 goto hash_irq_end; 758 759 error: 760 s5p_sg_done(dev); 761 dev->busy = false; 762 req = dev->req; 763 if (err_dma_hx == 1) 764 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 765 766 spin_unlock_irqrestore(&dev->lock, flags); 767 s5p_aes_complete(req, err); 768 769 hash_irq_end: 770 /* 771 * Note about else if: 772 * when hash_sg_iter reaches end and its UPDATE op, 773 * issue SSS_HASH_PAUSE and wait for HPART irq 774 */ 775 if (hx_end) 776 tasklet_schedule(&dev->hash_tasklet); 777 else if (err_dma_hx == 2) 778 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE, 779 SSS_HASH_PAUSE); 780 781 return IRQ_HANDLED; 782 } 783 784 /** 785 * s5p_hash_read_msg() - read message or IV from HW 786 * @req: AHASH request 787 */ 788 static void s5p_hash_read_msg(struct ahash_request *req) 789 { 790 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 791 struct s5p_aes_dev *dd = ctx->dd; 792 u32 *hash = (u32 *)ctx->digest; 793 unsigned int i; 794 795 for (i = 0; i < ctx->nregs; i++) 796 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i)); 797 } 798 799 /** 800 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op. 801 * @dd: device 802 * @ctx: request context 803 */ 804 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd, 805 const struct s5p_hash_reqctx *ctx) 806 { 807 const u32 *hash = (const u32 *)ctx->digest; 808 unsigned int i; 809 810 for (i = 0; i < ctx->nregs; i++) 811 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]); 812 } 813 814 /** 815 * s5p_hash_write_iv() - write IV for next partial/finup op. 816 * @req: AHASH request 817 */ 818 static void s5p_hash_write_iv(struct ahash_request *req) 819 { 820 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 821 822 s5p_hash_write_ctx_iv(ctx->dd, ctx); 823 } 824 825 /** 826 * s5p_hash_copy_result() - copy digest into req->result 827 * @req: AHASH request 828 */ 829 static void s5p_hash_copy_result(struct ahash_request *req) 830 { 831 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 832 833 if (!req->result) 834 return; 835 836 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF); 837 } 838 839 /** 840 * s5p_hash_dma_flush() - flush HASH DMA 841 * @dev: secss device 842 */ 843 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev) 844 { 845 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH); 846 } 847 848 /** 849 * s5p_hash_dma_enable() - enable DMA mode for HASH 850 * @dev: secss device 851 * 852 * enable DMA mode for HASH 853 */ 854 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev) 855 { 856 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA); 857 } 858 859 /** 860 * s5p_hash_irq_disable() - disable irq HASH signals 861 * @dev: secss device 862 * @flags: bitfield with irq's to be disabled 863 */ 864 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags) 865 { 866 SSS_WRITE(dev, FCINTENCLR, flags); 867 } 868 869 /** 870 * s5p_hash_irq_enable() - enable irq signals 871 * @dev: secss device 872 * @flags: bitfield with irq's to be enabled 873 */ 874 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags) 875 { 876 SSS_WRITE(dev, FCINTENSET, flags); 877 } 878 879 /** 880 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH 881 * @dev: secss device 882 * @hashflow: HASH stream flow with/without crypto AES/DES 883 */ 884 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow) 885 { 886 unsigned long flags; 887 u32 flow; 888 889 spin_lock_irqsave(&dev->lock, flags); 890 891 flow = SSS_READ(dev, FCFIFOCTRL); 892 flow &= ~SSS_HASHIN_MASK; 893 flow |= hashflow; 894 SSS_WRITE(dev, FCFIFOCTRL, flow); 895 896 spin_unlock_irqrestore(&dev->lock, flags); 897 } 898 899 /** 900 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS 901 * @dev: secss device 902 * @hashflow: HASH stream flow with/without AES/DES 903 * 904 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW, 905 * enable HASH irq's HRDMA, HDONE, HPART 906 */ 907 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow) 908 { 909 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR | 910 SSS_FCINTENCLR_HDONEINTENCLR | 911 SSS_FCINTENCLR_HPARTINTENCLR); 912 s5p_hash_dma_flush(dev); 913 914 s5p_hash_dma_enable(dev); 915 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK); 916 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET | 917 SSS_FCINTENSET_HDONEINTENSET | 918 SSS_FCINTENSET_HPARTINTENSET); 919 } 920 921 /** 922 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing 923 * @dd: secss device 924 * @length: length for request 925 * @final: true if final op 926 * 927 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called 928 * after previous updates, fill up IV words. For final, calculate and set 929 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH 930 * length as 2^63 so it will be never reached and set to zero prelow and 931 * prehigh. 932 * 933 * This function does not start DMA transfer. 934 */ 935 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length, 936 bool final) 937 { 938 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 939 u32 prelow, prehigh, low, high; 940 u32 configflags, swapflags; 941 u64 tmplen; 942 943 configflags = ctx->engine | SSS_HASH_INIT_BIT; 944 945 if (likely(ctx->digcnt)) { 946 s5p_hash_write_ctx_iv(dd, ctx); 947 configflags |= SSS_HASH_USER_IV_EN; 948 } 949 950 if (final) { 951 /* number of bytes for last part */ 952 low = length; 953 high = 0; 954 /* total number of bits prev hashed */ 955 tmplen = ctx->digcnt * 8; 956 prelow = (u32)tmplen; 957 prehigh = (u32)(tmplen >> 32); 958 } else { 959 prelow = 0; 960 prehigh = 0; 961 low = 0; 962 high = BIT(31); 963 } 964 965 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO | 966 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY; 967 968 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low); 969 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high); 970 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow); 971 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh); 972 973 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags); 974 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags); 975 } 976 977 /** 978 * s5p_hash_xmit_dma() - start DMA hash processing 979 * @dd: secss device 980 * @length: length for request 981 * @final: true if final op 982 * 983 * Update digcnt here, as it is needed for finup/final op. 984 */ 985 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length, 986 bool final) 987 { 988 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 989 unsigned int cnt; 990 991 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 992 if (!cnt) { 993 dev_err(dd->dev, "dma_map_sg error\n"); 994 ctx->error = true; 995 return -EINVAL; 996 } 997 998 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 999 dd->hash_sg_iter = ctx->sg; 1000 dd->hash_sg_cnt = cnt; 1001 s5p_hash_write_ctrl(dd, length, final); 1002 ctx->digcnt += length; 1003 ctx->total -= length; 1004 1005 /* catch last interrupt */ 1006 if (final) 1007 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags); 1008 1009 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */ 1010 1011 return -EINPROGRESS; 1012 } 1013 1014 /** 1015 * s5p_hash_copy_sgs() - copy request's bytes into new buffer 1016 * @ctx: request context 1017 * @sg: source scatterlist request 1018 * @new_len: number of bytes to process from sg 1019 * 1020 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf 1021 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0] 1022 * with allocated buffer. 1023 * 1024 * Set bit in dd->hash_flag so we can free it after irq ends processing. 1025 */ 1026 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx, 1027 struct scatterlist *sg, unsigned int new_len) 1028 { 1029 unsigned int pages, len; 1030 void *buf; 1031 1032 len = new_len + ctx->bufcnt; 1033 pages = get_order(len); 1034 1035 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 1036 if (!buf) { 1037 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n"); 1038 ctx->error = true; 1039 return -ENOMEM; 1040 } 1041 1042 if (ctx->bufcnt) 1043 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 1044 1045 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->skip, 1046 new_len, 0); 1047 sg_init_table(ctx->sgl, 1); 1048 sg_set_buf(ctx->sgl, buf, len); 1049 ctx->sg = ctx->sgl; 1050 ctx->sg_len = 1; 1051 ctx->bufcnt = 0; 1052 ctx->skip = 0; 1053 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy 1060 * @ctx: request context 1061 * @sg: source scatterlist request 1062 * @new_len: number of bytes to process from sg 1063 * 1064 * Allocate new scatterlist table, copy data for HASH into it. If there was 1065 * xmit_buf filled, prepare it first, then copy page, length and offset from 1066 * source sg into it, adjusting begin and/or end for skip offset and 1067 * hash_later value. 1068 * 1069 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free 1070 * it after irq ends processing. 1071 */ 1072 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx, 1073 struct scatterlist *sg, unsigned int new_len) 1074 { 1075 unsigned int skip = ctx->skip, n = sg_nents(sg); 1076 struct scatterlist *tmp; 1077 unsigned int len; 1078 1079 if (ctx->bufcnt) 1080 n++; 1081 1082 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 1083 if (!ctx->sg) { 1084 ctx->error = true; 1085 return -ENOMEM; 1086 } 1087 1088 sg_init_table(ctx->sg, n); 1089 1090 tmp = ctx->sg; 1091 1092 ctx->sg_len = 0; 1093 1094 if (ctx->bufcnt) { 1095 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 1096 tmp = sg_next(tmp); 1097 ctx->sg_len++; 1098 } 1099 1100 while (sg && skip >= sg->length) { 1101 skip -= sg->length; 1102 sg = sg_next(sg); 1103 } 1104 1105 while (sg && new_len) { 1106 len = sg->length - skip; 1107 if (new_len < len) 1108 len = new_len; 1109 1110 new_len -= len; 1111 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip); 1112 skip = 0; 1113 if (new_len <= 0) 1114 sg_mark_end(tmp); 1115 1116 tmp = sg_next(tmp); 1117 ctx->sg_len++; 1118 sg = sg_next(sg); 1119 } 1120 1121 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags); 1122 1123 return 0; 1124 } 1125 1126 /** 1127 * s5p_hash_prepare_sgs() - prepare sg for processing 1128 * @ctx: request context 1129 * @sg: source scatterlist request 1130 * @new_len: number of bytes to process from sg 1131 * @final: final flag 1132 * 1133 * Check two conditions: (1) if buffers in sg have len aligned data, and (2) 1134 * sg table have good aligned elements (list_ok). If one of this checks fails, 1135 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy 1136 * data into this buffer and prepare request in sgl, or (2) allocates new sg 1137 * table and prepare sg elements. 1138 * 1139 * For digest or finup all conditions can be good, and we may not need any 1140 * fixes. 1141 */ 1142 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx, 1143 struct scatterlist *sg, 1144 unsigned int new_len, bool final) 1145 { 1146 unsigned int skip = ctx->skip, nbytes = new_len, n = 0; 1147 bool aligned = true, list_ok = true; 1148 struct scatterlist *sg_tmp = sg; 1149 1150 if (!sg || !sg->length || !new_len) 1151 return 0; 1152 1153 if (skip || !final) 1154 list_ok = false; 1155 1156 while (nbytes > 0 && sg_tmp) { 1157 n++; 1158 if (skip >= sg_tmp->length) { 1159 skip -= sg_tmp->length; 1160 if (!sg_tmp->length) { 1161 aligned = false; 1162 break; 1163 } 1164 } else { 1165 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) { 1166 aligned = false; 1167 break; 1168 } 1169 1170 if (nbytes < sg_tmp->length - skip) { 1171 list_ok = false; 1172 break; 1173 } 1174 1175 nbytes -= sg_tmp->length - skip; 1176 skip = 0; 1177 } 1178 1179 sg_tmp = sg_next(sg_tmp); 1180 } 1181 1182 if (!aligned) 1183 return s5p_hash_copy_sgs(ctx, sg, new_len); 1184 else if (!list_ok) 1185 return s5p_hash_copy_sg_lists(ctx, sg, new_len); 1186 1187 /* 1188 * Have aligned data from previous operation and/or current 1189 * Note: will enter here only if (digest or finup) and aligned 1190 */ 1191 if (ctx->bufcnt) { 1192 ctx->sg_len = n; 1193 sg_init_table(ctx->sgl, 2); 1194 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt); 1195 sg_chain(ctx->sgl, 2, sg); 1196 ctx->sg = ctx->sgl; 1197 ctx->sg_len++; 1198 } else { 1199 ctx->sg = sg; 1200 ctx->sg_len = n; 1201 } 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * s5p_hash_prepare_request() - prepare request for processing 1208 * @req: AHASH request 1209 * @update: true if UPDATE op 1210 * 1211 * Note 1: we can have update flag _and_ final flag at the same time. 1212 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or 1213 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or 1214 * we have final op 1215 */ 1216 static int s5p_hash_prepare_request(struct ahash_request *req, bool update) 1217 { 1218 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1219 bool final = ctx->finup; 1220 int xmit_len, hash_later, nbytes; 1221 int ret; 1222 1223 if (update) 1224 nbytes = req->nbytes; 1225 else 1226 nbytes = 0; 1227 1228 ctx->total = nbytes + ctx->bufcnt; 1229 if (!ctx->total) 1230 return 0; 1231 1232 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) { 1233 /* bytes left from previous request, so fill up to BUFLEN */ 1234 int len = BUFLEN - ctx->bufcnt % BUFLEN; 1235 1236 if (len > nbytes) 1237 len = nbytes; 1238 1239 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1240 0, len, 0); 1241 ctx->bufcnt += len; 1242 nbytes -= len; 1243 ctx->skip = len; 1244 } else { 1245 ctx->skip = 0; 1246 } 1247 1248 if (ctx->bufcnt) 1249 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt); 1250 1251 xmit_len = ctx->total; 1252 if (final) { 1253 hash_later = 0; 1254 } else { 1255 if (IS_ALIGNED(xmit_len, BUFLEN)) 1256 xmit_len -= BUFLEN; 1257 else 1258 xmit_len -= xmit_len & (BUFLEN - 1); 1259 1260 hash_later = ctx->total - xmit_len; 1261 /* copy hash_later bytes from end of req->src */ 1262 /* previous bytes are in xmit_buf, so no overwrite */ 1263 scatterwalk_map_and_copy(ctx->buffer, req->src, 1264 req->nbytes - hash_later, 1265 hash_later, 0); 1266 } 1267 1268 if (xmit_len > BUFLEN) { 1269 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later, 1270 final); 1271 if (ret) 1272 return ret; 1273 } else { 1274 /* have buffered data only */ 1275 if (unlikely(!ctx->bufcnt)) { 1276 /* first update didn't fill up buffer */ 1277 scatterwalk_map_and_copy(ctx->dd->xmit_buf, req->src, 1278 0, xmit_len, 0); 1279 } 1280 1281 sg_init_table(ctx->sgl, 1); 1282 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len); 1283 1284 ctx->sg = ctx->sgl; 1285 ctx->sg_len = 1; 1286 } 1287 1288 ctx->bufcnt = hash_later; 1289 if (!final) 1290 ctx->total = xmit_len; 1291 1292 return 0; 1293 } 1294 1295 /** 1296 * s5p_hash_update_dma_stop() - unmap DMA 1297 * @dd: secss device 1298 * 1299 * Unmap scatterlist ctx->sg. 1300 */ 1301 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd) 1302 { 1303 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 1304 1305 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 1306 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 1307 } 1308 1309 /** 1310 * s5p_hash_finish() - copy calculated digest to crypto layer 1311 * @req: AHASH request 1312 */ 1313 static void s5p_hash_finish(struct ahash_request *req) 1314 { 1315 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1316 struct s5p_aes_dev *dd = ctx->dd; 1317 1318 if (ctx->digcnt) 1319 s5p_hash_copy_result(req); 1320 1321 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt); 1322 } 1323 1324 /** 1325 * s5p_hash_finish_req() - finish request 1326 * @req: AHASH request 1327 * @err: error 1328 */ 1329 static void s5p_hash_finish_req(struct ahash_request *req, int err) 1330 { 1331 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1332 struct s5p_aes_dev *dd = ctx->dd; 1333 unsigned long flags; 1334 1335 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags)) 1336 free_pages((unsigned long)sg_virt(ctx->sg), 1337 get_order(ctx->sg->length)); 1338 1339 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags)) 1340 kfree(ctx->sg); 1341 1342 ctx->sg = NULL; 1343 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) | 1344 BIT(HASH_FLAGS_SGS_COPIED)); 1345 1346 if (!err && !ctx->error) { 1347 s5p_hash_read_msg(req); 1348 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags)) 1349 s5p_hash_finish(req); 1350 } else { 1351 ctx->error = true; 1352 } 1353 1354 spin_lock_irqsave(&dd->hash_lock, flags); 1355 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) | 1356 BIT(HASH_FLAGS_DMA_READY) | 1357 BIT(HASH_FLAGS_OUTPUT_READY)); 1358 spin_unlock_irqrestore(&dd->hash_lock, flags); 1359 1360 if (req->base.complete) 1361 req->base.complete(&req->base, err); 1362 } 1363 1364 /** 1365 * s5p_hash_handle_queue() - handle hash queue 1366 * @dd: device s5p_aes_dev 1367 * @req: AHASH request 1368 * 1369 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the 1370 * device then processes the first request from the dd->queue 1371 * 1372 * Returns: see s5p_hash_final below. 1373 */ 1374 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd, 1375 struct ahash_request *req) 1376 { 1377 struct crypto_async_request *async_req, *backlog; 1378 struct s5p_hash_reqctx *ctx; 1379 unsigned long flags; 1380 int err = 0, ret = 0; 1381 1382 retry: 1383 spin_lock_irqsave(&dd->hash_lock, flags); 1384 if (req) 1385 ret = ahash_enqueue_request(&dd->hash_queue, req); 1386 1387 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1388 spin_unlock_irqrestore(&dd->hash_lock, flags); 1389 return ret; 1390 } 1391 1392 backlog = crypto_get_backlog(&dd->hash_queue); 1393 async_req = crypto_dequeue_request(&dd->hash_queue); 1394 if (async_req) 1395 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags); 1396 1397 spin_unlock_irqrestore(&dd->hash_lock, flags); 1398 1399 if (!async_req) 1400 return ret; 1401 1402 if (backlog) 1403 backlog->complete(backlog, -EINPROGRESS); 1404 1405 req = ahash_request_cast(async_req); 1406 dd->hash_req = req; 1407 ctx = ahash_request_ctx(req); 1408 1409 err = s5p_hash_prepare_request(req, ctx->op_update); 1410 if (err || !ctx->total) 1411 goto out; 1412 1413 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n", 1414 ctx->op_update, req->nbytes); 1415 1416 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT); 1417 if (ctx->digcnt) 1418 s5p_hash_write_iv(req); /* restore hash IV */ 1419 1420 if (ctx->op_update) { /* HASH_OP_UPDATE */ 1421 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup); 1422 if (err != -EINPROGRESS && ctx->finup && !ctx->error) 1423 /* no final() after finup() */ 1424 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1425 } else { /* HASH_OP_FINAL */ 1426 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1427 } 1428 out: 1429 if (err != -EINPROGRESS) { 1430 /* hash_tasklet_cb will not finish it, so do it here */ 1431 s5p_hash_finish_req(req, err); 1432 req = NULL; 1433 1434 /* 1435 * Execute next request immediately if there is anything 1436 * in queue. 1437 */ 1438 goto retry; 1439 } 1440 1441 return ret; 1442 } 1443 1444 /** 1445 * s5p_hash_tasklet_cb() - hash tasklet 1446 * @data: ptr to s5p_aes_dev 1447 */ 1448 static void s5p_hash_tasklet_cb(unsigned long data) 1449 { 1450 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data; 1451 1452 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1453 s5p_hash_handle_queue(dd, NULL); 1454 return; 1455 } 1456 1457 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) { 1458 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE, 1459 &dd->hash_flags)) { 1460 s5p_hash_update_dma_stop(dd); 1461 } 1462 1463 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY, 1464 &dd->hash_flags)) { 1465 /* hash or semi-hash ready */ 1466 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags); 1467 goto finish; 1468 } 1469 } 1470 1471 return; 1472 1473 finish: 1474 /* finish curent request */ 1475 s5p_hash_finish_req(dd->hash_req, 0); 1476 1477 /* If we are not busy, process next req */ 1478 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) 1479 s5p_hash_handle_queue(dd, NULL); 1480 } 1481 1482 /** 1483 * s5p_hash_enqueue() - enqueue request 1484 * @req: AHASH request 1485 * @op: operation UPDATE (true) or FINAL (false) 1486 * 1487 * Returns: see s5p_hash_final below. 1488 */ 1489 static int s5p_hash_enqueue(struct ahash_request *req, bool op) 1490 { 1491 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1492 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1493 1494 ctx->op_update = op; 1495 1496 return s5p_hash_handle_queue(tctx->dd, req); 1497 } 1498 1499 /** 1500 * s5p_hash_update() - process the hash input data 1501 * @req: AHASH request 1502 * 1503 * If request will fit in buffer, copy it and return immediately 1504 * else enqueue it with OP_UPDATE. 1505 * 1506 * Returns: see s5p_hash_final below. 1507 */ 1508 static int s5p_hash_update(struct ahash_request *req) 1509 { 1510 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1511 1512 if (!req->nbytes) 1513 return 0; 1514 1515 if (ctx->bufcnt + req->nbytes <= BUFLEN) { 1516 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1517 0, req->nbytes, 0); 1518 ctx->bufcnt += req->nbytes; 1519 return 0; 1520 } 1521 1522 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */ 1523 } 1524 1525 /** 1526 * s5p_hash_final() - close up hash and calculate digest 1527 * @req: AHASH request 1528 * 1529 * Note: in final req->src do not have any data, and req->nbytes can be 1530 * non-zero. 1531 * 1532 * If there were no input data processed yet and the buffered hash data is 1533 * less than BUFLEN (64) then calculate the final hash immediately by using 1534 * SW algorithm fallback. 1535 * 1536 * Otherwise enqueues the current AHASH request with OP_FINAL operation op 1537 * and finalize hash message in HW. Note that if digcnt!=0 then there were 1538 * previous update op, so there are always some buffered bytes in ctx->buffer, 1539 * which means that ctx->bufcnt!=0 1540 * 1541 * Returns: 1542 * 0 if the request has been processed immediately, 1543 * -EINPROGRESS if the operation has been queued for later execution or is set 1544 * to processing by HW, 1545 * -EBUSY if queue is full and request should be resubmitted later, 1546 * other negative values denotes an error. 1547 */ 1548 static int s5p_hash_final(struct ahash_request *req) 1549 { 1550 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1551 1552 ctx->finup = true; 1553 if (ctx->error) 1554 return -EINVAL; /* uncompleted hash is not needed */ 1555 1556 if (!ctx->digcnt && ctx->bufcnt < BUFLEN) { 1557 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1558 1559 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer, 1560 ctx->bufcnt, req->result); 1561 } 1562 1563 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */ 1564 } 1565 1566 /** 1567 * s5p_hash_finup() - process last req->src and calculate digest 1568 * @req: AHASH request containing the last update data 1569 * 1570 * Return values: see s5p_hash_final above. 1571 */ 1572 static int s5p_hash_finup(struct ahash_request *req) 1573 { 1574 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1575 int err1, err2; 1576 1577 ctx->finup = true; 1578 1579 err1 = s5p_hash_update(req); 1580 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1581 return err1; 1582 1583 /* 1584 * final() has to be always called to cleanup resources even if 1585 * update() failed, except EINPROGRESS or calculate digest for small 1586 * size 1587 */ 1588 err2 = s5p_hash_final(req); 1589 1590 return err1 ?: err2; 1591 } 1592 1593 /** 1594 * s5p_hash_init() - initialize AHASH request contex 1595 * @req: AHASH request 1596 * 1597 * Init async hash request context. 1598 */ 1599 static int s5p_hash_init(struct ahash_request *req) 1600 { 1601 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1602 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1603 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1604 1605 ctx->dd = tctx->dd; 1606 ctx->error = false; 1607 ctx->finup = false; 1608 ctx->bufcnt = 0; 1609 ctx->digcnt = 0; 1610 ctx->total = 0; 1611 ctx->skip = 0; 1612 1613 dev_dbg(tctx->dd->dev, "init: digest size: %d\n", 1614 crypto_ahash_digestsize(tfm)); 1615 1616 switch (crypto_ahash_digestsize(tfm)) { 1617 case MD5_DIGEST_SIZE: 1618 ctx->engine = SSS_HASH_ENGINE_MD5; 1619 ctx->nregs = HASH_MD5_MAX_REG; 1620 break; 1621 case SHA1_DIGEST_SIZE: 1622 ctx->engine = SSS_HASH_ENGINE_SHA1; 1623 ctx->nregs = HASH_SHA1_MAX_REG; 1624 break; 1625 case SHA256_DIGEST_SIZE: 1626 ctx->engine = SSS_HASH_ENGINE_SHA256; 1627 ctx->nregs = HASH_SHA256_MAX_REG; 1628 break; 1629 default: 1630 ctx->error = true; 1631 return -EINVAL; 1632 } 1633 1634 return 0; 1635 } 1636 1637 /** 1638 * s5p_hash_digest - calculate digest from req->src 1639 * @req: AHASH request 1640 * 1641 * Return values: see s5p_hash_final above. 1642 */ 1643 static int s5p_hash_digest(struct ahash_request *req) 1644 { 1645 return s5p_hash_init(req) ?: s5p_hash_finup(req); 1646 } 1647 1648 /** 1649 * s5p_hash_cra_init_alg - init crypto alg transformation 1650 * @tfm: crypto transformation 1651 */ 1652 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm) 1653 { 1654 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1655 const char *alg_name = crypto_tfm_alg_name(tfm); 1656 1657 tctx->dd = s5p_dev; 1658 /* Allocate a fallback and abort if it failed. */ 1659 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1660 CRYPTO_ALG_NEED_FALLBACK); 1661 if (IS_ERR(tctx->fallback)) { 1662 pr_err("fallback alloc fails for '%s'\n", alg_name); 1663 return PTR_ERR(tctx->fallback); 1664 } 1665 1666 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1667 sizeof(struct s5p_hash_reqctx) + BUFLEN); 1668 1669 return 0; 1670 } 1671 1672 /** 1673 * s5p_hash_cra_init - init crypto tfm 1674 * @tfm: crypto transformation 1675 */ 1676 static int s5p_hash_cra_init(struct crypto_tfm *tfm) 1677 { 1678 return s5p_hash_cra_init_alg(tfm); 1679 } 1680 1681 /** 1682 * s5p_hash_cra_exit - exit crypto tfm 1683 * @tfm: crypto transformation 1684 * 1685 * free allocated fallback 1686 */ 1687 static void s5p_hash_cra_exit(struct crypto_tfm *tfm) 1688 { 1689 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1690 1691 crypto_free_shash(tctx->fallback); 1692 tctx->fallback = NULL; 1693 } 1694 1695 /** 1696 * s5p_hash_export - export hash state 1697 * @req: AHASH request 1698 * @out: buffer for exported state 1699 */ 1700 static int s5p_hash_export(struct ahash_request *req, void *out) 1701 { 1702 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1703 1704 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt); 1705 1706 return 0; 1707 } 1708 1709 /** 1710 * s5p_hash_import - import hash state 1711 * @req: AHASH request 1712 * @in: buffer with state to be imported from 1713 */ 1714 static int s5p_hash_import(struct ahash_request *req, const void *in) 1715 { 1716 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1717 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1718 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1719 const struct s5p_hash_reqctx *ctx_in = in; 1720 1721 memcpy(ctx, in, sizeof(*ctx) + BUFLEN); 1722 if (ctx_in->bufcnt > BUFLEN) { 1723 ctx->error = true; 1724 return -EINVAL; 1725 } 1726 1727 ctx->dd = tctx->dd; 1728 ctx->error = false; 1729 1730 return 0; 1731 } 1732 1733 static struct ahash_alg algs_sha1_md5_sha256[] = { 1734 { 1735 .init = s5p_hash_init, 1736 .update = s5p_hash_update, 1737 .final = s5p_hash_final, 1738 .finup = s5p_hash_finup, 1739 .digest = s5p_hash_digest, 1740 .export = s5p_hash_export, 1741 .import = s5p_hash_import, 1742 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1743 .halg.digestsize = SHA1_DIGEST_SIZE, 1744 .halg.base = { 1745 .cra_name = "sha1", 1746 .cra_driver_name = "exynos-sha1", 1747 .cra_priority = 100, 1748 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1749 CRYPTO_ALG_ASYNC | 1750 CRYPTO_ALG_NEED_FALLBACK, 1751 .cra_blocksize = HASH_BLOCK_SIZE, 1752 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1753 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1754 .cra_module = THIS_MODULE, 1755 .cra_init = s5p_hash_cra_init, 1756 .cra_exit = s5p_hash_cra_exit, 1757 } 1758 }, 1759 { 1760 .init = s5p_hash_init, 1761 .update = s5p_hash_update, 1762 .final = s5p_hash_final, 1763 .finup = s5p_hash_finup, 1764 .digest = s5p_hash_digest, 1765 .export = s5p_hash_export, 1766 .import = s5p_hash_import, 1767 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1768 .halg.digestsize = MD5_DIGEST_SIZE, 1769 .halg.base = { 1770 .cra_name = "md5", 1771 .cra_driver_name = "exynos-md5", 1772 .cra_priority = 100, 1773 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1774 CRYPTO_ALG_ASYNC | 1775 CRYPTO_ALG_NEED_FALLBACK, 1776 .cra_blocksize = HASH_BLOCK_SIZE, 1777 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1778 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1779 .cra_module = THIS_MODULE, 1780 .cra_init = s5p_hash_cra_init, 1781 .cra_exit = s5p_hash_cra_exit, 1782 } 1783 }, 1784 { 1785 .init = s5p_hash_init, 1786 .update = s5p_hash_update, 1787 .final = s5p_hash_final, 1788 .finup = s5p_hash_finup, 1789 .digest = s5p_hash_digest, 1790 .export = s5p_hash_export, 1791 .import = s5p_hash_import, 1792 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1793 .halg.digestsize = SHA256_DIGEST_SIZE, 1794 .halg.base = { 1795 .cra_name = "sha256", 1796 .cra_driver_name = "exynos-sha256", 1797 .cra_priority = 100, 1798 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1799 CRYPTO_ALG_ASYNC | 1800 CRYPTO_ALG_NEED_FALLBACK, 1801 .cra_blocksize = HASH_BLOCK_SIZE, 1802 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1803 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1804 .cra_module = THIS_MODULE, 1805 .cra_init = s5p_hash_cra_init, 1806 .cra_exit = s5p_hash_cra_exit, 1807 } 1808 } 1809 1810 }; 1811 1812 static void s5p_set_aes(struct s5p_aes_dev *dev, 1813 const u8 *key, const u8 *iv, const u8 *ctr, 1814 unsigned int keylen) 1815 { 1816 void __iomem *keystart; 1817 1818 if (iv) 1819 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 1820 AES_BLOCK_SIZE); 1821 1822 if (ctr) 1823 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 1824 AES_BLOCK_SIZE); 1825 1826 if (keylen == AES_KEYSIZE_256) 1827 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); 1828 else if (keylen == AES_KEYSIZE_192) 1829 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); 1830 else 1831 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); 1832 1833 memcpy_toio(keystart, key, keylen); 1834 } 1835 1836 static bool s5p_is_sg_aligned(struct scatterlist *sg) 1837 { 1838 while (sg) { 1839 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) 1840 return false; 1841 sg = sg_next(sg); 1842 } 1843 1844 return true; 1845 } 1846 1847 static int s5p_set_indata_start(struct s5p_aes_dev *dev, 1848 struct skcipher_request *req) 1849 { 1850 struct scatterlist *sg; 1851 int err; 1852 1853 dev->sg_src_cpy = NULL; 1854 sg = req->src; 1855 if (!s5p_is_sg_aligned(sg)) { 1856 dev_dbg(dev->dev, 1857 "At least one unaligned source scatter list, making a copy\n"); 1858 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy); 1859 if (err) 1860 return err; 1861 1862 sg = dev->sg_src_cpy; 1863 } 1864 1865 err = s5p_set_indata(dev, sg); 1866 if (err) { 1867 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 1868 return err; 1869 } 1870 1871 return 0; 1872 } 1873 1874 static int s5p_set_outdata_start(struct s5p_aes_dev *dev, 1875 struct skcipher_request *req) 1876 { 1877 struct scatterlist *sg; 1878 int err; 1879 1880 dev->sg_dst_cpy = NULL; 1881 sg = req->dst; 1882 if (!s5p_is_sg_aligned(sg)) { 1883 dev_dbg(dev->dev, 1884 "At least one unaligned dest scatter list, making a copy\n"); 1885 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy); 1886 if (err) 1887 return err; 1888 1889 sg = dev->sg_dst_cpy; 1890 } 1891 1892 err = s5p_set_outdata(dev, sg); 1893 if (err) { 1894 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 1895 return err; 1896 } 1897 1898 return 0; 1899 } 1900 1901 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) 1902 { 1903 struct skcipher_request *req = dev->req; 1904 u32 aes_control; 1905 unsigned long flags; 1906 int err; 1907 u8 *iv, *ctr; 1908 1909 /* This sets bit [13:12] to 00, which selects 128-bit counter */ 1910 aes_control = SSS_AES_KEY_CHANGE_MODE; 1911 if (mode & FLAGS_AES_DECRYPT) 1912 aes_control |= SSS_AES_MODE_DECRYPT; 1913 1914 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) { 1915 aes_control |= SSS_AES_CHAIN_MODE_CBC; 1916 iv = req->iv; 1917 ctr = NULL; 1918 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) { 1919 aes_control |= SSS_AES_CHAIN_MODE_CTR; 1920 iv = NULL; 1921 ctr = req->iv; 1922 } else { 1923 iv = NULL; /* AES_ECB */ 1924 ctr = NULL; 1925 } 1926 1927 if (dev->ctx->keylen == AES_KEYSIZE_192) 1928 aes_control |= SSS_AES_KEY_SIZE_192; 1929 else if (dev->ctx->keylen == AES_KEYSIZE_256) 1930 aes_control |= SSS_AES_KEY_SIZE_256; 1931 1932 aes_control |= SSS_AES_FIFO_MODE; 1933 1934 /* as a variant it is possible to use byte swapping on DMA side */ 1935 aes_control |= SSS_AES_BYTESWAP_DI 1936 | SSS_AES_BYTESWAP_DO 1937 | SSS_AES_BYTESWAP_IV 1938 | SSS_AES_BYTESWAP_KEY 1939 | SSS_AES_BYTESWAP_CNT; 1940 1941 spin_lock_irqsave(&dev->lock, flags); 1942 1943 SSS_WRITE(dev, FCINTENCLR, 1944 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); 1945 SSS_WRITE(dev, FCFIFOCTRL, 0x00); 1946 1947 err = s5p_set_indata_start(dev, req); 1948 if (err) 1949 goto indata_error; 1950 1951 err = s5p_set_outdata_start(dev, req); 1952 if (err) 1953 goto outdata_error; 1954 1955 SSS_AES_WRITE(dev, AES_CONTROL, aes_control); 1956 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen); 1957 1958 s5p_set_dma_indata(dev, dev->sg_src); 1959 s5p_set_dma_outdata(dev, dev->sg_dst); 1960 1961 SSS_WRITE(dev, FCINTENSET, 1962 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); 1963 1964 spin_unlock_irqrestore(&dev->lock, flags); 1965 1966 return; 1967 1968 outdata_error: 1969 s5p_unset_indata(dev); 1970 1971 indata_error: 1972 s5p_sg_done(dev); 1973 dev->busy = false; 1974 spin_unlock_irqrestore(&dev->lock, flags); 1975 s5p_aes_complete(req, err); 1976 } 1977 1978 static void s5p_tasklet_cb(unsigned long data) 1979 { 1980 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; 1981 struct crypto_async_request *async_req, *backlog; 1982 struct s5p_aes_reqctx *reqctx; 1983 unsigned long flags; 1984 1985 spin_lock_irqsave(&dev->lock, flags); 1986 backlog = crypto_get_backlog(&dev->queue); 1987 async_req = crypto_dequeue_request(&dev->queue); 1988 1989 if (!async_req) { 1990 dev->busy = false; 1991 spin_unlock_irqrestore(&dev->lock, flags); 1992 return; 1993 } 1994 spin_unlock_irqrestore(&dev->lock, flags); 1995 1996 if (backlog) 1997 backlog->complete(backlog, -EINPROGRESS); 1998 1999 dev->req = skcipher_request_cast(async_req); 2000 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); 2001 reqctx = skcipher_request_ctx(dev->req); 2002 2003 s5p_aes_crypt_start(dev, reqctx->mode); 2004 } 2005 2006 static int s5p_aes_handle_req(struct s5p_aes_dev *dev, 2007 struct skcipher_request *req) 2008 { 2009 unsigned long flags; 2010 int err; 2011 2012 spin_lock_irqsave(&dev->lock, flags); 2013 err = crypto_enqueue_request(&dev->queue, &req->base); 2014 if (dev->busy) { 2015 spin_unlock_irqrestore(&dev->lock, flags); 2016 return err; 2017 } 2018 dev->busy = true; 2019 2020 spin_unlock_irqrestore(&dev->lock, flags); 2021 2022 tasklet_schedule(&dev->tasklet); 2023 2024 return err; 2025 } 2026 2027 static int s5p_aes_crypt(struct skcipher_request *req, unsigned long mode) 2028 { 2029 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 2030 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 2031 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2032 struct s5p_aes_dev *dev = ctx->dev; 2033 2034 if (!req->cryptlen) 2035 return 0; 2036 2037 if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE) && 2038 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) { 2039 dev_dbg(dev->dev, "request size is not exact amount of AES blocks\n"); 2040 return -EINVAL; 2041 } 2042 2043 reqctx->mode = mode; 2044 2045 return s5p_aes_handle_req(dev, req); 2046 } 2047 2048 static int s5p_aes_setkey(struct crypto_skcipher *cipher, 2049 const u8 *key, unsigned int keylen) 2050 { 2051 struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); 2052 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); 2053 2054 if (keylen != AES_KEYSIZE_128 && 2055 keylen != AES_KEYSIZE_192 && 2056 keylen != AES_KEYSIZE_256) 2057 return -EINVAL; 2058 2059 memcpy(ctx->aes_key, key, keylen); 2060 ctx->keylen = keylen; 2061 2062 return 0; 2063 } 2064 2065 static int s5p_aes_ecb_encrypt(struct skcipher_request *req) 2066 { 2067 return s5p_aes_crypt(req, 0); 2068 } 2069 2070 static int s5p_aes_ecb_decrypt(struct skcipher_request *req) 2071 { 2072 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); 2073 } 2074 2075 static int s5p_aes_cbc_encrypt(struct skcipher_request *req) 2076 { 2077 return s5p_aes_crypt(req, FLAGS_AES_CBC); 2078 } 2079 2080 static int s5p_aes_cbc_decrypt(struct skcipher_request *req) 2081 { 2082 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); 2083 } 2084 2085 static int s5p_aes_ctr_crypt(struct skcipher_request *req) 2086 { 2087 return s5p_aes_crypt(req, FLAGS_AES_CTR); 2088 } 2089 2090 static int s5p_aes_init_tfm(struct crypto_skcipher *tfm) 2091 { 2092 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2093 2094 ctx->dev = s5p_dev; 2095 crypto_skcipher_set_reqsize(tfm, sizeof(struct s5p_aes_reqctx)); 2096 2097 return 0; 2098 } 2099 2100 static struct skcipher_alg algs[] = { 2101 { 2102 .base.cra_name = "ecb(aes)", 2103 .base.cra_driver_name = "ecb-aes-s5p", 2104 .base.cra_priority = 100, 2105 .base.cra_flags = CRYPTO_ALG_ASYNC | 2106 CRYPTO_ALG_KERN_DRIVER_ONLY, 2107 .base.cra_blocksize = AES_BLOCK_SIZE, 2108 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2109 .base.cra_alignmask = 0x0f, 2110 .base.cra_module = THIS_MODULE, 2111 2112 .min_keysize = AES_MIN_KEY_SIZE, 2113 .max_keysize = AES_MAX_KEY_SIZE, 2114 .setkey = s5p_aes_setkey, 2115 .encrypt = s5p_aes_ecb_encrypt, 2116 .decrypt = s5p_aes_ecb_decrypt, 2117 .init = s5p_aes_init_tfm, 2118 }, 2119 { 2120 .base.cra_name = "cbc(aes)", 2121 .base.cra_driver_name = "cbc-aes-s5p", 2122 .base.cra_priority = 100, 2123 .base.cra_flags = CRYPTO_ALG_ASYNC | 2124 CRYPTO_ALG_KERN_DRIVER_ONLY, 2125 .base.cra_blocksize = AES_BLOCK_SIZE, 2126 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2127 .base.cra_alignmask = 0x0f, 2128 .base.cra_module = THIS_MODULE, 2129 2130 .min_keysize = AES_MIN_KEY_SIZE, 2131 .max_keysize = AES_MAX_KEY_SIZE, 2132 .ivsize = AES_BLOCK_SIZE, 2133 .setkey = s5p_aes_setkey, 2134 .encrypt = s5p_aes_cbc_encrypt, 2135 .decrypt = s5p_aes_cbc_decrypt, 2136 .init = s5p_aes_init_tfm, 2137 }, 2138 { 2139 .base.cra_name = "ctr(aes)", 2140 .base.cra_driver_name = "ctr-aes-s5p", 2141 .base.cra_priority = 100, 2142 .base.cra_flags = CRYPTO_ALG_ASYNC | 2143 CRYPTO_ALG_KERN_DRIVER_ONLY, 2144 .base.cra_blocksize = 1, 2145 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2146 .base.cra_alignmask = 0x0f, 2147 .base.cra_module = THIS_MODULE, 2148 2149 .min_keysize = AES_MIN_KEY_SIZE, 2150 .max_keysize = AES_MAX_KEY_SIZE, 2151 .ivsize = AES_BLOCK_SIZE, 2152 .setkey = s5p_aes_setkey, 2153 .encrypt = s5p_aes_ctr_crypt, 2154 .decrypt = s5p_aes_ctr_crypt, 2155 .init = s5p_aes_init_tfm, 2156 }, 2157 }; 2158 2159 static int s5p_aes_probe(struct platform_device *pdev) 2160 { 2161 struct device *dev = &pdev->dev; 2162 int i, j, err = -ENODEV; 2163 const struct samsung_aes_variant *variant; 2164 struct s5p_aes_dev *pdata; 2165 struct resource *res; 2166 unsigned int hash_i; 2167 2168 if (s5p_dev) 2169 return -EEXIST; 2170 2171 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2172 if (!pdata) 2173 return -ENOMEM; 2174 2175 variant = find_s5p_sss_version(pdev); 2176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2177 2178 /* 2179 * Note: HASH and PRNG uses the same registers in secss, avoid 2180 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG 2181 * is enabled in config. We need larger size for HASH registers in 2182 * secss, current describe only AES/DES 2183 */ 2184 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) { 2185 if (variant == &exynos_aes_data) { 2186 res->end += 0x300; 2187 pdata->use_hash = true; 2188 } 2189 } 2190 2191 pdata->res = res; 2192 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); 2193 if (IS_ERR(pdata->ioaddr)) { 2194 if (!pdata->use_hash) 2195 return PTR_ERR(pdata->ioaddr); 2196 /* try AES without HASH */ 2197 res->end -= 0x300; 2198 pdata->use_hash = false; 2199 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); 2200 if (IS_ERR(pdata->ioaddr)) 2201 return PTR_ERR(pdata->ioaddr); 2202 } 2203 2204 pdata->clk = devm_clk_get(dev, variant->clk_names[0]); 2205 if (IS_ERR(pdata->clk)) 2206 return dev_err_probe(dev, PTR_ERR(pdata->clk), 2207 "failed to find secss clock %s\n", 2208 variant->clk_names[0]); 2209 2210 err = clk_prepare_enable(pdata->clk); 2211 if (err < 0) { 2212 dev_err(dev, "Enabling clock %s failed, err %d\n", 2213 variant->clk_names[0], err); 2214 return err; 2215 } 2216 2217 if (variant->clk_names[1]) { 2218 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]); 2219 if (IS_ERR(pdata->pclk)) { 2220 err = dev_err_probe(dev, PTR_ERR(pdata->pclk), 2221 "failed to find clock %s\n", 2222 variant->clk_names[1]); 2223 goto err_clk; 2224 } 2225 2226 err = clk_prepare_enable(pdata->pclk); 2227 if (err < 0) { 2228 dev_err(dev, "Enabling clock %s failed, err %d\n", 2229 variant->clk_names[0], err); 2230 goto err_clk; 2231 } 2232 } else { 2233 pdata->pclk = NULL; 2234 } 2235 2236 spin_lock_init(&pdata->lock); 2237 spin_lock_init(&pdata->hash_lock); 2238 2239 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; 2240 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset; 2241 2242 pdata->irq_fc = platform_get_irq(pdev, 0); 2243 if (pdata->irq_fc < 0) { 2244 err = pdata->irq_fc; 2245 dev_warn(dev, "feed control interrupt is not available.\n"); 2246 goto err_irq; 2247 } 2248 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL, 2249 s5p_aes_interrupt, IRQF_ONESHOT, 2250 pdev->name, pdev); 2251 if (err < 0) { 2252 dev_warn(dev, "feed control interrupt is not available.\n"); 2253 goto err_irq; 2254 } 2255 2256 pdata->busy = false; 2257 pdata->dev = dev; 2258 platform_set_drvdata(pdev, pdata); 2259 s5p_dev = pdata; 2260 2261 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); 2262 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); 2263 2264 for (i = 0; i < ARRAY_SIZE(algs); i++) { 2265 err = crypto_register_skcipher(&algs[i]); 2266 if (err) 2267 goto err_algs; 2268 } 2269 2270 if (pdata->use_hash) { 2271 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb, 2272 (unsigned long)pdata); 2273 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH); 2274 2275 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256); 2276 hash_i++) { 2277 struct ahash_alg *alg; 2278 2279 alg = &algs_sha1_md5_sha256[hash_i]; 2280 err = crypto_register_ahash(alg); 2281 if (err) { 2282 dev_err(dev, "can't register '%s': %d\n", 2283 alg->halg.base.cra_driver_name, err); 2284 goto err_hash; 2285 } 2286 } 2287 } 2288 2289 dev_info(dev, "s5p-sss driver registered\n"); 2290 2291 return 0; 2292 2293 err_hash: 2294 for (j = hash_i - 1; j >= 0; j--) 2295 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]); 2296 2297 tasklet_kill(&pdata->hash_tasklet); 2298 res->end -= 0x300; 2299 2300 err_algs: 2301 if (i < ARRAY_SIZE(algs)) 2302 dev_err(dev, "can't register '%s': %d\n", algs[i].base.cra_name, 2303 err); 2304 2305 for (j = 0; j < i; j++) 2306 crypto_unregister_skcipher(&algs[j]); 2307 2308 tasklet_kill(&pdata->tasklet); 2309 2310 err_irq: 2311 clk_disable_unprepare(pdata->pclk); 2312 2313 err_clk: 2314 clk_disable_unprepare(pdata->clk); 2315 s5p_dev = NULL; 2316 2317 return err; 2318 } 2319 2320 static int s5p_aes_remove(struct platform_device *pdev) 2321 { 2322 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); 2323 int i; 2324 2325 if (!pdata) 2326 return -ENODEV; 2327 2328 for (i = 0; i < ARRAY_SIZE(algs); i++) 2329 crypto_unregister_skcipher(&algs[i]); 2330 2331 tasklet_kill(&pdata->tasklet); 2332 if (pdata->use_hash) { 2333 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--) 2334 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]); 2335 2336 pdata->res->end -= 0x300; 2337 tasklet_kill(&pdata->hash_tasklet); 2338 pdata->use_hash = false; 2339 } 2340 2341 clk_disable_unprepare(pdata->pclk); 2342 2343 clk_disable_unprepare(pdata->clk); 2344 s5p_dev = NULL; 2345 2346 return 0; 2347 } 2348 2349 static struct platform_driver s5p_aes_crypto = { 2350 .probe = s5p_aes_probe, 2351 .remove = s5p_aes_remove, 2352 .driver = { 2353 .name = "s5p-secss", 2354 .of_match_table = s5p_sss_dt_match, 2355 }, 2356 }; 2357 2358 module_platform_driver(s5p_aes_crypto); 2359 2360 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); 2361 MODULE_LICENSE("GPL v2"); 2362 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); 2363 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>"); 2364