xref: /openbmc/linux/drivers/crypto/qcom-rng.c (revision e65e175b)
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-18 Linaro Limited
3 //
4 // Based on msm-rng.c and downstream driver
5 
6 #include <crypto/internal/rng.h>
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/crypto.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 
17 /* Device specific register offsets */
18 #define PRNG_DATA_OUT		0x0000
19 #define PRNG_STATUS		0x0004
20 #define PRNG_LFSR_CFG		0x0100
21 #define PRNG_CONFIG		0x0104
22 
23 /* Device specific register masks and config values */
24 #define PRNG_LFSR_CFG_MASK	0x0000ffff
25 #define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
26 #define PRNG_CONFIG_HW_ENABLE	BIT(1)
27 #define PRNG_STATUS_DATA_AVAIL	BIT(0)
28 
29 #define WORD_SZ			4
30 
31 struct qcom_rng {
32 	struct mutex lock;
33 	void __iomem *base;
34 	struct clk *clk;
35 	unsigned int skip_init;
36 };
37 
38 struct qcom_rng_ctx {
39 	struct qcom_rng *rng;
40 };
41 
42 static struct qcom_rng *qcom_rng_dev;
43 
44 static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
45 {
46 	unsigned int currsize = 0;
47 	u32 val;
48 	int ret;
49 
50 	/* read random data from hardware */
51 	do {
52 		ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
53 					 val & PRNG_STATUS_DATA_AVAIL,
54 					 200, 10000);
55 		if (ret)
56 			return ret;
57 
58 		val = readl_relaxed(rng->base + PRNG_DATA_OUT);
59 		if (!val)
60 			return -EINVAL;
61 
62 		if ((max - currsize) >= WORD_SZ) {
63 			memcpy(data, &val, WORD_SZ);
64 			data += WORD_SZ;
65 			currsize += WORD_SZ;
66 		} else {
67 			/* copy only remaining bytes */
68 			memcpy(data, &val, max - currsize);
69 			break;
70 		}
71 	} while (currsize < max);
72 
73 	return 0;
74 }
75 
76 static int qcom_rng_generate(struct crypto_rng *tfm,
77 			     const u8 *src, unsigned int slen,
78 			     u8 *dstn, unsigned int dlen)
79 {
80 	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
81 	struct qcom_rng *rng = ctx->rng;
82 	int ret;
83 
84 	ret = clk_prepare_enable(rng->clk);
85 	if (ret)
86 		return ret;
87 
88 	mutex_lock(&rng->lock);
89 
90 	ret = qcom_rng_read(rng, dstn, dlen);
91 
92 	mutex_unlock(&rng->lock);
93 	clk_disable_unprepare(rng->clk);
94 
95 	return ret;
96 }
97 
98 static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
99 			 unsigned int slen)
100 {
101 	return 0;
102 }
103 
104 static int qcom_rng_enable(struct qcom_rng *rng)
105 {
106 	u32 val;
107 	int ret;
108 
109 	ret = clk_prepare_enable(rng->clk);
110 	if (ret)
111 		return ret;
112 
113 	/* Enable PRNG only if it is not already enabled */
114 	val = readl_relaxed(rng->base + PRNG_CONFIG);
115 	if (val & PRNG_CONFIG_HW_ENABLE)
116 		goto already_enabled;
117 
118 	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
119 	val &= ~PRNG_LFSR_CFG_MASK;
120 	val |= PRNG_LFSR_CFG_CLOCKS;
121 	writel(val, rng->base + PRNG_LFSR_CFG);
122 
123 	val = readl_relaxed(rng->base + PRNG_CONFIG);
124 	val |= PRNG_CONFIG_HW_ENABLE;
125 	writel(val, rng->base + PRNG_CONFIG);
126 
127 already_enabled:
128 	clk_disable_unprepare(rng->clk);
129 
130 	return 0;
131 }
132 
133 static int qcom_rng_init(struct crypto_tfm *tfm)
134 {
135 	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
136 
137 	ctx->rng = qcom_rng_dev;
138 
139 	if (!ctx->rng->skip_init)
140 		return qcom_rng_enable(ctx->rng);
141 
142 	return 0;
143 }
144 
145 static struct rng_alg qcom_rng_alg = {
146 	.generate	= qcom_rng_generate,
147 	.seed		= qcom_rng_seed,
148 	.seedsize	= 0,
149 	.base		= {
150 		.cra_name		= "stdrng",
151 		.cra_driver_name	= "qcom-rng",
152 		.cra_flags		= CRYPTO_ALG_TYPE_RNG,
153 		.cra_priority		= 300,
154 		.cra_ctxsize		= sizeof(struct qcom_rng_ctx),
155 		.cra_module		= THIS_MODULE,
156 		.cra_init		= qcom_rng_init,
157 	}
158 };
159 
160 static int qcom_rng_probe(struct platform_device *pdev)
161 {
162 	struct qcom_rng *rng;
163 	int ret;
164 
165 	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
166 	if (!rng)
167 		return -ENOMEM;
168 
169 	platform_set_drvdata(pdev, rng);
170 	mutex_init(&rng->lock);
171 
172 	rng->base = devm_platform_ioremap_resource(pdev, 0);
173 	if (IS_ERR(rng->base))
174 		return PTR_ERR(rng->base);
175 
176 	/* ACPI systems have clk already on, so skip clk_get */
177 	if (!has_acpi_companion(&pdev->dev)) {
178 		rng->clk = devm_clk_get(&pdev->dev, "core");
179 		if (IS_ERR(rng->clk))
180 			return PTR_ERR(rng->clk);
181 	}
182 
183 
184 	rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
185 
186 	qcom_rng_dev = rng;
187 	ret = crypto_register_rng(&qcom_rng_alg);
188 	if (ret) {
189 		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
190 		qcom_rng_dev = NULL;
191 	}
192 
193 	return ret;
194 }
195 
196 static int qcom_rng_remove(struct platform_device *pdev)
197 {
198 	crypto_unregister_rng(&qcom_rng_alg);
199 
200 	qcom_rng_dev = NULL;
201 
202 	return 0;
203 }
204 
205 static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
206 	{ .id = "QCOM8160", .driver_data = 1 },
207 	{}
208 };
209 MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
210 
211 static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
212 	{ .compatible = "qcom,prng", .data = (void *)0},
213 	{ .compatible = "qcom,prng-ee", .data = (void *)1},
214 	{}
215 };
216 MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
217 
218 static struct platform_driver qcom_rng_driver = {
219 	.probe = qcom_rng_probe,
220 	.remove =  qcom_rng_remove,
221 	.driver = {
222 		.name = KBUILD_MODNAME,
223 		.of_match_table = of_match_ptr(qcom_rng_of_match),
224 		.acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
225 	}
226 };
227 module_platform_driver(qcom_rng_driver);
228 
229 MODULE_ALIAS("platform:" KBUILD_MODNAME);
230 MODULE_DESCRIPTION("Qualcomm random number generator driver");
231 MODULE_LICENSE("GPL v2");
232