1 /* 2 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <crypto/internal/hash.h> 17 18 #include "common.h" 19 #include "core.h" 20 #include "sha.h" 21 22 /* crypto hw padding constant for first operation */ 23 #define SHA_PADDING 64 24 #define SHA_PADDING_MASK (SHA_PADDING - 1) 25 26 static LIST_HEAD(ahash_algs); 27 28 static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = { 29 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0 30 }; 31 32 static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = { 33 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, 34 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7 35 }; 36 37 static void qce_ahash_done(void *data) 38 { 39 struct crypto_async_request *async_req = data; 40 struct ahash_request *req = ahash_request_cast(async_req); 41 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); 42 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 43 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 44 struct qce_device *qce = tmpl->qce; 45 struct qce_result_dump *result = qce->dma.result_buf; 46 unsigned int digestsize = crypto_ahash_digestsize(ahash); 47 int error; 48 u32 status; 49 50 error = qce_dma_terminate_all(&qce->dma); 51 if (error) 52 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error); 53 54 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 55 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 56 57 memcpy(rctx->digest, result->auth_iv, digestsize); 58 if (req->result) 59 memcpy(req->result, result->auth_iv, digestsize); 60 61 rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); 62 rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); 63 64 error = qce_check_status(qce, &status); 65 if (error < 0) 66 dev_dbg(qce->dev, "ahash operation error (%x)\n", status); 67 68 req->src = rctx->src_orig; 69 req->nbytes = rctx->nbytes_orig; 70 rctx->last_blk = false; 71 rctx->first_blk = false; 72 73 qce->async_req_done(tmpl->qce, error); 74 } 75 76 static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) 77 { 78 struct ahash_request *req = ahash_request_cast(async_req); 79 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 80 struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm); 81 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 82 struct qce_device *qce = tmpl->qce; 83 unsigned long flags = rctx->flags; 84 int ret; 85 86 if (IS_SHA_HMAC(flags)) { 87 rctx->authkey = ctx->authkey; 88 rctx->authklen = QCE_SHA_HMAC_KEY_SIZE; 89 } else if (IS_CMAC(flags)) { 90 rctx->authkey = ctx->authkey; 91 rctx->authklen = AES_KEYSIZE_128; 92 } 93 94 rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); 95 if (rctx->src_nents < 0) { 96 dev_err(qce->dev, "Invalid numbers of src SG.\n"); 97 return rctx->src_nents; 98 } 99 100 ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 101 if (ret < 0) 102 return ret; 103 104 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); 105 106 ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 107 if (ret < 0) 108 goto error_unmap_src; 109 110 ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents, 111 &rctx->result_sg, 1, qce_ahash_done, async_req); 112 if (ret) 113 goto error_unmap_dst; 114 115 qce_dma_issue_pending(&qce->dma); 116 117 ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0); 118 if (ret) 119 goto error_terminate; 120 121 return 0; 122 123 error_terminate: 124 qce_dma_terminate_all(&qce->dma); 125 error_unmap_dst: 126 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 127 error_unmap_src: 128 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 129 return ret; 130 } 131 132 static int qce_ahash_init(struct ahash_request *req) 133 { 134 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 135 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 136 const u32 *std_iv = tmpl->std_iv; 137 138 memset(rctx, 0, sizeof(*rctx)); 139 rctx->first_blk = true; 140 rctx->last_blk = false; 141 rctx->flags = tmpl->alg_flags; 142 memcpy(rctx->digest, std_iv, sizeof(rctx->digest)); 143 144 return 0; 145 } 146 147 static int qce_ahash_export(struct ahash_request *req, void *out) 148 { 149 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); 150 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 151 unsigned long flags = rctx->flags; 152 unsigned int digestsize = crypto_ahash_digestsize(ahash); 153 unsigned int blocksize = 154 crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash)); 155 156 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) { 157 struct sha1_state *out_state = out; 158 159 out_state->count = rctx->count; 160 qce_cpu_to_be32p_array((__be32 *)out_state->state, 161 rctx->digest, digestsize); 162 memcpy(out_state->buffer, rctx->buf, blocksize); 163 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) { 164 struct sha256_state *out_state = out; 165 166 out_state->count = rctx->count; 167 qce_cpu_to_be32p_array((__be32 *)out_state->state, 168 rctx->digest, digestsize); 169 memcpy(out_state->buf, rctx->buf, blocksize); 170 } else { 171 return -EINVAL; 172 } 173 174 return 0; 175 } 176 177 static int qce_import_common(struct ahash_request *req, u64 in_count, 178 const u32 *state, const u8 *buffer, bool hmac) 179 { 180 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); 181 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 182 unsigned int digestsize = crypto_ahash_digestsize(ahash); 183 unsigned int blocksize; 184 u64 count = in_count; 185 186 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash)); 187 rctx->count = in_count; 188 memcpy(rctx->buf, buffer, blocksize); 189 190 if (in_count <= blocksize) { 191 rctx->first_blk = 1; 192 } else { 193 rctx->first_blk = 0; 194 /* 195 * For HMAC, there is a hardware padding done when first block 196 * is set. Therefore the byte_count must be incremened by 64 197 * after the first block operation. 198 */ 199 if (hmac) 200 count += SHA_PADDING; 201 } 202 203 rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK); 204 rctx->byte_count[1] = (__force __be32)(count >> 32); 205 qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state, 206 digestsize); 207 rctx->buflen = (unsigned int)(in_count & (blocksize - 1)); 208 209 return 0; 210 } 211 212 static int qce_ahash_import(struct ahash_request *req, const void *in) 213 { 214 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 215 unsigned long flags = rctx->flags; 216 bool hmac = IS_SHA_HMAC(flags); 217 int ret = -EINVAL; 218 219 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) { 220 const struct sha1_state *state = in; 221 222 ret = qce_import_common(req, state->count, state->state, 223 state->buffer, hmac); 224 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) { 225 const struct sha256_state *state = in; 226 227 ret = qce_import_common(req, state->count, state->state, 228 state->buf, hmac); 229 } 230 231 return ret; 232 } 233 234 static int qce_ahash_update(struct ahash_request *req) 235 { 236 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 237 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 238 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 239 struct qce_device *qce = tmpl->qce; 240 struct scatterlist *sg_last, *sg; 241 unsigned int total, len; 242 unsigned int hash_later; 243 unsigned int nbytes; 244 unsigned int blocksize; 245 246 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); 247 rctx->count += req->nbytes; 248 249 /* check for buffer from previous updates and append it */ 250 total = req->nbytes + rctx->buflen; 251 252 if (total <= blocksize) { 253 scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src, 254 0, req->nbytes, 0); 255 rctx->buflen += req->nbytes; 256 return 0; 257 } 258 259 /* save the original req structure fields */ 260 rctx->src_orig = req->src; 261 rctx->nbytes_orig = req->nbytes; 262 263 /* 264 * if we have data from previous update copy them on buffer. The old 265 * data will be combined with current request bytes. 266 */ 267 if (rctx->buflen) 268 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen); 269 270 /* calculate how many bytes will be hashed later */ 271 hash_later = total % blocksize; 272 if (hash_later) { 273 unsigned int src_offset = req->nbytes - hash_later; 274 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset, 275 hash_later, 0); 276 } 277 278 /* here nbytes is multiple of blocksize */ 279 nbytes = total - hash_later; 280 281 len = rctx->buflen; 282 sg = sg_last = req->src; 283 284 while (len < nbytes && sg) { 285 if (len + sg_dma_len(sg) > nbytes) 286 break; 287 len += sg_dma_len(sg); 288 sg_last = sg; 289 sg = sg_next(sg); 290 } 291 292 if (!sg_last) 293 return -EINVAL; 294 295 sg_mark_end(sg_last); 296 297 if (rctx->buflen) { 298 sg_init_table(rctx->sg, 2); 299 sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen); 300 sg_chain(rctx->sg, 2, req->src); 301 req->src = rctx->sg; 302 } 303 304 req->nbytes = nbytes; 305 rctx->buflen = hash_later; 306 307 return qce->async_req_enqueue(tmpl->qce, &req->base); 308 } 309 310 static int qce_ahash_final(struct ahash_request *req) 311 { 312 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 313 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 314 struct qce_device *qce = tmpl->qce; 315 316 if (!rctx->buflen) 317 return 0; 318 319 rctx->last_blk = true; 320 321 rctx->src_orig = req->src; 322 rctx->nbytes_orig = req->nbytes; 323 324 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen); 325 sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen); 326 327 req->src = rctx->sg; 328 req->nbytes = rctx->buflen; 329 330 return qce->async_req_enqueue(tmpl->qce, &req->base); 331 } 332 333 static int qce_ahash_digest(struct ahash_request *req) 334 { 335 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 336 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 337 struct qce_device *qce = tmpl->qce; 338 int ret; 339 340 ret = qce_ahash_init(req); 341 if (ret) 342 return ret; 343 344 rctx->src_orig = req->src; 345 rctx->nbytes_orig = req->nbytes; 346 rctx->first_blk = true; 347 rctx->last_blk = true; 348 349 return qce->async_req_enqueue(tmpl->qce, &req->base); 350 } 351 352 static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, 353 unsigned int keylen) 354 { 355 unsigned int digestsize = crypto_ahash_digestsize(tfm); 356 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base); 357 struct crypto_wait wait; 358 struct ahash_request *req; 359 struct scatterlist sg; 360 unsigned int blocksize; 361 struct crypto_ahash *ahash_tfm; 362 u8 *buf; 363 int ret; 364 const char *alg_name; 365 366 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); 367 memset(ctx->authkey, 0, sizeof(ctx->authkey)); 368 369 if (keylen <= blocksize) { 370 memcpy(ctx->authkey, key, keylen); 371 return 0; 372 } 373 374 if (digestsize == SHA1_DIGEST_SIZE) 375 alg_name = "sha1-qce"; 376 else if (digestsize == SHA256_DIGEST_SIZE) 377 alg_name = "sha256-qce"; 378 else 379 return -EINVAL; 380 381 ahash_tfm = crypto_alloc_ahash(alg_name, CRYPTO_ALG_TYPE_AHASH, 382 CRYPTO_ALG_TYPE_AHASH_MASK); 383 if (IS_ERR(ahash_tfm)) 384 return PTR_ERR(ahash_tfm); 385 386 req = ahash_request_alloc(ahash_tfm, GFP_KERNEL); 387 if (!req) { 388 ret = -ENOMEM; 389 goto err_free_ahash; 390 } 391 392 crypto_init_wait(&wait); 393 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, 394 crypto_req_done, &wait); 395 crypto_ahash_clear_flags(ahash_tfm, ~0); 396 397 buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL); 398 if (!buf) { 399 ret = -ENOMEM; 400 goto err_free_req; 401 } 402 403 memcpy(buf, key, keylen); 404 sg_init_one(&sg, buf, keylen); 405 ahash_request_set_crypt(req, &sg, ctx->authkey, keylen); 406 407 ret = crypto_wait_req(crypto_ahash_digest(req), &wait); 408 if (ret) 409 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 410 411 kfree(buf); 412 err_free_req: 413 ahash_request_free(req); 414 err_free_ahash: 415 crypto_free_ahash(ahash_tfm); 416 return ret; 417 } 418 419 static int qce_ahash_cra_init(struct crypto_tfm *tfm) 420 { 421 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); 422 struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm); 423 424 crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx)); 425 memset(ctx, 0, sizeof(*ctx)); 426 return 0; 427 } 428 429 struct qce_ahash_def { 430 unsigned long flags; 431 const char *name; 432 const char *drv_name; 433 unsigned int digestsize; 434 unsigned int blocksize; 435 unsigned int statesize; 436 const u32 *std_iv; 437 }; 438 439 static const struct qce_ahash_def ahash_def[] = { 440 { 441 .flags = QCE_HASH_SHA1, 442 .name = "sha1", 443 .drv_name = "sha1-qce", 444 .digestsize = SHA1_DIGEST_SIZE, 445 .blocksize = SHA1_BLOCK_SIZE, 446 .statesize = sizeof(struct sha1_state), 447 .std_iv = std_iv_sha1, 448 }, 449 { 450 .flags = QCE_HASH_SHA256, 451 .name = "sha256", 452 .drv_name = "sha256-qce", 453 .digestsize = SHA256_DIGEST_SIZE, 454 .blocksize = SHA256_BLOCK_SIZE, 455 .statesize = sizeof(struct sha256_state), 456 .std_iv = std_iv_sha256, 457 }, 458 { 459 .flags = QCE_HASH_SHA1_HMAC, 460 .name = "hmac(sha1)", 461 .drv_name = "hmac-sha1-qce", 462 .digestsize = SHA1_DIGEST_SIZE, 463 .blocksize = SHA1_BLOCK_SIZE, 464 .statesize = sizeof(struct sha1_state), 465 .std_iv = std_iv_sha1, 466 }, 467 { 468 .flags = QCE_HASH_SHA256_HMAC, 469 .name = "hmac(sha256)", 470 .drv_name = "hmac-sha256-qce", 471 .digestsize = SHA256_DIGEST_SIZE, 472 .blocksize = SHA256_BLOCK_SIZE, 473 .statesize = sizeof(struct sha256_state), 474 .std_iv = std_iv_sha256, 475 }, 476 }; 477 478 static int qce_ahash_register_one(const struct qce_ahash_def *def, 479 struct qce_device *qce) 480 { 481 struct qce_alg_template *tmpl; 482 struct ahash_alg *alg; 483 struct crypto_alg *base; 484 int ret; 485 486 tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL); 487 if (!tmpl) 488 return -ENOMEM; 489 490 tmpl->std_iv = def->std_iv; 491 492 alg = &tmpl->alg.ahash; 493 alg->init = qce_ahash_init; 494 alg->update = qce_ahash_update; 495 alg->final = qce_ahash_final; 496 alg->digest = qce_ahash_digest; 497 alg->export = qce_ahash_export; 498 alg->import = qce_ahash_import; 499 if (IS_SHA_HMAC(def->flags)) 500 alg->setkey = qce_ahash_hmac_setkey; 501 alg->halg.digestsize = def->digestsize; 502 alg->halg.statesize = def->statesize; 503 504 base = &alg->halg.base; 505 base->cra_blocksize = def->blocksize; 506 base->cra_priority = 300; 507 base->cra_flags = CRYPTO_ALG_ASYNC; 508 base->cra_ctxsize = sizeof(struct qce_sha_ctx); 509 base->cra_alignmask = 0; 510 base->cra_module = THIS_MODULE; 511 base->cra_init = qce_ahash_cra_init; 512 INIT_LIST_HEAD(&base->cra_list); 513 514 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); 515 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", 516 def->drv_name); 517 518 INIT_LIST_HEAD(&tmpl->entry); 519 tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH; 520 tmpl->alg_flags = def->flags; 521 tmpl->qce = qce; 522 523 ret = crypto_register_ahash(alg); 524 if (ret) { 525 kfree(tmpl); 526 dev_err(qce->dev, "%s registration failed\n", base->cra_name); 527 return ret; 528 } 529 530 list_add_tail(&tmpl->entry, &ahash_algs); 531 dev_dbg(qce->dev, "%s is registered\n", base->cra_name); 532 return 0; 533 } 534 535 static void qce_ahash_unregister(struct qce_device *qce) 536 { 537 struct qce_alg_template *tmpl, *n; 538 539 list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) { 540 crypto_unregister_ahash(&tmpl->alg.ahash); 541 list_del(&tmpl->entry); 542 kfree(tmpl); 543 } 544 } 545 546 static int qce_ahash_register(struct qce_device *qce) 547 { 548 int ret, i; 549 550 for (i = 0; i < ARRAY_SIZE(ahash_def); i++) { 551 ret = qce_ahash_register_one(&ahash_def[i], qce); 552 if (ret) 553 goto err; 554 } 555 556 return 0; 557 err: 558 qce_ahash_unregister(qce); 559 return ret; 560 } 561 562 const struct qce_algo_ops ahash_ops = { 563 .type = CRYPTO_ALG_TYPE_AHASH, 564 .register_algs = qce_ahash_register, 565 .unregister_algs = qce_ahash_unregister, 566 .async_req_handle = qce_ahash_async_req_handle, 567 }; 568