1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/interrupt.h> 8 #include <linux/types.h> 9 #include <crypto/scatterwalk.h> 10 #include <crypto/sha.h> 11 12 #include "cipher.h" 13 #include "common.h" 14 #include "core.h" 15 #include "regs-v5.h" 16 #include "sha.h" 17 18 #define QCE_SECTOR_SIZE 512 19 20 static inline u32 qce_read(struct qce_device *qce, u32 offset) 21 { 22 return readl(qce->base + offset); 23 } 24 25 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) 26 { 27 writel(val, qce->base + offset); 28 } 29 30 static inline void qce_write_array(struct qce_device *qce, u32 offset, 31 const u32 *val, unsigned int len) 32 { 33 int i; 34 35 for (i = 0; i < len; i++) 36 qce_write(qce, offset + i * sizeof(u32), val[i]); 37 } 38 39 static inline void 40 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) 41 { 42 int i; 43 44 for (i = 0; i < len; i++) 45 qce_write(qce, offset + i * sizeof(u32), 0); 46 } 47 48 static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) 49 { 50 u32 cfg = 0; 51 52 if (IS_AES(flags)) { 53 if (aes_key_size == AES_KEYSIZE_128) 54 cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; 55 else if (aes_key_size == AES_KEYSIZE_256) 56 cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; 57 } 58 59 if (IS_AES(flags)) 60 cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; 61 else if (IS_DES(flags) || IS_3DES(flags)) 62 cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT; 63 64 if (IS_DES(flags)) 65 cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT; 66 67 if (IS_3DES(flags)) 68 cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT; 69 70 switch (flags & QCE_MODE_MASK) { 71 case QCE_MODE_ECB: 72 cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT; 73 break; 74 case QCE_MODE_CBC: 75 cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; 76 break; 77 case QCE_MODE_CTR: 78 cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; 79 break; 80 case QCE_MODE_XTS: 81 cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; 82 break; 83 case QCE_MODE_CCM: 84 cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; 85 cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; 86 break; 87 default: 88 return ~0; 89 } 90 91 return cfg; 92 } 93 94 static u32 qce_auth_cfg(unsigned long flags, u32 key_size) 95 { 96 u32 cfg = 0; 97 98 if (IS_AES(flags) && (IS_CCM(flags) || IS_CMAC(flags))) 99 cfg |= AUTH_ALG_AES << AUTH_ALG_SHIFT; 100 else 101 cfg |= AUTH_ALG_SHA << AUTH_ALG_SHIFT; 102 103 if (IS_CCM(flags) || IS_CMAC(flags)) { 104 if (key_size == AES_KEYSIZE_128) 105 cfg |= AUTH_KEY_SZ_AES128 << AUTH_KEY_SIZE_SHIFT; 106 else if (key_size == AES_KEYSIZE_256) 107 cfg |= AUTH_KEY_SZ_AES256 << AUTH_KEY_SIZE_SHIFT; 108 } 109 110 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) 111 cfg |= AUTH_SIZE_SHA1 << AUTH_SIZE_SHIFT; 112 else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) 113 cfg |= AUTH_SIZE_SHA256 << AUTH_SIZE_SHIFT; 114 else if (IS_CMAC(flags)) 115 cfg |= AUTH_SIZE_ENUM_16_BYTES << AUTH_SIZE_SHIFT; 116 117 if (IS_SHA1(flags) || IS_SHA256(flags)) 118 cfg |= AUTH_MODE_HASH << AUTH_MODE_SHIFT; 119 else if (IS_SHA1_HMAC(flags) || IS_SHA256_HMAC(flags) || 120 IS_CBC(flags) || IS_CTR(flags)) 121 cfg |= AUTH_MODE_HMAC << AUTH_MODE_SHIFT; 122 else if (IS_AES(flags) && IS_CCM(flags)) 123 cfg |= AUTH_MODE_CCM << AUTH_MODE_SHIFT; 124 else if (IS_AES(flags) && IS_CMAC(flags)) 125 cfg |= AUTH_MODE_CMAC << AUTH_MODE_SHIFT; 126 127 if (IS_SHA(flags) || IS_SHA_HMAC(flags)) 128 cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; 129 130 if (IS_CCM(flags)) 131 cfg |= QCE_MAX_NONCE_WORDS << AUTH_NONCE_NUM_WORDS_SHIFT; 132 133 if (IS_CBC(flags) || IS_CTR(flags) || IS_CCM(flags) || 134 IS_CMAC(flags)) 135 cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT); 136 137 return cfg; 138 } 139 140 static u32 qce_config_reg(struct qce_device *qce, int little) 141 { 142 u32 beats = (qce->burst_size >> 3) - 1; 143 u32 pipe_pair = qce->pipe_pair_id; 144 u32 config; 145 146 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; 147 config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | 148 BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); 149 config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; 150 config &= ~HIGH_SPD_EN_N_SHIFT; 151 152 if (little) 153 config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); 154 155 return config; 156 } 157 158 void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) 159 { 160 __be32 *d = dst; 161 const u8 *s = src; 162 unsigned int n; 163 164 n = len / sizeof(u32); 165 for (; n > 0; n--) { 166 *d = cpu_to_be32p((const __u32 *) s); 167 s += sizeof(__u32); 168 d++; 169 } 170 } 171 172 static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) 173 { 174 u8 swap[QCE_AES_IV_LENGTH]; 175 u32 i, j; 176 177 if (ivsize > QCE_AES_IV_LENGTH) 178 return; 179 180 memset(swap, 0, QCE_AES_IV_LENGTH); 181 182 for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1; 183 i < QCE_AES_IV_LENGTH; i++, j--) 184 swap[i] = src[j]; 185 186 qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); 187 } 188 189 static void qce_xtskey(struct qce_device *qce, const u8 *enckey, 190 unsigned int enckeylen, unsigned int cryptlen) 191 { 192 u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; 193 unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); 194 unsigned int xtsdusize; 195 196 qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, 197 enckeylen / 2); 198 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); 199 200 /* xts du size 512B */ 201 xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen); 202 qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); 203 } 204 205 static void qce_setup_config(struct qce_device *qce) 206 { 207 u32 config; 208 209 /* get big endianness */ 210 config = qce_config_reg(qce, 0); 211 212 /* clear status */ 213 qce_write(qce, REG_STATUS, 0); 214 qce_write(qce, REG_CONFIG, config); 215 } 216 217 static inline void qce_crypto_go(struct qce_device *qce) 218 { 219 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); 220 } 221 222 static int qce_setup_regs_ahash(struct crypto_async_request *async_req, 223 u32 totallen, u32 offset) 224 { 225 struct ahash_request *req = ahash_request_cast(async_req); 226 struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm); 227 struct qce_sha_reqctx *rctx = ahash_request_ctx(req); 228 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 229 struct qce_device *qce = tmpl->qce; 230 unsigned int digestsize = crypto_ahash_digestsize(ahash); 231 unsigned int blocksize = crypto_tfm_alg_blocksize(async_req->tfm); 232 __be32 auth[SHA256_DIGEST_SIZE / sizeof(__be32)] = {0}; 233 __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; 234 u32 auth_cfg = 0, config; 235 unsigned int iv_words; 236 237 /* if not the last, the size has to be on the block boundary */ 238 if (!rctx->last_blk && req->nbytes % blocksize) 239 return -EINVAL; 240 241 qce_setup_config(qce); 242 243 if (IS_CMAC(rctx->flags)) { 244 qce_write(qce, REG_AUTH_SEG_CFG, 0); 245 qce_write(qce, REG_ENCR_SEG_CFG, 0); 246 qce_write(qce, REG_ENCR_SEG_SIZE, 0); 247 qce_clear_array(qce, REG_AUTH_IV0, 16); 248 qce_clear_array(qce, REG_AUTH_KEY0, 16); 249 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); 250 251 auth_cfg = qce_auth_cfg(rctx->flags, rctx->authklen); 252 } 253 254 if (IS_SHA_HMAC(rctx->flags) || IS_CMAC(rctx->flags)) { 255 u32 authkey_words = rctx->authklen / sizeof(u32); 256 257 qce_cpu_to_be32p_array(mackey, rctx->authkey, rctx->authklen); 258 qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey, 259 authkey_words); 260 } 261 262 if (IS_CMAC(rctx->flags)) 263 goto go_proc; 264 265 if (rctx->first_blk) 266 memcpy(auth, rctx->digest, digestsize); 267 else 268 qce_cpu_to_be32p_array(auth, rctx->digest, digestsize); 269 270 iv_words = (IS_SHA1(rctx->flags) || IS_SHA1_HMAC(rctx->flags)) ? 5 : 8; 271 qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words); 272 273 if (rctx->first_blk) 274 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); 275 else 276 qce_write_array(qce, REG_AUTH_BYTECNT0, 277 (u32 *)rctx->byte_count, 2); 278 279 auth_cfg = qce_auth_cfg(rctx->flags, 0); 280 281 if (rctx->last_blk) 282 auth_cfg |= BIT(AUTH_LAST_SHIFT); 283 else 284 auth_cfg &= ~BIT(AUTH_LAST_SHIFT); 285 286 if (rctx->first_blk) 287 auth_cfg |= BIT(AUTH_FIRST_SHIFT); 288 else 289 auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); 290 291 go_proc: 292 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); 293 qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); 294 qce_write(qce, REG_AUTH_SEG_START, 0); 295 qce_write(qce, REG_ENCR_SEG_CFG, 0); 296 qce_write(qce, REG_SEG_SIZE, req->nbytes); 297 298 /* get little endianness */ 299 config = qce_config_reg(qce, 1); 300 qce_write(qce, REG_CONFIG, config); 301 302 qce_crypto_go(qce); 303 304 return 0; 305 } 306 307 static int qce_setup_regs_ablkcipher(struct crypto_async_request *async_req, 308 u32 totallen, u32 offset) 309 { 310 struct ablkcipher_request *req = ablkcipher_request_cast(async_req); 311 struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req); 312 struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm); 313 struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm); 314 struct qce_device *qce = tmpl->qce; 315 __be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0}; 316 __be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0}; 317 unsigned int enckey_words, enciv_words; 318 unsigned int keylen; 319 u32 encr_cfg = 0, auth_cfg = 0, config; 320 unsigned int ivsize = rctx->ivsize; 321 unsigned long flags = rctx->flags; 322 323 qce_setup_config(qce); 324 325 if (IS_XTS(flags)) 326 keylen = ctx->enc_keylen / 2; 327 else 328 keylen = ctx->enc_keylen; 329 330 qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen); 331 enckey_words = keylen / sizeof(u32); 332 333 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); 334 335 encr_cfg = qce_encr_cfg(flags, keylen); 336 337 if (IS_DES(flags)) { 338 enciv_words = 2; 339 enckey_words = 2; 340 } else if (IS_3DES(flags)) { 341 enciv_words = 2; 342 enckey_words = 6; 343 } else if (IS_AES(flags)) { 344 if (IS_XTS(flags)) 345 qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen, 346 rctx->cryptlen); 347 enciv_words = 4; 348 } else { 349 return -EINVAL; 350 } 351 352 qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words); 353 354 if (!IS_ECB(flags)) { 355 if (IS_XTS(flags)) 356 qce_xts_swapiv(enciv, rctx->iv, ivsize); 357 else 358 qce_cpu_to_be32p_array(enciv, rctx->iv, ivsize); 359 360 qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words); 361 } 362 363 if (IS_ENCRYPT(flags)) 364 encr_cfg |= BIT(ENCODE_SHIFT); 365 366 qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); 367 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); 368 qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff); 369 370 if (IS_CTR(flags)) { 371 qce_write(qce, REG_CNTR_MASK, ~0); 372 qce_write(qce, REG_CNTR_MASK0, ~0); 373 qce_write(qce, REG_CNTR_MASK1, ~0); 374 qce_write(qce, REG_CNTR_MASK2, ~0); 375 } 376 377 qce_write(qce, REG_SEG_SIZE, totallen); 378 379 /* get little endianness */ 380 config = qce_config_reg(qce, 1); 381 qce_write(qce, REG_CONFIG, config); 382 383 qce_crypto_go(qce); 384 385 return 0; 386 } 387 388 int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen, 389 u32 offset) 390 { 391 switch (type) { 392 case CRYPTO_ALG_TYPE_ABLKCIPHER: 393 return qce_setup_regs_ablkcipher(async_req, totallen, offset); 394 case CRYPTO_ALG_TYPE_AHASH: 395 return qce_setup_regs_ahash(async_req, totallen, offset); 396 default: 397 return -EINVAL; 398 } 399 } 400 401 #define STATUS_ERRORS \ 402 (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) 403 404 int qce_check_status(struct qce_device *qce, u32 *status) 405 { 406 int ret = 0; 407 408 *status = qce_read(qce, REG_STATUS); 409 410 /* 411 * Don't use result dump status. The operation may not be complete. 412 * Instead, use the status we just read from device. In case, we need to 413 * use result_status from result dump the result_status needs to be byte 414 * swapped, since we set the device to little endian. 415 */ 416 if (*status & STATUS_ERRORS || !(*status & BIT(OPERATION_DONE_SHIFT))) 417 ret = -ENXIO; 418 419 return ret; 420 } 421 422 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) 423 { 424 u32 val; 425 426 val = qce_read(qce, REG_VERSION); 427 *major = (val & CORE_MAJOR_REV_MASK) >> CORE_MAJOR_REV_SHIFT; 428 *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; 429 *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; 430 } 431