1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP SHA1/MD5 HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * Some ideas are from old omap-sha1-md5.c driver. 15 */ 16 17 #define pr_fmt(fmt) "%s: " fmt, __func__ 18 19 #include <linux/err.h> 20 #include <linux/device.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/irq.h> 27 #include <linux/io.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/delay.h> 38 #include <linux/crypto.h> 39 #include <linux/cryptohash.h> 40 #include <crypto/scatterwalk.h> 41 #include <crypto/algapi.h> 42 #include <crypto/sha.h> 43 #include <crypto/hash.h> 44 #include <crypto/internal/hash.h> 45 46 #define MD5_DIGEST_SIZE 16 47 48 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 49 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 50 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 51 52 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 53 54 #define SHA_REG_CTRL 0x18 55 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 56 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 57 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 58 #define SHA_REG_CTRL_ALGO (1 << 2) 59 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 60 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 61 62 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 63 64 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 65 #define SHA_REG_MASK_DMA_EN (1 << 3) 66 #define SHA_REG_MASK_IT_EN (1 << 2) 67 #define SHA_REG_MASK_SOFTRESET (1 << 1) 68 #define SHA_REG_AUTOIDLE (1 << 0) 69 70 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 71 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 72 73 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 74 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 75 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 76 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 77 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 78 79 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 80 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 81 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 82 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 83 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 84 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 85 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 86 87 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 88 89 #define SHA_REG_IRQSTATUS 0x118 90 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 92 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 94 95 #define SHA_REG_IRQENA 0x11C 96 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 97 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 98 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 99 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 100 101 #define DEFAULT_TIMEOUT_INTERVAL HZ 102 103 #define DEFAULT_AUTOSUSPEND_DELAY 1000 104 105 /* mostly device flags */ 106 #define FLAGS_BUSY 0 107 #define FLAGS_FINAL 1 108 #define FLAGS_DMA_ACTIVE 2 109 #define FLAGS_OUTPUT_READY 3 110 #define FLAGS_INIT 4 111 #define FLAGS_CPU 5 112 #define FLAGS_DMA_READY 6 113 #define FLAGS_AUTO_XOR 7 114 #define FLAGS_BE32_SHA1 8 115 /* context flags */ 116 #define FLAGS_FINUP 16 117 #define FLAGS_SG 17 118 119 #define FLAGS_MODE_SHIFT 18 120 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 126 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 127 128 #define FLAGS_HMAC 21 129 #define FLAGS_ERROR 22 130 131 #define OP_UPDATE 1 132 #define OP_FINAL 2 133 134 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 135 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 136 137 #define BUFLEN PAGE_SIZE 138 139 struct omap_sham_dev; 140 141 struct omap_sham_reqctx { 142 struct omap_sham_dev *dd; 143 unsigned long flags; 144 unsigned long op; 145 146 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 147 size_t digcnt; 148 size_t bufcnt; 149 size_t buflen; 150 dma_addr_t dma_addr; 151 152 /* walk state */ 153 struct scatterlist *sg; 154 struct scatterlist sgl; 155 unsigned int offset; /* offset in current sg */ 156 unsigned int total; /* total request */ 157 158 u8 buffer[0] OMAP_ALIGNED; 159 }; 160 161 struct omap_sham_hmac_ctx { 162 struct crypto_shash *shash; 163 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 164 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 165 }; 166 167 struct omap_sham_ctx { 168 struct omap_sham_dev *dd; 169 170 unsigned long flags; 171 172 /* fallback stuff */ 173 struct crypto_shash *fallback; 174 175 struct omap_sham_hmac_ctx base[0]; 176 }; 177 178 #define OMAP_SHAM_QUEUE_LENGTH 10 179 180 struct omap_sham_algs_info { 181 struct ahash_alg *algs_list; 182 unsigned int size; 183 unsigned int registered; 184 }; 185 186 struct omap_sham_pdata { 187 struct omap_sham_algs_info *algs_info; 188 unsigned int algs_info_size; 189 unsigned long flags; 190 int digest_size; 191 192 void (*copy_hash)(struct ahash_request *req, int out); 193 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 194 int final, int dma); 195 void (*trigger)(struct omap_sham_dev *dd, size_t length); 196 int (*poll_irq)(struct omap_sham_dev *dd); 197 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 198 199 u32 odigest_ofs; 200 u32 idigest_ofs; 201 u32 din_ofs; 202 u32 digcnt_ofs; 203 u32 rev_ofs; 204 u32 mask_ofs; 205 u32 sysstatus_ofs; 206 u32 mode_ofs; 207 u32 length_ofs; 208 209 u32 major_mask; 210 u32 major_shift; 211 u32 minor_mask; 212 u32 minor_shift; 213 }; 214 215 struct omap_sham_dev { 216 struct list_head list; 217 unsigned long phys_base; 218 struct device *dev; 219 void __iomem *io_base; 220 int irq; 221 spinlock_t lock; 222 int err; 223 struct dma_chan *dma_lch; 224 struct tasklet_struct done_task; 225 u8 polling_mode; 226 227 unsigned long flags; 228 struct crypto_queue queue; 229 struct ahash_request *req; 230 231 const struct omap_sham_pdata *pdata; 232 }; 233 234 struct omap_sham_drv { 235 struct list_head dev_list; 236 spinlock_t lock; 237 unsigned long flags; 238 }; 239 240 static struct omap_sham_drv sham = { 241 .dev_list = LIST_HEAD_INIT(sham.dev_list), 242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 243 }; 244 245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 246 { 247 return __raw_readl(dd->io_base + offset); 248 } 249 250 static inline void omap_sham_write(struct omap_sham_dev *dd, 251 u32 offset, u32 value) 252 { 253 __raw_writel(value, dd->io_base + offset); 254 } 255 256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 257 u32 value, u32 mask) 258 { 259 u32 val; 260 261 val = omap_sham_read(dd, address); 262 val &= ~mask; 263 val |= value; 264 omap_sham_write(dd, address, val); 265 } 266 267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 268 { 269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 270 271 while (!(omap_sham_read(dd, offset) & bit)) { 272 if (time_is_before_jiffies(timeout)) 273 return -ETIMEDOUT; 274 } 275 276 return 0; 277 } 278 279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 280 { 281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 282 struct omap_sham_dev *dd = ctx->dd; 283 u32 *hash = (u32 *)ctx->digest; 284 int i; 285 286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 287 if (out) 288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 289 else 290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 291 } 292 } 293 294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 295 { 296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 297 struct omap_sham_dev *dd = ctx->dd; 298 int i; 299 300 if (ctx->flags & BIT(FLAGS_HMAC)) { 301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 303 struct omap_sham_hmac_ctx *bctx = tctx->base; 304 u32 *opad = (u32 *)bctx->opad; 305 306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 307 if (out) 308 opad[i] = omap_sham_read(dd, 309 SHA_REG_ODIGEST(dd, i)); 310 else 311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 312 opad[i]); 313 } 314 } 315 316 omap_sham_copy_hash_omap2(req, out); 317 } 318 319 static void omap_sham_copy_ready_hash(struct ahash_request *req) 320 { 321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 322 u32 *in = (u32 *)ctx->digest; 323 u32 *hash = (u32 *)req->result; 324 int i, d, big_endian = 0; 325 326 if (!hash) 327 return; 328 329 switch (ctx->flags & FLAGS_MODE_MASK) { 330 case FLAGS_MODE_MD5: 331 d = MD5_DIGEST_SIZE / sizeof(u32); 332 break; 333 case FLAGS_MODE_SHA1: 334 /* OMAP2 SHA1 is big endian */ 335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 336 big_endian = 1; 337 d = SHA1_DIGEST_SIZE / sizeof(u32); 338 break; 339 case FLAGS_MODE_SHA224: 340 d = SHA224_DIGEST_SIZE / sizeof(u32); 341 break; 342 case FLAGS_MODE_SHA256: 343 d = SHA256_DIGEST_SIZE / sizeof(u32); 344 break; 345 case FLAGS_MODE_SHA384: 346 d = SHA384_DIGEST_SIZE / sizeof(u32); 347 break; 348 case FLAGS_MODE_SHA512: 349 d = SHA512_DIGEST_SIZE / sizeof(u32); 350 break; 351 default: 352 d = 0; 353 } 354 355 if (big_endian) 356 for (i = 0; i < d; i++) 357 hash[i] = be32_to_cpu(in[i]); 358 else 359 for (i = 0; i < d; i++) 360 hash[i] = le32_to_cpu(in[i]); 361 } 362 363 static int omap_sham_hw_init(struct omap_sham_dev *dd) 364 { 365 int err; 366 367 err = pm_runtime_get_sync(dd->dev); 368 if (err < 0) { 369 dev_err(dd->dev, "failed to get sync: %d\n", err); 370 return err; 371 } 372 373 if (!test_bit(FLAGS_INIT, &dd->flags)) { 374 set_bit(FLAGS_INIT, &dd->flags); 375 dd->err = 0; 376 } 377 378 return 0; 379 } 380 381 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 382 int final, int dma) 383 { 384 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 385 u32 val = length << 5, mask; 386 387 if (likely(ctx->digcnt)) 388 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 389 390 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 391 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 392 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 393 /* 394 * Setting ALGO_CONST only for the first iteration 395 * and CLOSE_HASH only for the last one. 396 */ 397 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 398 val |= SHA_REG_CTRL_ALGO; 399 if (!ctx->digcnt) 400 val |= SHA_REG_CTRL_ALGO_CONST; 401 if (final) 402 val |= SHA_REG_CTRL_CLOSE_HASH; 403 404 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 405 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 406 407 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 408 } 409 410 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 411 { 412 } 413 414 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 415 { 416 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 417 } 418 419 static int get_block_size(struct omap_sham_reqctx *ctx) 420 { 421 int d; 422 423 switch (ctx->flags & FLAGS_MODE_MASK) { 424 case FLAGS_MODE_MD5: 425 case FLAGS_MODE_SHA1: 426 d = SHA1_BLOCK_SIZE; 427 break; 428 case FLAGS_MODE_SHA224: 429 case FLAGS_MODE_SHA256: 430 d = SHA256_BLOCK_SIZE; 431 break; 432 case FLAGS_MODE_SHA384: 433 case FLAGS_MODE_SHA512: 434 d = SHA512_BLOCK_SIZE; 435 break; 436 default: 437 d = 0; 438 } 439 440 return d; 441 } 442 443 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 444 u32 *value, int count) 445 { 446 for (; count--; value++, offset += 4) 447 omap_sham_write(dd, offset, *value); 448 } 449 450 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 451 int final, int dma) 452 { 453 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 454 u32 val, mask; 455 456 /* 457 * Setting ALGO_CONST only for the first iteration and 458 * CLOSE_HASH only for the last one. Note that flags mode bits 459 * correspond to algorithm encoding in mode register. 460 */ 461 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 462 if (!ctx->digcnt) { 463 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 464 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 465 struct omap_sham_hmac_ctx *bctx = tctx->base; 466 int bs, nr_dr; 467 468 val |= SHA_REG_MODE_ALGO_CONSTANT; 469 470 if (ctx->flags & BIT(FLAGS_HMAC)) { 471 bs = get_block_size(ctx); 472 nr_dr = bs / (2 * sizeof(u32)); 473 val |= SHA_REG_MODE_HMAC_KEY_PROC; 474 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 475 (u32 *)bctx->ipad, nr_dr); 476 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 477 (u32 *)bctx->ipad + nr_dr, nr_dr); 478 ctx->digcnt += bs; 479 } 480 } 481 482 if (final) { 483 val |= SHA_REG_MODE_CLOSE_HASH; 484 485 if (ctx->flags & BIT(FLAGS_HMAC)) 486 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 487 } 488 489 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 490 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 491 SHA_REG_MODE_HMAC_KEY_PROC; 492 493 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 494 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 495 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 496 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 497 SHA_REG_MASK_IT_EN | 498 (dma ? SHA_REG_MASK_DMA_EN : 0), 499 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 500 } 501 502 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 503 { 504 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 505 } 506 507 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 508 { 509 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 510 SHA_REG_IRQSTATUS_INPUT_RDY); 511 } 512 513 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf, 514 size_t length, int final) 515 { 516 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 517 int count, len32, bs32, offset = 0; 518 const u32 *buffer = (const u32 *)buf; 519 520 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 521 ctx->digcnt, length, final); 522 523 dd->pdata->write_ctrl(dd, length, final, 0); 524 dd->pdata->trigger(dd, length); 525 526 /* should be non-zero before next lines to disable clocks later */ 527 ctx->digcnt += length; 528 529 if (final) 530 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 531 532 set_bit(FLAGS_CPU, &dd->flags); 533 534 len32 = DIV_ROUND_UP(length, sizeof(u32)); 535 bs32 = get_block_size(ctx) / sizeof(u32); 536 537 while (len32) { 538 if (dd->pdata->poll_irq(dd)) 539 return -ETIMEDOUT; 540 541 for (count = 0; count < min(len32, bs32); count++, offset++) 542 omap_sham_write(dd, SHA_REG_DIN(dd, count), 543 buffer[offset]); 544 len32 -= min(len32, bs32); 545 } 546 547 return -EINPROGRESS; 548 } 549 550 static void omap_sham_dma_callback(void *param) 551 { 552 struct omap_sham_dev *dd = param; 553 554 set_bit(FLAGS_DMA_READY, &dd->flags); 555 tasklet_schedule(&dd->done_task); 556 } 557 558 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr, 559 size_t length, int final, int is_sg) 560 { 561 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 562 struct dma_async_tx_descriptor *tx; 563 struct dma_slave_config cfg; 564 int len32, ret, dma_min = get_block_size(ctx); 565 566 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 567 ctx->digcnt, length, final); 568 569 memset(&cfg, 0, sizeof(cfg)); 570 571 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 572 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 573 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES; 574 575 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 576 if (ret) { 577 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 578 return ret; 579 } 580 581 len32 = DIV_ROUND_UP(length, dma_min) * dma_min; 582 583 if (is_sg) { 584 /* 585 * The SG entry passed in may not have the 'length' member 586 * set correctly so use a local SG entry (sgl) with the 587 * proper value for 'length' instead. If this is not done, 588 * the dmaengine may try to DMA the incorrect amount of data. 589 */ 590 sg_init_table(&ctx->sgl, 1); 591 sg_assign_page(&ctx->sgl, sg_page(ctx->sg)); 592 ctx->sgl.offset = ctx->sg->offset; 593 sg_dma_len(&ctx->sgl) = len32; 594 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg); 595 596 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1, 597 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 598 } else { 599 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32, 600 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 601 } 602 603 if (!tx) { 604 dev_err(dd->dev, "prep_slave_sg/single() failed\n"); 605 return -EINVAL; 606 } 607 608 tx->callback = omap_sham_dma_callback; 609 tx->callback_param = dd; 610 611 dd->pdata->write_ctrl(dd, length, final, 1); 612 613 ctx->digcnt += length; 614 615 if (final) 616 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 617 618 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 619 620 dmaengine_submit(tx); 621 dma_async_issue_pending(dd->dma_lch); 622 623 dd->pdata->trigger(dd, length); 624 625 return -EINPROGRESS; 626 } 627 628 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx, 629 const u8 *data, size_t length) 630 { 631 size_t count = min(length, ctx->buflen - ctx->bufcnt); 632 633 count = min(count, ctx->total); 634 if (count <= 0) 635 return 0; 636 memcpy(ctx->buffer + ctx->bufcnt, data, count); 637 ctx->bufcnt += count; 638 639 return count; 640 } 641 642 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx) 643 { 644 size_t count; 645 const u8 *vaddr; 646 647 while (ctx->sg) { 648 vaddr = kmap_atomic(sg_page(ctx->sg)); 649 vaddr += ctx->sg->offset; 650 651 count = omap_sham_append_buffer(ctx, 652 vaddr + ctx->offset, 653 ctx->sg->length - ctx->offset); 654 655 kunmap_atomic((void *)vaddr); 656 657 if (!count) 658 break; 659 ctx->offset += count; 660 ctx->total -= count; 661 if (ctx->offset == ctx->sg->length) { 662 ctx->sg = sg_next(ctx->sg); 663 if (ctx->sg) 664 ctx->offset = 0; 665 else 666 ctx->total = 0; 667 } 668 } 669 670 return 0; 671 } 672 673 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd, 674 struct omap_sham_reqctx *ctx, 675 size_t length, int final) 676 { 677 int ret; 678 679 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen, 680 DMA_TO_DEVICE); 681 if (dma_mapping_error(dd->dev, ctx->dma_addr)) { 682 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen); 683 return -EINVAL; 684 } 685 686 ctx->flags &= ~BIT(FLAGS_SG); 687 688 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0); 689 if (ret != -EINPROGRESS) 690 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, 691 DMA_TO_DEVICE); 692 693 return ret; 694 } 695 696 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd) 697 { 698 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 699 unsigned int final; 700 size_t count; 701 702 omap_sham_append_sg(ctx); 703 704 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 705 706 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n", 707 ctx->bufcnt, ctx->digcnt, final); 708 709 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { 710 count = ctx->bufcnt; 711 ctx->bufcnt = 0; 712 return omap_sham_xmit_dma_map(dd, ctx, count, final); 713 } 714 715 return 0; 716 } 717 718 /* Start address alignment */ 719 #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32))) 720 /* SHA1 block size alignment */ 721 #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs)) 722 723 static int omap_sham_update_dma_start(struct omap_sham_dev *dd) 724 { 725 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 726 unsigned int length, final, tail; 727 struct scatterlist *sg; 728 int ret, bs; 729 730 if (!ctx->total) 731 return 0; 732 733 if (ctx->bufcnt || ctx->offset) 734 return omap_sham_update_dma_slow(dd); 735 736 /* 737 * Don't use the sg interface when the transfer size is less 738 * than the number of elements in a DMA frame. Otherwise, 739 * the dmaengine infrastructure will calculate that it needs 740 * to transfer 0 frames which ultimately fails. 741 */ 742 if (ctx->total < get_block_size(ctx)) 743 return omap_sham_update_dma_slow(dd); 744 745 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n", 746 ctx->digcnt, ctx->bufcnt, ctx->total); 747 748 sg = ctx->sg; 749 bs = get_block_size(ctx); 750 751 if (!SG_AA(sg)) 752 return omap_sham_update_dma_slow(dd); 753 754 if (!sg_is_last(sg) && !SG_SA(sg, bs)) 755 /* size is not BLOCK_SIZE aligned */ 756 return omap_sham_update_dma_slow(dd); 757 758 length = min(ctx->total, sg->length); 759 760 if (sg_is_last(sg)) { 761 if (!(ctx->flags & BIT(FLAGS_FINUP))) { 762 /* not last sg must be BLOCK_SIZE aligned */ 763 tail = length & (bs - 1); 764 /* without finup() we need one block to close hash */ 765 if (!tail) 766 tail = bs; 767 length -= tail; 768 } 769 } 770 771 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { 772 dev_err(dd->dev, "dma_map_sg error\n"); 773 return -EINVAL; 774 } 775 776 ctx->flags |= BIT(FLAGS_SG); 777 778 ctx->total -= length; 779 ctx->offset = length; /* offset where to start slow */ 780 781 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 782 783 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1); 784 if (ret != -EINPROGRESS) 785 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); 786 787 return ret; 788 } 789 790 static int omap_sham_update_cpu(struct omap_sham_dev *dd) 791 { 792 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 793 int bufcnt, final; 794 795 if (!ctx->total) 796 return 0; 797 798 omap_sham_append_sg(ctx); 799 800 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 801 802 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n", 803 ctx->bufcnt, ctx->digcnt, final); 804 805 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { 806 bufcnt = ctx->bufcnt; 807 ctx->bufcnt = 0; 808 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final); 809 } 810 811 return 0; 812 } 813 814 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 815 { 816 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 817 818 819 if (ctx->flags & BIT(FLAGS_SG)) { 820 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); 821 if (ctx->sg->length == ctx->offset) { 822 ctx->sg = sg_next(ctx->sg); 823 if (ctx->sg) 824 ctx->offset = 0; 825 } 826 } else { 827 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, 828 DMA_TO_DEVICE); 829 } 830 831 return 0; 832 } 833 834 static int omap_sham_init(struct ahash_request *req) 835 { 836 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 837 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 838 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 839 struct omap_sham_dev *dd = NULL, *tmp; 840 int bs = 0; 841 842 spin_lock_bh(&sham.lock); 843 if (!tctx->dd) { 844 list_for_each_entry(tmp, &sham.dev_list, list) { 845 dd = tmp; 846 break; 847 } 848 tctx->dd = dd; 849 } else { 850 dd = tctx->dd; 851 } 852 spin_unlock_bh(&sham.lock); 853 854 ctx->dd = dd; 855 856 ctx->flags = 0; 857 858 dev_dbg(dd->dev, "init: digest size: %d\n", 859 crypto_ahash_digestsize(tfm)); 860 861 switch (crypto_ahash_digestsize(tfm)) { 862 case MD5_DIGEST_SIZE: 863 ctx->flags |= FLAGS_MODE_MD5; 864 bs = SHA1_BLOCK_SIZE; 865 break; 866 case SHA1_DIGEST_SIZE: 867 ctx->flags |= FLAGS_MODE_SHA1; 868 bs = SHA1_BLOCK_SIZE; 869 break; 870 case SHA224_DIGEST_SIZE: 871 ctx->flags |= FLAGS_MODE_SHA224; 872 bs = SHA224_BLOCK_SIZE; 873 break; 874 case SHA256_DIGEST_SIZE: 875 ctx->flags |= FLAGS_MODE_SHA256; 876 bs = SHA256_BLOCK_SIZE; 877 break; 878 case SHA384_DIGEST_SIZE: 879 ctx->flags |= FLAGS_MODE_SHA384; 880 bs = SHA384_BLOCK_SIZE; 881 break; 882 case SHA512_DIGEST_SIZE: 883 ctx->flags |= FLAGS_MODE_SHA512; 884 bs = SHA512_BLOCK_SIZE; 885 break; 886 } 887 888 ctx->bufcnt = 0; 889 ctx->digcnt = 0; 890 ctx->buflen = BUFLEN; 891 892 if (tctx->flags & BIT(FLAGS_HMAC)) { 893 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 894 struct omap_sham_hmac_ctx *bctx = tctx->base; 895 896 memcpy(ctx->buffer, bctx->ipad, bs); 897 ctx->bufcnt = bs; 898 } 899 900 ctx->flags |= BIT(FLAGS_HMAC); 901 } 902 903 return 0; 904 905 } 906 907 static int omap_sham_update_req(struct omap_sham_dev *dd) 908 { 909 struct ahash_request *req = dd->req; 910 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 911 int err; 912 913 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", 914 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); 915 916 if (ctx->flags & BIT(FLAGS_CPU)) 917 err = omap_sham_update_cpu(dd); 918 else 919 err = omap_sham_update_dma_start(dd); 920 921 /* wait for dma completion before can take more data */ 922 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 923 924 return err; 925 } 926 927 static int omap_sham_final_req(struct omap_sham_dev *dd) 928 { 929 struct ahash_request *req = dd->req; 930 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 931 int err = 0, use_dma = 1; 932 933 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode) 934 /* 935 * faster to handle last block with cpu or 936 * use cpu when dma is not present. 937 */ 938 use_dma = 0; 939 940 if (use_dma) 941 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1); 942 else 943 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1); 944 945 ctx->bufcnt = 0; 946 947 dev_dbg(dd->dev, "final_req: err: %d\n", err); 948 949 return err; 950 } 951 952 static int omap_sham_finish_hmac(struct ahash_request *req) 953 { 954 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 955 struct omap_sham_hmac_ctx *bctx = tctx->base; 956 int bs = crypto_shash_blocksize(bctx->shash); 957 int ds = crypto_shash_digestsize(bctx->shash); 958 SHASH_DESC_ON_STACK(shash, bctx->shash); 959 960 shash->tfm = bctx->shash; 961 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */ 962 963 return crypto_shash_init(shash) ?: 964 crypto_shash_update(shash, bctx->opad, bs) ?: 965 crypto_shash_finup(shash, req->result, ds, req->result); 966 } 967 968 static int omap_sham_finish(struct ahash_request *req) 969 { 970 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 971 struct omap_sham_dev *dd = ctx->dd; 972 int err = 0; 973 974 if (ctx->digcnt) { 975 omap_sham_copy_ready_hash(req); 976 if ((ctx->flags & BIT(FLAGS_HMAC)) && 977 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 978 err = omap_sham_finish_hmac(req); 979 } 980 981 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 982 983 return err; 984 } 985 986 static void omap_sham_finish_req(struct ahash_request *req, int err) 987 { 988 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 989 struct omap_sham_dev *dd = ctx->dd; 990 991 if (!err) { 992 dd->pdata->copy_hash(req, 1); 993 if (test_bit(FLAGS_FINAL, &dd->flags)) 994 err = omap_sham_finish(req); 995 } else { 996 ctx->flags |= BIT(FLAGS_ERROR); 997 } 998 999 /* atomic operation is not needed here */ 1000 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1001 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1002 1003 pm_runtime_mark_last_busy(dd->dev); 1004 pm_runtime_put_autosuspend(dd->dev); 1005 1006 if (req->base.complete) 1007 req->base.complete(&req->base, err); 1008 1009 /* handle new request */ 1010 tasklet_schedule(&dd->done_task); 1011 } 1012 1013 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1014 struct ahash_request *req) 1015 { 1016 struct crypto_async_request *async_req, *backlog; 1017 struct omap_sham_reqctx *ctx; 1018 unsigned long flags; 1019 int err = 0, ret = 0; 1020 1021 spin_lock_irqsave(&dd->lock, flags); 1022 if (req) 1023 ret = ahash_enqueue_request(&dd->queue, req); 1024 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1025 spin_unlock_irqrestore(&dd->lock, flags); 1026 return ret; 1027 } 1028 backlog = crypto_get_backlog(&dd->queue); 1029 async_req = crypto_dequeue_request(&dd->queue); 1030 if (async_req) 1031 set_bit(FLAGS_BUSY, &dd->flags); 1032 spin_unlock_irqrestore(&dd->lock, flags); 1033 1034 if (!async_req) 1035 return ret; 1036 1037 if (backlog) 1038 backlog->complete(backlog, -EINPROGRESS); 1039 1040 req = ahash_request_cast(async_req); 1041 dd->req = req; 1042 ctx = ahash_request_ctx(req); 1043 1044 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1045 ctx->op, req->nbytes); 1046 1047 err = omap_sham_hw_init(dd); 1048 if (err) 1049 goto err1; 1050 1051 if (ctx->digcnt) 1052 /* request has changed - restore hash */ 1053 dd->pdata->copy_hash(req, 0); 1054 1055 if (ctx->op == OP_UPDATE) { 1056 err = omap_sham_update_req(dd); 1057 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1058 /* no final() after finup() */ 1059 err = omap_sham_final_req(dd); 1060 } else if (ctx->op == OP_FINAL) { 1061 err = omap_sham_final_req(dd); 1062 } 1063 err1: 1064 if (err != -EINPROGRESS) 1065 /* done_task will not finish it, so do it here */ 1066 omap_sham_finish_req(req, err); 1067 1068 dev_dbg(dd->dev, "exit, err: %d\n", err); 1069 1070 return ret; 1071 } 1072 1073 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1074 { 1075 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1076 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1077 struct omap_sham_dev *dd = tctx->dd; 1078 1079 ctx->op = op; 1080 1081 return omap_sham_handle_queue(dd, req); 1082 } 1083 1084 static int omap_sham_update(struct ahash_request *req) 1085 { 1086 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1087 struct omap_sham_dev *dd = ctx->dd; 1088 int bs = get_block_size(ctx); 1089 1090 if (!req->nbytes) 1091 return 0; 1092 1093 ctx->total = req->nbytes; 1094 ctx->sg = req->src; 1095 ctx->offset = 0; 1096 1097 if (ctx->flags & BIT(FLAGS_FINUP)) { 1098 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) { 1099 /* 1100 * OMAP HW accel works only with buffers >= 9 1101 * will switch to bypass in final() 1102 * final has the same request and data 1103 */ 1104 omap_sham_append_sg(ctx); 1105 return 0; 1106 } else if ((ctx->bufcnt + ctx->total <= bs) || 1107 dd->polling_mode) { 1108 /* 1109 * faster to use CPU for short transfers or 1110 * use cpu when dma is not present. 1111 */ 1112 ctx->flags |= BIT(FLAGS_CPU); 1113 } 1114 } else if (ctx->bufcnt + ctx->total < ctx->buflen) { 1115 omap_sham_append_sg(ctx); 1116 return 0; 1117 } 1118 1119 if (dd->polling_mode) 1120 ctx->flags |= BIT(FLAGS_CPU); 1121 1122 return omap_sham_enqueue(req, OP_UPDATE); 1123 } 1124 1125 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags, 1126 const u8 *data, unsigned int len, u8 *out) 1127 { 1128 SHASH_DESC_ON_STACK(shash, tfm); 1129 1130 shash->tfm = tfm; 1131 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP; 1132 1133 return crypto_shash_digest(shash, data, len, out); 1134 } 1135 1136 static int omap_sham_final_shash(struct ahash_request *req) 1137 { 1138 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1139 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1140 1141 return omap_sham_shash_digest(tctx->fallback, req->base.flags, 1142 ctx->buffer, ctx->bufcnt, req->result); 1143 } 1144 1145 static int omap_sham_final(struct ahash_request *req) 1146 { 1147 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1148 1149 ctx->flags |= BIT(FLAGS_FINUP); 1150 1151 if (ctx->flags & BIT(FLAGS_ERROR)) 1152 return 0; /* uncompleted hash is not needed */ 1153 1154 /* 1155 * OMAP HW accel works only with buffers >= 9. 1156 * HMAC is always >= 9 because ipad == block size. 1157 * If buffersize is less than 240, we use fallback SW encoding, 1158 * as using DMA + HW in this case doesn't provide any benefit. 1159 */ 1160 if ((ctx->digcnt + ctx->bufcnt) < 240) 1161 return omap_sham_final_shash(req); 1162 else if (ctx->bufcnt) 1163 return omap_sham_enqueue(req, OP_FINAL); 1164 1165 /* copy ready hash (+ finalize hmac) */ 1166 return omap_sham_finish(req); 1167 } 1168 1169 static int omap_sham_finup(struct ahash_request *req) 1170 { 1171 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1172 int err1, err2; 1173 1174 ctx->flags |= BIT(FLAGS_FINUP); 1175 1176 err1 = omap_sham_update(req); 1177 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1178 return err1; 1179 /* 1180 * final() has to be always called to cleanup resources 1181 * even if udpate() failed, except EINPROGRESS 1182 */ 1183 err2 = omap_sham_final(req); 1184 1185 return err1 ?: err2; 1186 } 1187 1188 static int omap_sham_digest(struct ahash_request *req) 1189 { 1190 return omap_sham_init(req) ?: omap_sham_finup(req); 1191 } 1192 1193 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1194 unsigned int keylen) 1195 { 1196 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1197 struct omap_sham_hmac_ctx *bctx = tctx->base; 1198 int bs = crypto_shash_blocksize(bctx->shash); 1199 int ds = crypto_shash_digestsize(bctx->shash); 1200 struct omap_sham_dev *dd = NULL, *tmp; 1201 int err, i; 1202 1203 spin_lock_bh(&sham.lock); 1204 if (!tctx->dd) { 1205 list_for_each_entry(tmp, &sham.dev_list, list) { 1206 dd = tmp; 1207 break; 1208 } 1209 tctx->dd = dd; 1210 } else { 1211 dd = tctx->dd; 1212 } 1213 spin_unlock_bh(&sham.lock); 1214 1215 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1216 if (err) 1217 return err; 1218 1219 if (keylen > bs) { 1220 err = omap_sham_shash_digest(bctx->shash, 1221 crypto_shash_get_flags(bctx->shash), 1222 key, keylen, bctx->ipad); 1223 if (err) 1224 return err; 1225 keylen = ds; 1226 } else { 1227 memcpy(bctx->ipad, key, keylen); 1228 } 1229 1230 memset(bctx->ipad + keylen, 0, bs - keylen); 1231 1232 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1233 memcpy(bctx->opad, bctx->ipad, bs); 1234 1235 for (i = 0; i < bs; i++) { 1236 bctx->ipad[i] ^= 0x36; 1237 bctx->opad[i] ^= 0x5c; 1238 } 1239 } 1240 1241 return err; 1242 } 1243 1244 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1245 { 1246 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1247 const char *alg_name = crypto_tfm_alg_name(tfm); 1248 1249 /* Allocate a fallback and abort if it failed. */ 1250 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1251 CRYPTO_ALG_NEED_FALLBACK); 1252 if (IS_ERR(tctx->fallback)) { 1253 pr_err("omap-sham: fallback driver '%s' " 1254 "could not be loaded.\n", alg_name); 1255 return PTR_ERR(tctx->fallback); 1256 } 1257 1258 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1259 sizeof(struct omap_sham_reqctx) + BUFLEN); 1260 1261 if (alg_base) { 1262 struct omap_sham_hmac_ctx *bctx = tctx->base; 1263 tctx->flags |= BIT(FLAGS_HMAC); 1264 bctx->shash = crypto_alloc_shash(alg_base, 0, 1265 CRYPTO_ALG_NEED_FALLBACK); 1266 if (IS_ERR(bctx->shash)) { 1267 pr_err("omap-sham: base driver '%s' " 1268 "could not be loaded.\n", alg_base); 1269 crypto_free_shash(tctx->fallback); 1270 return PTR_ERR(bctx->shash); 1271 } 1272 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1279 { 1280 return omap_sham_cra_init_alg(tfm, NULL); 1281 } 1282 1283 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1284 { 1285 return omap_sham_cra_init_alg(tfm, "sha1"); 1286 } 1287 1288 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1289 { 1290 return omap_sham_cra_init_alg(tfm, "sha224"); 1291 } 1292 1293 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1294 { 1295 return omap_sham_cra_init_alg(tfm, "sha256"); 1296 } 1297 1298 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1299 { 1300 return omap_sham_cra_init_alg(tfm, "md5"); 1301 } 1302 1303 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1304 { 1305 return omap_sham_cra_init_alg(tfm, "sha384"); 1306 } 1307 1308 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1309 { 1310 return omap_sham_cra_init_alg(tfm, "sha512"); 1311 } 1312 1313 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1314 { 1315 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1316 1317 crypto_free_shash(tctx->fallback); 1318 tctx->fallback = NULL; 1319 1320 if (tctx->flags & BIT(FLAGS_HMAC)) { 1321 struct omap_sham_hmac_ctx *bctx = tctx->base; 1322 crypto_free_shash(bctx->shash); 1323 } 1324 } 1325 1326 static struct ahash_alg algs_sha1_md5[] = { 1327 { 1328 .init = omap_sham_init, 1329 .update = omap_sham_update, 1330 .final = omap_sham_final, 1331 .finup = omap_sham_finup, 1332 .digest = omap_sham_digest, 1333 .halg.digestsize = SHA1_DIGEST_SIZE, 1334 .halg.base = { 1335 .cra_name = "sha1", 1336 .cra_driver_name = "omap-sha1", 1337 .cra_priority = 400, 1338 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1339 CRYPTO_ALG_KERN_DRIVER_ONLY | 1340 CRYPTO_ALG_ASYNC | 1341 CRYPTO_ALG_NEED_FALLBACK, 1342 .cra_blocksize = SHA1_BLOCK_SIZE, 1343 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1344 .cra_alignmask = 0, 1345 .cra_module = THIS_MODULE, 1346 .cra_init = omap_sham_cra_init, 1347 .cra_exit = omap_sham_cra_exit, 1348 } 1349 }, 1350 { 1351 .init = omap_sham_init, 1352 .update = omap_sham_update, 1353 .final = omap_sham_final, 1354 .finup = omap_sham_finup, 1355 .digest = omap_sham_digest, 1356 .halg.digestsize = MD5_DIGEST_SIZE, 1357 .halg.base = { 1358 .cra_name = "md5", 1359 .cra_driver_name = "omap-md5", 1360 .cra_priority = 400, 1361 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1362 CRYPTO_ALG_KERN_DRIVER_ONLY | 1363 CRYPTO_ALG_ASYNC | 1364 CRYPTO_ALG_NEED_FALLBACK, 1365 .cra_blocksize = SHA1_BLOCK_SIZE, 1366 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1367 .cra_alignmask = OMAP_ALIGN_MASK, 1368 .cra_module = THIS_MODULE, 1369 .cra_init = omap_sham_cra_init, 1370 .cra_exit = omap_sham_cra_exit, 1371 } 1372 }, 1373 { 1374 .init = omap_sham_init, 1375 .update = omap_sham_update, 1376 .final = omap_sham_final, 1377 .finup = omap_sham_finup, 1378 .digest = omap_sham_digest, 1379 .setkey = omap_sham_setkey, 1380 .halg.digestsize = SHA1_DIGEST_SIZE, 1381 .halg.base = { 1382 .cra_name = "hmac(sha1)", 1383 .cra_driver_name = "omap-hmac-sha1", 1384 .cra_priority = 400, 1385 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1386 CRYPTO_ALG_KERN_DRIVER_ONLY | 1387 CRYPTO_ALG_ASYNC | 1388 CRYPTO_ALG_NEED_FALLBACK, 1389 .cra_blocksize = SHA1_BLOCK_SIZE, 1390 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1391 sizeof(struct omap_sham_hmac_ctx), 1392 .cra_alignmask = OMAP_ALIGN_MASK, 1393 .cra_module = THIS_MODULE, 1394 .cra_init = omap_sham_cra_sha1_init, 1395 .cra_exit = omap_sham_cra_exit, 1396 } 1397 }, 1398 { 1399 .init = omap_sham_init, 1400 .update = omap_sham_update, 1401 .final = omap_sham_final, 1402 .finup = omap_sham_finup, 1403 .digest = omap_sham_digest, 1404 .setkey = omap_sham_setkey, 1405 .halg.digestsize = MD5_DIGEST_SIZE, 1406 .halg.base = { 1407 .cra_name = "hmac(md5)", 1408 .cra_driver_name = "omap-hmac-md5", 1409 .cra_priority = 400, 1410 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1411 CRYPTO_ALG_KERN_DRIVER_ONLY | 1412 CRYPTO_ALG_ASYNC | 1413 CRYPTO_ALG_NEED_FALLBACK, 1414 .cra_blocksize = SHA1_BLOCK_SIZE, 1415 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1416 sizeof(struct omap_sham_hmac_ctx), 1417 .cra_alignmask = OMAP_ALIGN_MASK, 1418 .cra_module = THIS_MODULE, 1419 .cra_init = omap_sham_cra_md5_init, 1420 .cra_exit = omap_sham_cra_exit, 1421 } 1422 } 1423 }; 1424 1425 /* OMAP4 has some algs in addition to what OMAP2 has */ 1426 static struct ahash_alg algs_sha224_sha256[] = { 1427 { 1428 .init = omap_sham_init, 1429 .update = omap_sham_update, 1430 .final = omap_sham_final, 1431 .finup = omap_sham_finup, 1432 .digest = omap_sham_digest, 1433 .halg.digestsize = SHA224_DIGEST_SIZE, 1434 .halg.base = { 1435 .cra_name = "sha224", 1436 .cra_driver_name = "omap-sha224", 1437 .cra_priority = 400, 1438 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1439 CRYPTO_ALG_ASYNC | 1440 CRYPTO_ALG_NEED_FALLBACK, 1441 .cra_blocksize = SHA224_BLOCK_SIZE, 1442 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1443 .cra_alignmask = 0, 1444 .cra_module = THIS_MODULE, 1445 .cra_init = omap_sham_cra_init, 1446 .cra_exit = omap_sham_cra_exit, 1447 } 1448 }, 1449 { 1450 .init = omap_sham_init, 1451 .update = omap_sham_update, 1452 .final = omap_sham_final, 1453 .finup = omap_sham_finup, 1454 .digest = omap_sham_digest, 1455 .halg.digestsize = SHA256_DIGEST_SIZE, 1456 .halg.base = { 1457 .cra_name = "sha256", 1458 .cra_driver_name = "omap-sha256", 1459 .cra_priority = 400, 1460 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1461 CRYPTO_ALG_ASYNC | 1462 CRYPTO_ALG_NEED_FALLBACK, 1463 .cra_blocksize = SHA256_BLOCK_SIZE, 1464 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1465 .cra_alignmask = 0, 1466 .cra_module = THIS_MODULE, 1467 .cra_init = omap_sham_cra_init, 1468 .cra_exit = omap_sham_cra_exit, 1469 } 1470 }, 1471 { 1472 .init = omap_sham_init, 1473 .update = omap_sham_update, 1474 .final = omap_sham_final, 1475 .finup = omap_sham_finup, 1476 .digest = omap_sham_digest, 1477 .setkey = omap_sham_setkey, 1478 .halg.digestsize = SHA224_DIGEST_SIZE, 1479 .halg.base = { 1480 .cra_name = "hmac(sha224)", 1481 .cra_driver_name = "omap-hmac-sha224", 1482 .cra_priority = 400, 1483 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1484 CRYPTO_ALG_ASYNC | 1485 CRYPTO_ALG_NEED_FALLBACK, 1486 .cra_blocksize = SHA224_BLOCK_SIZE, 1487 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1488 sizeof(struct omap_sham_hmac_ctx), 1489 .cra_alignmask = OMAP_ALIGN_MASK, 1490 .cra_module = THIS_MODULE, 1491 .cra_init = omap_sham_cra_sha224_init, 1492 .cra_exit = omap_sham_cra_exit, 1493 } 1494 }, 1495 { 1496 .init = omap_sham_init, 1497 .update = omap_sham_update, 1498 .final = omap_sham_final, 1499 .finup = omap_sham_finup, 1500 .digest = omap_sham_digest, 1501 .setkey = omap_sham_setkey, 1502 .halg.digestsize = SHA256_DIGEST_SIZE, 1503 .halg.base = { 1504 .cra_name = "hmac(sha256)", 1505 .cra_driver_name = "omap-hmac-sha256", 1506 .cra_priority = 400, 1507 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1508 CRYPTO_ALG_ASYNC | 1509 CRYPTO_ALG_NEED_FALLBACK, 1510 .cra_blocksize = SHA256_BLOCK_SIZE, 1511 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1512 sizeof(struct omap_sham_hmac_ctx), 1513 .cra_alignmask = OMAP_ALIGN_MASK, 1514 .cra_module = THIS_MODULE, 1515 .cra_init = omap_sham_cra_sha256_init, 1516 .cra_exit = omap_sham_cra_exit, 1517 } 1518 }, 1519 }; 1520 1521 static struct ahash_alg algs_sha384_sha512[] = { 1522 { 1523 .init = omap_sham_init, 1524 .update = omap_sham_update, 1525 .final = omap_sham_final, 1526 .finup = omap_sham_finup, 1527 .digest = omap_sham_digest, 1528 .halg.digestsize = SHA384_DIGEST_SIZE, 1529 .halg.base = { 1530 .cra_name = "sha384", 1531 .cra_driver_name = "omap-sha384", 1532 .cra_priority = 400, 1533 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1534 CRYPTO_ALG_ASYNC | 1535 CRYPTO_ALG_NEED_FALLBACK, 1536 .cra_blocksize = SHA384_BLOCK_SIZE, 1537 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1538 .cra_alignmask = 0, 1539 .cra_module = THIS_MODULE, 1540 .cra_init = omap_sham_cra_init, 1541 .cra_exit = omap_sham_cra_exit, 1542 } 1543 }, 1544 { 1545 .init = omap_sham_init, 1546 .update = omap_sham_update, 1547 .final = omap_sham_final, 1548 .finup = omap_sham_finup, 1549 .digest = omap_sham_digest, 1550 .halg.digestsize = SHA512_DIGEST_SIZE, 1551 .halg.base = { 1552 .cra_name = "sha512", 1553 .cra_driver_name = "omap-sha512", 1554 .cra_priority = 400, 1555 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1556 CRYPTO_ALG_ASYNC | 1557 CRYPTO_ALG_NEED_FALLBACK, 1558 .cra_blocksize = SHA512_BLOCK_SIZE, 1559 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1560 .cra_alignmask = 0, 1561 .cra_module = THIS_MODULE, 1562 .cra_init = omap_sham_cra_init, 1563 .cra_exit = omap_sham_cra_exit, 1564 } 1565 }, 1566 { 1567 .init = omap_sham_init, 1568 .update = omap_sham_update, 1569 .final = omap_sham_final, 1570 .finup = omap_sham_finup, 1571 .digest = omap_sham_digest, 1572 .setkey = omap_sham_setkey, 1573 .halg.digestsize = SHA384_DIGEST_SIZE, 1574 .halg.base = { 1575 .cra_name = "hmac(sha384)", 1576 .cra_driver_name = "omap-hmac-sha384", 1577 .cra_priority = 400, 1578 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1579 CRYPTO_ALG_ASYNC | 1580 CRYPTO_ALG_NEED_FALLBACK, 1581 .cra_blocksize = SHA384_BLOCK_SIZE, 1582 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1583 sizeof(struct omap_sham_hmac_ctx), 1584 .cra_alignmask = OMAP_ALIGN_MASK, 1585 .cra_module = THIS_MODULE, 1586 .cra_init = omap_sham_cra_sha384_init, 1587 .cra_exit = omap_sham_cra_exit, 1588 } 1589 }, 1590 { 1591 .init = omap_sham_init, 1592 .update = omap_sham_update, 1593 .final = omap_sham_final, 1594 .finup = omap_sham_finup, 1595 .digest = omap_sham_digest, 1596 .setkey = omap_sham_setkey, 1597 .halg.digestsize = SHA512_DIGEST_SIZE, 1598 .halg.base = { 1599 .cra_name = "hmac(sha512)", 1600 .cra_driver_name = "omap-hmac-sha512", 1601 .cra_priority = 400, 1602 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1603 CRYPTO_ALG_ASYNC | 1604 CRYPTO_ALG_NEED_FALLBACK, 1605 .cra_blocksize = SHA512_BLOCK_SIZE, 1606 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1607 sizeof(struct omap_sham_hmac_ctx), 1608 .cra_alignmask = OMAP_ALIGN_MASK, 1609 .cra_module = THIS_MODULE, 1610 .cra_init = omap_sham_cra_sha512_init, 1611 .cra_exit = omap_sham_cra_exit, 1612 } 1613 }, 1614 }; 1615 1616 static void omap_sham_done_task(unsigned long data) 1617 { 1618 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1619 int err = 0; 1620 1621 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1622 omap_sham_handle_queue(dd, NULL); 1623 return; 1624 } 1625 1626 if (test_bit(FLAGS_CPU, &dd->flags)) { 1627 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1628 /* hash or semi-hash ready */ 1629 err = omap_sham_update_cpu(dd); 1630 if (err != -EINPROGRESS) 1631 goto finish; 1632 } 1633 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1634 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1635 omap_sham_update_dma_stop(dd); 1636 if (dd->err) { 1637 err = dd->err; 1638 goto finish; 1639 } 1640 } 1641 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1642 /* hash or semi-hash ready */ 1643 clear_bit(FLAGS_DMA_READY, &dd->flags); 1644 err = omap_sham_update_dma_start(dd); 1645 if (err != -EINPROGRESS) 1646 goto finish; 1647 } 1648 } 1649 1650 return; 1651 1652 finish: 1653 dev_dbg(dd->dev, "update done: err: %d\n", err); 1654 /* finish curent request */ 1655 omap_sham_finish_req(dd->req, err); 1656 } 1657 1658 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1659 { 1660 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1661 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1662 } else { 1663 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1664 tasklet_schedule(&dd->done_task); 1665 } 1666 1667 return IRQ_HANDLED; 1668 } 1669 1670 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1671 { 1672 struct omap_sham_dev *dd = dev_id; 1673 1674 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1675 /* final -> allow device to go to power-saving mode */ 1676 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1677 1678 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1679 SHA_REG_CTRL_OUTPUT_READY); 1680 omap_sham_read(dd, SHA_REG_CTRL); 1681 1682 return omap_sham_irq_common(dd); 1683 } 1684 1685 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1686 { 1687 struct omap_sham_dev *dd = dev_id; 1688 1689 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1690 1691 return omap_sham_irq_common(dd); 1692 } 1693 1694 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1695 { 1696 .algs_list = algs_sha1_md5, 1697 .size = ARRAY_SIZE(algs_sha1_md5), 1698 }, 1699 }; 1700 1701 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1702 .algs_info = omap_sham_algs_info_omap2, 1703 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1704 .flags = BIT(FLAGS_BE32_SHA1), 1705 .digest_size = SHA1_DIGEST_SIZE, 1706 .copy_hash = omap_sham_copy_hash_omap2, 1707 .write_ctrl = omap_sham_write_ctrl_omap2, 1708 .trigger = omap_sham_trigger_omap2, 1709 .poll_irq = omap_sham_poll_irq_omap2, 1710 .intr_hdlr = omap_sham_irq_omap2, 1711 .idigest_ofs = 0x00, 1712 .din_ofs = 0x1c, 1713 .digcnt_ofs = 0x14, 1714 .rev_ofs = 0x5c, 1715 .mask_ofs = 0x60, 1716 .sysstatus_ofs = 0x64, 1717 .major_mask = 0xf0, 1718 .major_shift = 4, 1719 .minor_mask = 0x0f, 1720 .minor_shift = 0, 1721 }; 1722 1723 #ifdef CONFIG_OF 1724 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1725 { 1726 .algs_list = algs_sha1_md5, 1727 .size = ARRAY_SIZE(algs_sha1_md5), 1728 }, 1729 { 1730 .algs_list = algs_sha224_sha256, 1731 .size = ARRAY_SIZE(algs_sha224_sha256), 1732 }, 1733 }; 1734 1735 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1736 .algs_info = omap_sham_algs_info_omap4, 1737 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1738 .flags = BIT(FLAGS_AUTO_XOR), 1739 .digest_size = SHA256_DIGEST_SIZE, 1740 .copy_hash = omap_sham_copy_hash_omap4, 1741 .write_ctrl = omap_sham_write_ctrl_omap4, 1742 .trigger = omap_sham_trigger_omap4, 1743 .poll_irq = omap_sham_poll_irq_omap4, 1744 .intr_hdlr = omap_sham_irq_omap4, 1745 .idigest_ofs = 0x020, 1746 .odigest_ofs = 0x0, 1747 .din_ofs = 0x080, 1748 .digcnt_ofs = 0x040, 1749 .rev_ofs = 0x100, 1750 .mask_ofs = 0x110, 1751 .sysstatus_ofs = 0x114, 1752 .mode_ofs = 0x44, 1753 .length_ofs = 0x48, 1754 .major_mask = 0x0700, 1755 .major_shift = 8, 1756 .minor_mask = 0x003f, 1757 .minor_shift = 0, 1758 }; 1759 1760 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1761 { 1762 .algs_list = algs_sha1_md5, 1763 .size = ARRAY_SIZE(algs_sha1_md5), 1764 }, 1765 { 1766 .algs_list = algs_sha224_sha256, 1767 .size = ARRAY_SIZE(algs_sha224_sha256), 1768 }, 1769 { 1770 .algs_list = algs_sha384_sha512, 1771 .size = ARRAY_SIZE(algs_sha384_sha512), 1772 }, 1773 }; 1774 1775 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1776 .algs_info = omap_sham_algs_info_omap5, 1777 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1778 .flags = BIT(FLAGS_AUTO_XOR), 1779 .digest_size = SHA512_DIGEST_SIZE, 1780 .copy_hash = omap_sham_copy_hash_omap4, 1781 .write_ctrl = omap_sham_write_ctrl_omap4, 1782 .trigger = omap_sham_trigger_omap4, 1783 .poll_irq = omap_sham_poll_irq_omap4, 1784 .intr_hdlr = omap_sham_irq_omap4, 1785 .idigest_ofs = 0x240, 1786 .odigest_ofs = 0x200, 1787 .din_ofs = 0x080, 1788 .digcnt_ofs = 0x280, 1789 .rev_ofs = 0x100, 1790 .mask_ofs = 0x110, 1791 .sysstatus_ofs = 0x114, 1792 .mode_ofs = 0x284, 1793 .length_ofs = 0x288, 1794 .major_mask = 0x0700, 1795 .major_shift = 8, 1796 .minor_mask = 0x003f, 1797 .minor_shift = 0, 1798 }; 1799 1800 static const struct of_device_id omap_sham_of_match[] = { 1801 { 1802 .compatible = "ti,omap2-sham", 1803 .data = &omap_sham_pdata_omap2, 1804 }, 1805 { 1806 .compatible = "ti,omap3-sham", 1807 .data = &omap_sham_pdata_omap2, 1808 }, 1809 { 1810 .compatible = "ti,omap4-sham", 1811 .data = &omap_sham_pdata_omap4, 1812 }, 1813 { 1814 .compatible = "ti,omap5-sham", 1815 .data = &omap_sham_pdata_omap5, 1816 }, 1817 {}, 1818 }; 1819 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1820 1821 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1822 struct device *dev, struct resource *res) 1823 { 1824 struct device_node *node = dev->of_node; 1825 const struct of_device_id *match; 1826 int err = 0; 1827 1828 match = of_match_device(of_match_ptr(omap_sham_of_match), dev); 1829 if (!match) { 1830 dev_err(dev, "no compatible OF match\n"); 1831 err = -EINVAL; 1832 goto err; 1833 } 1834 1835 err = of_address_to_resource(node, 0, res); 1836 if (err < 0) { 1837 dev_err(dev, "can't translate OF node address\n"); 1838 err = -EINVAL; 1839 goto err; 1840 } 1841 1842 dd->irq = irq_of_parse_and_map(node, 0); 1843 if (!dd->irq) { 1844 dev_err(dev, "can't translate OF irq value\n"); 1845 err = -EINVAL; 1846 goto err; 1847 } 1848 1849 dd->pdata = match->data; 1850 1851 err: 1852 return err; 1853 } 1854 #else 1855 static const struct of_device_id omap_sham_of_match[] = { 1856 {}, 1857 }; 1858 1859 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1860 struct device *dev, struct resource *res) 1861 { 1862 return -EINVAL; 1863 } 1864 #endif 1865 1866 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 1867 struct platform_device *pdev, struct resource *res) 1868 { 1869 struct device *dev = &pdev->dev; 1870 struct resource *r; 1871 int err = 0; 1872 1873 /* Get the base address */ 1874 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1875 if (!r) { 1876 dev_err(dev, "no MEM resource info\n"); 1877 err = -ENODEV; 1878 goto err; 1879 } 1880 memcpy(res, r, sizeof(*res)); 1881 1882 /* Get the IRQ */ 1883 dd->irq = platform_get_irq(pdev, 0); 1884 if (dd->irq < 0) { 1885 dev_err(dev, "no IRQ resource info\n"); 1886 err = dd->irq; 1887 goto err; 1888 } 1889 1890 /* Only OMAP2/3 can be non-DT */ 1891 dd->pdata = &omap_sham_pdata_omap2; 1892 1893 err: 1894 return err; 1895 } 1896 1897 static int omap_sham_probe(struct platform_device *pdev) 1898 { 1899 struct omap_sham_dev *dd; 1900 struct device *dev = &pdev->dev; 1901 struct resource res; 1902 dma_cap_mask_t mask; 1903 int err, i, j; 1904 u32 rev; 1905 1906 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 1907 if (dd == NULL) { 1908 dev_err(dev, "unable to alloc data struct.\n"); 1909 err = -ENOMEM; 1910 goto data_err; 1911 } 1912 dd->dev = dev; 1913 platform_set_drvdata(pdev, dd); 1914 1915 INIT_LIST_HEAD(&dd->list); 1916 spin_lock_init(&dd->lock); 1917 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 1918 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 1919 1920 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 1921 omap_sham_get_res_pdev(dd, pdev, &res); 1922 if (err) 1923 goto data_err; 1924 1925 dd->io_base = devm_ioremap_resource(dev, &res); 1926 if (IS_ERR(dd->io_base)) { 1927 err = PTR_ERR(dd->io_base); 1928 goto data_err; 1929 } 1930 dd->phys_base = res.start; 1931 1932 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 1933 IRQF_TRIGGER_NONE, dev_name(dev), dd); 1934 if (err) { 1935 dev_err(dev, "unable to request irq %d, err = %d\n", 1936 dd->irq, err); 1937 goto data_err; 1938 } 1939 1940 dma_cap_zero(mask); 1941 dma_cap_set(DMA_SLAVE, mask); 1942 1943 dd->dma_lch = dma_request_chan(dev, "rx"); 1944 if (IS_ERR(dd->dma_lch)) { 1945 err = PTR_ERR(dd->dma_lch); 1946 if (err == -EPROBE_DEFER) 1947 goto data_err; 1948 1949 dd->polling_mode = 1; 1950 dev_dbg(dev, "using polling mode instead of dma\n"); 1951 } 1952 1953 dd->flags |= dd->pdata->flags; 1954 1955 pm_runtime_use_autosuspend(dev); 1956 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1957 1958 pm_runtime_enable(dev); 1959 pm_runtime_irq_safe(dev); 1960 1961 err = pm_runtime_get_sync(dev); 1962 if (err < 0) { 1963 dev_err(dev, "failed to get sync: %d\n", err); 1964 goto err_pm; 1965 } 1966 1967 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 1968 pm_runtime_put_sync(&pdev->dev); 1969 1970 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 1971 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 1972 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1973 1974 spin_lock(&sham.lock); 1975 list_add_tail(&dd->list, &sham.dev_list); 1976 spin_unlock(&sham.lock); 1977 1978 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1979 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1980 err = crypto_register_ahash( 1981 &dd->pdata->algs_info[i].algs_list[j]); 1982 if (err) 1983 goto err_algs; 1984 1985 dd->pdata->algs_info[i].registered++; 1986 } 1987 } 1988 1989 return 0; 1990 1991 err_algs: 1992 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1993 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1994 crypto_unregister_ahash( 1995 &dd->pdata->algs_info[i].algs_list[j]); 1996 err_pm: 1997 pm_runtime_disable(dev); 1998 if (!dd->polling_mode) 1999 dma_release_channel(dd->dma_lch); 2000 data_err: 2001 dev_err(dev, "initialization failed.\n"); 2002 2003 return err; 2004 } 2005 2006 static int omap_sham_remove(struct platform_device *pdev) 2007 { 2008 static struct omap_sham_dev *dd; 2009 int i, j; 2010 2011 dd = platform_get_drvdata(pdev); 2012 if (!dd) 2013 return -ENODEV; 2014 spin_lock(&sham.lock); 2015 list_del(&dd->list); 2016 spin_unlock(&sham.lock); 2017 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2018 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2019 crypto_unregister_ahash( 2020 &dd->pdata->algs_info[i].algs_list[j]); 2021 tasklet_kill(&dd->done_task); 2022 pm_runtime_disable(&pdev->dev); 2023 2024 if (!dd->polling_mode) 2025 dma_release_channel(dd->dma_lch); 2026 2027 return 0; 2028 } 2029 2030 #ifdef CONFIG_PM_SLEEP 2031 static int omap_sham_suspend(struct device *dev) 2032 { 2033 pm_runtime_put_sync(dev); 2034 return 0; 2035 } 2036 2037 static int omap_sham_resume(struct device *dev) 2038 { 2039 int err = pm_runtime_get_sync(dev); 2040 if (err < 0) { 2041 dev_err(dev, "failed to get sync: %d\n", err); 2042 return err; 2043 } 2044 return 0; 2045 } 2046 #endif 2047 2048 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2049 2050 static struct platform_driver omap_sham_driver = { 2051 .probe = omap_sham_probe, 2052 .remove = omap_sham_remove, 2053 .driver = { 2054 .name = "omap-sham", 2055 .pm = &omap_sham_pm_ops, 2056 .of_match_table = omap_sham_of_match, 2057 }, 2058 }; 2059 2060 module_platform_driver(omap_sham_driver); 2061 2062 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2063 MODULE_LICENSE("GPL v2"); 2064 MODULE_AUTHOR("Dmitry Kasatkin"); 2065 MODULE_ALIAS("platform:omap-sham"); 2066