1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP SHA1/MD5 HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * Some ideas are from old omap-sha1-md5.c driver. 15 */ 16 17 #define pr_fmt(fmt) "%s: " fmt, __func__ 18 19 #include <linux/err.h> 20 #include <linux/device.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/irq.h> 27 #include <linux/io.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/omap-dma.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/of_address.h> 37 #include <linux/of_irq.h> 38 #include <linux/delay.h> 39 #include <linux/crypto.h> 40 #include <linux/cryptohash.h> 41 #include <crypto/scatterwalk.h> 42 #include <crypto/algapi.h> 43 #include <crypto/sha.h> 44 #include <crypto/hash.h> 45 #include <crypto/internal/hash.h> 46 47 #define MD5_DIGEST_SIZE 16 48 49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 52 53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 54 55 #define SHA_REG_CTRL 0x18 56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 59 #define SHA_REG_CTRL_ALGO (1 << 2) 60 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 62 63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 64 65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 66 #define SHA_REG_MASK_DMA_EN (1 << 3) 67 #define SHA_REG_MASK_IT_EN (1 << 2) 68 #define SHA_REG_MASK_SOFTRESET (1 << 1) 69 #define SHA_REG_AUTOIDLE (1 << 0) 70 71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 73 74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 79 80 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 87 88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 89 90 #define SHA_REG_IRQSTATUS 0x118 91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 95 96 #define SHA_REG_IRQENA 0x11C 97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 101 102 #define DEFAULT_TIMEOUT_INTERVAL HZ 103 104 /* mostly device flags */ 105 #define FLAGS_BUSY 0 106 #define FLAGS_FINAL 1 107 #define FLAGS_DMA_ACTIVE 2 108 #define FLAGS_OUTPUT_READY 3 109 #define FLAGS_INIT 4 110 #define FLAGS_CPU 5 111 #define FLAGS_DMA_READY 6 112 #define FLAGS_AUTO_XOR 7 113 #define FLAGS_BE32_SHA1 8 114 /* context flags */ 115 #define FLAGS_FINUP 16 116 #define FLAGS_SG 17 117 118 #define FLAGS_MODE_SHIFT 18 119 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 120 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 126 127 #define FLAGS_HMAC 21 128 #define FLAGS_ERROR 22 129 130 #define OP_UPDATE 1 131 #define OP_FINAL 2 132 133 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 134 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 135 136 #define BUFLEN PAGE_SIZE 137 138 struct omap_sham_dev; 139 140 struct omap_sham_reqctx { 141 struct omap_sham_dev *dd; 142 unsigned long flags; 143 unsigned long op; 144 145 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 146 size_t digcnt; 147 size_t bufcnt; 148 size_t buflen; 149 dma_addr_t dma_addr; 150 151 /* walk state */ 152 struct scatterlist *sg; 153 struct scatterlist sgl; 154 unsigned int offset; /* offset in current sg */ 155 unsigned int total; /* total request */ 156 157 u8 buffer[0] OMAP_ALIGNED; 158 }; 159 160 struct omap_sham_hmac_ctx { 161 struct crypto_shash *shash; 162 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 163 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 164 }; 165 166 struct omap_sham_ctx { 167 struct omap_sham_dev *dd; 168 169 unsigned long flags; 170 171 /* fallback stuff */ 172 struct crypto_shash *fallback; 173 174 struct omap_sham_hmac_ctx base[0]; 175 }; 176 177 #define OMAP_SHAM_QUEUE_LENGTH 1 178 179 struct omap_sham_algs_info { 180 struct ahash_alg *algs_list; 181 unsigned int size; 182 unsigned int registered; 183 }; 184 185 struct omap_sham_pdata { 186 struct omap_sham_algs_info *algs_info; 187 unsigned int algs_info_size; 188 unsigned long flags; 189 int digest_size; 190 191 void (*copy_hash)(struct ahash_request *req, int out); 192 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 193 int final, int dma); 194 void (*trigger)(struct omap_sham_dev *dd, size_t length); 195 int (*poll_irq)(struct omap_sham_dev *dd); 196 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 197 198 u32 odigest_ofs; 199 u32 idigest_ofs; 200 u32 din_ofs; 201 u32 digcnt_ofs; 202 u32 rev_ofs; 203 u32 mask_ofs; 204 u32 sysstatus_ofs; 205 u32 mode_ofs; 206 u32 length_ofs; 207 208 u32 major_mask; 209 u32 major_shift; 210 u32 minor_mask; 211 u32 minor_shift; 212 }; 213 214 struct omap_sham_dev { 215 struct list_head list; 216 unsigned long phys_base; 217 struct device *dev; 218 void __iomem *io_base; 219 int irq; 220 spinlock_t lock; 221 int err; 222 unsigned int dma; 223 struct dma_chan *dma_lch; 224 struct tasklet_struct done_task; 225 u8 polling_mode; 226 227 unsigned long flags; 228 struct crypto_queue queue; 229 struct ahash_request *req; 230 231 const struct omap_sham_pdata *pdata; 232 }; 233 234 struct omap_sham_drv { 235 struct list_head dev_list; 236 spinlock_t lock; 237 unsigned long flags; 238 }; 239 240 static struct omap_sham_drv sham = { 241 .dev_list = LIST_HEAD_INIT(sham.dev_list), 242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 243 }; 244 245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 246 { 247 return __raw_readl(dd->io_base + offset); 248 } 249 250 static inline void omap_sham_write(struct omap_sham_dev *dd, 251 u32 offset, u32 value) 252 { 253 __raw_writel(value, dd->io_base + offset); 254 } 255 256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 257 u32 value, u32 mask) 258 { 259 u32 val; 260 261 val = omap_sham_read(dd, address); 262 val &= ~mask; 263 val |= value; 264 omap_sham_write(dd, address, val); 265 } 266 267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 268 { 269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 270 271 while (!(omap_sham_read(dd, offset) & bit)) { 272 if (time_is_before_jiffies(timeout)) 273 return -ETIMEDOUT; 274 } 275 276 return 0; 277 } 278 279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 280 { 281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 282 struct omap_sham_dev *dd = ctx->dd; 283 u32 *hash = (u32 *)ctx->digest; 284 int i; 285 286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 287 if (out) 288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 289 else 290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 291 } 292 } 293 294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 295 { 296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 297 struct omap_sham_dev *dd = ctx->dd; 298 int i; 299 300 if (ctx->flags & BIT(FLAGS_HMAC)) { 301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 303 struct omap_sham_hmac_ctx *bctx = tctx->base; 304 u32 *opad = (u32 *)bctx->opad; 305 306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 307 if (out) 308 opad[i] = omap_sham_read(dd, 309 SHA_REG_ODIGEST(dd, i)); 310 else 311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 312 opad[i]); 313 } 314 } 315 316 omap_sham_copy_hash_omap2(req, out); 317 } 318 319 static void omap_sham_copy_ready_hash(struct ahash_request *req) 320 { 321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 322 u32 *in = (u32 *)ctx->digest; 323 u32 *hash = (u32 *)req->result; 324 int i, d, big_endian = 0; 325 326 if (!hash) 327 return; 328 329 switch (ctx->flags & FLAGS_MODE_MASK) { 330 case FLAGS_MODE_MD5: 331 d = MD5_DIGEST_SIZE / sizeof(u32); 332 break; 333 case FLAGS_MODE_SHA1: 334 /* OMAP2 SHA1 is big endian */ 335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 336 big_endian = 1; 337 d = SHA1_DIGEST_SIZE / sizeof(u32); 338 break; 339 case FLAGS_MODE_SHA224: 340 d = SHA224_DIGEST_SIZE / sizeof(u32); 341 break; 342 case FLAGS_MODE_SHA256: 343 d = SHA256_DIGEST_SIZE / sizeof(u32); 344 break; 345 case FLAGS_MODE_SHA384: 346 d = SHA384_DIGEST_SIZE / sizeof(u32); 347 break; 348 case FLAGS_MODE_SHA512: 349 d = SHA512_DIGEST_SIZE / sizeof(u32); 350 break; 351 default: 352 d = 0; 353 } 354 355 if (big_endian) 356 for (i = 0; i < d; i++) 357 hash[i] = be32_to_cpu(in[i]); 358 else 359 for (i = 0; i < d; i++) 360 hash[i] = le32_to_cpu(in[i]); 361 } 362 363 static int omap_sham_hw_init(struct omap_sham_dev *dd) 364 { 365 pm_runtime_get_sync(dd->dev); 366 367 if (!test_bit(FLAGS_INIT, &dd->flags)) { 368 set_bit(FLAGS_INIT, &dd->flags); 369 dd->err = 0; 370 } 371 372 return 0; 373 } 374 375 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 376 int final, int dma) 377 { 378 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 379 u32 val = length << 5, mask; 380 381 if (likely(ctx->digcnt)) 382 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 383 384 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 385 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 386 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 387 /* 388 * Setting ALGO_CONST only for the first iteration 389 * and CLOSE_HASH only for the last one. 390 */ 391 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 392 val |= SHA_REG_CTRL_ALGO; 393 if (!ctx->digcnt) 394 val |= SHA_REG_CTRL_ALGO_CONST; 395 if (final) 396 val |= SHA_REG_CTRL_CLOSE_HASH; 397 398 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 399 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 400 401 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 402 } 403 404 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 405 { 406 } 407 408 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 409 { 410 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 411 } 412 413 static int get_block_size(struct omap_sham_reqctx *ctx) 414 { 415 int d; 416 417 switch (ctx->flags & FLAGS_MODE_MASK) { 418 case FLAGS_MODE_MD5: 419 case FLAGS_MODE_SHA1: 420 d = SHA1_BLOCK_SIZE; 421 break; 422 case FLAGS_MODE_SHA224: 423 case FLAGS_MODE_SHA256: 424 d = SHA256_BLOCK_SIZE; 425 break; 426 case FLAGS_MODE_SHA384: 427 case FLAGS_MODE_SHA512: 428 d = SHA512_BLOCK_SIZE; 429 break; 430 default: 431 d = 0; 432 } 433 434 return d; 435 } 436 437 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 438 u32 *value, int count) 439 { 440 for (; count--; value++, offset += 4) 441 omap_sham_write(dd, offset, *value); 442 } 443 444 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 445 int final, int dma) 446 { 447 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 448 u32 val, mask; 449 450 /* 451 * Setting ALGO_CONST only for the first iteration and 452 * CLOSE_HASH only for the last one. Note that flags mode bits 453 * correspond to algorithm encoding in mode register. 454 */ 455 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 456 if (!ctx->digcnt) { 457 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 458 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 459 struct omap_sham_hmac_ctx *bctx = tctx->base; 460 int bs, nr_dr; 461 462 val |= SHA_REG_MODE_ALGO_CONSTANT; 463 464 if (ctx->flags & BIT(FLAGS_HMAC)) { 465 bs = get_block_size(ctx); 466 nr_dr = bs / (2 * sizeof(u32)); 467 val |= SHA_REG_MODE_HMAC_KEY_PROC; 468 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 469 (u32 *)bctx->ipad, nr_dr); 470 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 471 (u32 *)bctx->ipad + nr_dr, nr_dr); 472 ctx->digcnt += bs; 473 } 474 } 475 476 if (final) { 477 val |= SHA_REG_MODE_CLOSE_HASH; 478 479 if (ctx->flags & BIT(FLAGS_HMAC)) 480 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 481 } 482 483 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 484 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 485 SHA_REG_MODE_HMAC_KEY_PROC; 486 487 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 488 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 489 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 490 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 491 SHA_REG_MASK_IT_EN | 492 (dma ? SHA_REG_MASK_DMA_EN : 0), 493 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 494 } 495 496 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 497 { 498 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 499 } 500 501 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 502 { 503 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 504 SHA_REG_IRQSTATUS_INPUT_RDY); 505 } 506 507 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf, 508 size_t length, int final) 509 { 510 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 511 int count, len32, bs32, offset = 0; 512 const u32 *buffer = (const u32 *)buf; 513 514 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 515 ctx->digcnt, length, final); 516 517 dd->pdata->write_ctrl(dd, length, final, 0); 518 dd->pdata->trigger(dd, length); 519 520 /* should be non-zero before next lines to disable clocks later */ 521 ctx->digcnt += length; 522 523 if (final) 524 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 525 526 set_bit(FLAGS_CPU, &dd->flags); 527 528 len32 = DIV_ROUND_UP(length, sizeof(u32)); 529 bs32 = get_block_size(ctx) / sizeof(u32); 530 531 while (len32) { 532 if (dd->pdata->poll_irq(dd)) 533 return -ETIMEDOUT; 534 535 for (count = 0; count < min(len32, bs32); count++, offset++) 536 omap_sham_write(dd, SHA_REG_DIN(dd, count), 537 buffer[offset]); 538 len32 -= min(len32, bs32); 539 } 540 541 return -EINPROGRESS; 542 } 543 544 static void omap_sham_dma_callback(void *param) 545 { 546 struct omap_sham_dev *dd = param; 547 548 set_bit(FLAGS_DMA_READY, &dd->flags); 549 tasklet_schedule(&dd->done_task); 550 } 551 552 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr, 553 size_t length, int final, int is_sg) 554 { 555 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 556 struct dma_async_tx_descriptor *tx; 557 struct dma_slave_config cfg; 558 int len32, ret, dma_min = get_block_size(ctx); 559 560 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 561 ctx->digcnt, length, final); 562 563 memset(&cfg, 0, sizeof(cfg)); 564 565 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 566 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 567 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES; 568 569 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 570 if (ret) { 571 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 572 return ret; 573 } 574 575 len32 = DIV_ROUND_UP(length, dma_min) * dma_min; 576 577 if (is_sg) { 578 /* 579 * The SG entry passed in may not have the 'length' member 580 * set correctly so use a local SG entry (sgl) with the 581 * proper value for 'length' instead. If this is not done, 582 * the dmaengine may try to DMA the incorrect amount of data. 583 */ 584 sg_init_table(&ctx->sgl, 1); 585 ctx->sgl.page_link = ctx->sg->page_link; 586 ctx->sgl.offset = ctx->sg->offset; 587 sg_dma_len(&ctx->sgl) = len32; 588 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg); 589 590 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1, 591 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 592 } else { 593 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32, 594 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 595 } 596 597 if (!tx) { 598 dev_err(dd->dev, "prep_slave_sg/single() failed\n"); 599 return -EINVAL; 600 } 601 602 tx->callback = omap_sham_dma_callback; 603 tx->callback_param = dd; 604 605 dd->pdata->write_ctrl(dd, length, final, 1); 606 607 ctx->digcnt += length; 608 609 if (final) 610 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 611 612 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 613 614 dmaengine_submit(tx); 615 dma_async_issue_pending(dd->dma_lch); 616 617 dd->pdata->trigger(dd, length); 618 619 return -EINPROGRESS; 620 } 621 622 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx, 623 const u8 *data, size_t length) 624 { 625 size_t count = min(length, ctx->buflen - ctx->bufcnt); 626 627 count = min(count, ctx->total); 628 if (count <= 0) 629 return 0; 630 memcpy(ctx->buffer + ctx->bufcnt, data, count); 631 ctx->bufcnt += count; 632 633 return count; 634 } 635 636 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx) 637 { 638 size_t count; 639 const u8 *vaddr; 640 641 while (ctx->sg) { 642 vaddr = kmap_atomic(sg_page(ctx->sg)); 643 644 count = omap_sham_append_buffer(ctx, 645 vaddr + ctx->offset, 646 ctx->sg->length - ctx->offset); 647 648 kunmap_atomic((void *)vaddr); 649 650 if (!count) 651 break; 652 ctx->offset += count; 653 ctx->total -= count; 654 if (ctx->offset == ctx->sg->length) { 655 ctx->sg = sg_next(ctx->sg); 656 if (ctx->sg) 657 ctx->offset = 0; 658 else 659 ctx->total = 0; 660 } 661 } 662 663 return 0; 664 } 665 666 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd, 667 struct omap_sham_reqctx *ctx, 668 size_t length, int final) 669 { 670 int ret; 671 672 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen, 673 DMA_TO_DEVICE); 674 if (dma_mapping_error(dd->dev, ctx->dma_addr)) { 675 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen); 676 return -EINVAL; 677 } 678 679 ctx->flags &= ~BIT(FLAGS_SG); 680 681 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0); 682 if (ret != -EINPROGRESS) 683 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, 684 DMA_TO_DEVICE); 685 686 return ret; 687 } 688 689 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd) 690 { 691 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 692 unsigned int final; 693 size_t count; 694 695 omap_sham_append_sg(ctx); 696 697 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 698 699 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n", 700 ctx->bufcnt, ctx->digcnt, final); 701 702 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { 703 count = ctx->bufcnt; 704 ctx->bufcnt = 0; 705 return omap_sham_xmit_dma_map(dd, ctx, count, final); 706 } 707 708 return 0; 709 } 710 711 /* Start address alignment */ 712 #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32))) 713 /* SHA1 block size alignment */ 714 #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs)) 715 716 static int omap_sham_update_dma_start(struct omap_sham_dev *dd) 717 { 718 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 719 unsigned int length, final, tail; 720 struct scatterlist *sg; 721 int ret, bs; 722 723 if (!ctx->total) 724 return 0; 725 726 if (ctx->bufcnt || ctx->offset) 727 return omap_sham_update_dma_slow(dd); 728 729 /* 730 * Don't use the sg interface when the transfer size is less 731 * than the number of elements in a DMA frame. Otherwise, 732 * the dmaengine infrastructure will calculate that it needs 733 * to transfer 0 frames which ultimately fails. 734 */ 735 if (ctx->total < get_block_size(ctx)) 736 return omap_sham_update_dma_slow(dd); 737 738 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n", 739 ctx->digcnt, ctx->bufcnt, ctx->total); 740 741 sg = ctx->sg; 742 bs = get_block_size(ctx); 743 744 if (!SG_AA(sg)) 745 return omap_sham_update_dma_slow(dd); 746 747 if (!sg_is_last(sg) && !SG_SA(sg, bs)) 748 /* size is not BLOCK_SIZE aligned */ 749 return omap_sham_update_dma_slow(dd); 750 751 length = min(ctx->total, sg->length); 752 753 if (sg_is_last(sg)) { 754 if (!(ctx->flags & BIT(FLAGS_FINUP))) { 755 /* not last sg must be BLOCK_SIZE aligned */ 756 tail = length & (bs - 1); 757 /* without finup() we need one block to close hash */ 758 if (!tail) 759 tail = bs; 760 length -= tail; 761 } 762 } 763 764 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { 765 dev_err(dd->dev, "dma_map_sg error\n"); 766 return -EINVAL; 767 } 768 769 ctx->flags |= BIT(FLAGS_SG); 770 771 ctx->total -= length; 772 ctx->offset = length; /* offset where to start slow */ 773 774 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 775 776 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1); 777 if (ret != -EINPROGRESS) 778 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); 779 780 return ret; 781 } 782 783 static int omap_sham_update_cpu(struct omap_sham_dev *dd) 784 { 785 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 786 int bufcnt, final; 787 788 if (!ctx->total) 789 return 0; 790 791 omap_sham_append_sg(ctx); 792 793 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; 794 795 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n", 796 ctx->bufcnt, ctx->digcnt, final); 797 798 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { 799 bufcnt = ctx->bufcnt; 800 ctx->bufcnt = 0; 801 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final); 802 } 803 804 return 0; 805 } 806 807 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 808 { 809 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 810 811 dmaengine_terminate_all(dd->dma_lch); 812 813 if (ctx->flags & BIT(FLAGS_SG)) { 814 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); 815 if (ctx->sg->length == ctx->offset) { 816 ctx->sg = sg_next(ctx->sg); 817 if (ctx->sg) 818 ctx->offset = 0; 819 } 820 } else { 821 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, 822 DMA_TO_DEVICE); 823 } 824 825 return 0; 826 } 827 828 static int omap_sham_init(struct ahash_request *req) 829 { 830 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 831 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 832 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 833 struct omap_sham_dev *dd = NULL, *tmp; 834 int bs = 0; 835 836 spin_lock_bh(&sham.lock); 837 if (!tctx->dd) { 838 list_for_each_entry(tmp, &sham.dev_list, list) { 839 dd = tmp; 840 break; 841 } 842 tctx->dd = dd; 843 } else { 844 dd = tctx->dd; 845 } 846 spin_unlock_bh(&sham.lock); 847 848 ctx->dd = dd; 849 850 ctx->flags = 0; 851 852 dev_dbg(dd->dev, "init: digest size: %d\n", 853 crypto_ahash_digestsize(tfm)); 854 855 switch (crypto_ahash_digestsize(tfm)) { 856 case MD5_DIGEST_SIZE: 857 ctx->flags |= FLAGS_MODE_MD5; 858 bs = SHA1_BLOCK_SIZE; 859 break; 860 case SHA1_DIGEST_SIZE: 861 ctx->flags |= FLAGS_MODE_SHA1; 862 bs = SHA1_BLOCK_SIZE; 863 break; 864 case SHA224_DIGEST_SIZE: 865 ctx->flags |= FLAGS_MODE_SHA224; 866 bs = SHA224_BLOCK_SIZE; 867 break; 868 case SHA256_DIGEST_SIZE: 869 ctx->flags |= FLAGS_MODE_SHA256; 870 bs = SHA256_BLOCK_SIZE; 871 break; 872 case SHA384_DIGEST_SIZE: 873 ctx->flags |= FLAGS_MODE_SHA384; 874 bs = SHA384_BLOCK_SIZE; 875 break; 876 case SHA512_DIGEST_SIZE: 877 ctx->flags |= FLAGS_MODE_SHA512; 878 bs = SHA512_BLOCK_SIZE; 879 break; 880 } 881 882 ctx->bufcnt = 0; 883 ctx->digcnt = 0; 884 ctx->buflen = BUFLEN; 885 886 if (tctx->flags & BIT(FLAGS_HMAC)) { 887 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 888 struct omap_sham_hmac_ctx *bctx = tctx->base; 889 890 memcpy(ctx->buffer, bctx->ipad, bs); 891 ctx->bufcnt = bs; 892 } 893 894 ctx->flags |= BIT(FLAGS_HMAC); 895 } 896 897 return 0; 898 899 } 900 901 static int omap_sham_update_req(struct omap_sham_dev *dd) 902 { 903 struct ahash_request *req = dd->req; 904 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 905 int err; 906 907 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", 908 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); 909 910 if (ctx->flags & BIT(FLAGS_CPU)) 911 err = omap_sham_update_cpu(dd); 912 else 913 err = omap_sham_update_dma_start(dd); 914 915 /* wait for dma completion before can take more data */ 916 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 917 918 return err; 919 } 920 921 static int omap_sham_final_req(struct omap_sham_dev *dd) 922 { 923 struct ahash_request *req = dd->req; 924 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 925 int err = 0, use_dma = 1; 926 927 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode) 928 /* 929 * faster to handle last block with cpu or 930 * use cpu when dma is not present. 931 */ 932 use_dma = 0; 933 934 if (use_dma) 935 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1); 936 else 937 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1); 938 939 ctx->bufcnt = 0; 940 941 dev_dbg(dd->dev, "final_req: err: %d\n", err); 942 943 return err; 944 } 945 946 static int omap_sham_finish_hmac(struct ahash_request *req) 947 { 948 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 949 struct omap_sham_hmac_ctx *bctx = tctx->base; 950 int bs = crypto_shash_blocksize(bctx->shash); 951 int ds = crypto_shash_digestsize(bctx->shash); 952 struct { 953 struct shash_desc shash; 954 char ctx[crypto_shash_descsize(bctx->shash)]; 955 } desc; 956 957 desc.shash.tfm = bctx->shash; 958 desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */ 959 960 return crypto_shash_init(&desc.shash) ?: 961 crypto_shash_update(&desc.shash, bctx->opad, bs) ?: 962 crypto_shash_finup(&desc.shash, req->result, ds, req->result); 963 } 964 965 static int omap_sham_finish(struct ahash_request *req) 966 { 967 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 968 struct omap_sham_dev *dd = ctx->dd; 969 int err = 0; 970 971 if (ctx->digcnt) { 972 omap_sham_copy_ready_hash(req); 973 if ((ctx->flags & BIT(FLAGS_HMAC)) && 974 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 975 err = omap_sham_finish_hmac(req); 976 } 977 978 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 979 980 return err; 981 } 982 983 static void omap_sham_finish_req(struct ahash_request *req, int err) 984 { 985 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 986 struct omap_sham_dev *dd = ctx->dd; 987 988 if (!err) { 989 dd->pdata->copy_hash(req, 1); 990 if (test_bit(FLAGS_FINAL, &dd->flags)) 991 err = omap_sham_finish(req); 992 } else { 993 ctx->flags |= BIT(FLAGS_ERROR); 994 } 995 996 /* atomic operation is not needed here */ 997 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 998 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 999 1000 pm_runtime_put(dd->dev); 1001 1002 if (req->base.complete) 1003 req->base.complete(&req->base, err); 1004 1005 /* handle new request */ 1006 tasklet_schedule(&dd->done_task); 1007 } 1008 1009 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1010 struct ahash_request *req) 1011 { 1012 struct crypto_async_request *async_req, *backlog; 1013 struct omap_sham_reqctx *ctx; 1014 unsigned long flags; 1015 int err = 0, ret = 0; 1016 1017 spin_lock_irqsave(&dd->lock, flags); 1018 if (req) 1019 ret = ahash_enqueue_request(&dd->queue, req); 1020 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1021 spin_unlock_irqrestore(&dd->lock, flags); 1022 return ret; 1023 } 1024 backlog = crypto_get_backlog(&dd->queue); 1025 async_req = crypto_dequeue_request(&dd->queue); 1026 if (async_req) 1027 set_bit(FLAGS_BUSY, &dd->flags); 1028 spin_unlock_irqrestore(&dd->lock, flags); 1029 1030 if (!async_req) 1031 return ret; 1032 1033 if (backlog) 1034 backlog->complete(backlog, -EINPROGRESS); 1035 1036 req = ahash_request_cast(async_req); 1037 dd->req = req; 1038 ctx = ahash_request_ctx(req); 1039 1040 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1041 ctx->op, req->nbytes); 1042 1043 err = omap_sham_hw_init(dd); 1044 if (err) 1045 goto err1; 1046 1047 if (ctx->digcnt) 1048 /* request has changed - restore hash */ 1049 dd->pdata->copy_hash(req, 0); 1050 1051 if (ctx->op == OP_UPDATE) { 1052 err = omap_sham_update_req(dd); 1053 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1054 /* no final() after finup() */ 1055 err = omap_sham_final_req(dd); 1056 } else if (ctx->op == OP_FINAL) { 1057 err = omap_sham_final_req(dd); 1058 } 1059 err1: 1060 if (err != -EINPROGRESS) 1061 /* done_task will not finish it, so do it here */ 1062 omap_sham_finish_req(req, err); 1063 1064 dev_dbg(dd->dev, "exit, err: %d\n", err); 1065 1066 return ret; 1067 } 1068 1069 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1070 { 1071 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1072 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1073 struct omap_sham_dev *dd = tctx->dd; 1074 1075 ctx->op = op; 1076 1077 return omap_sham_handle_queue(dd, req); 1078 } 1079 1080 static int omap_sham_update(struct ahash_request *req) 1081 { 1082 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1083 struct omap_sham_dev *dd = ctx->dd; 1084 int bs = get_block_size(ctx); 1085 1086 if (!req->nbytes) 1087 return 0; 1088 1089 ctx->total = req->nbytes; 1090 ctx->sg = req->src; 1091 ctx->offset = 0; 1092 1093 if (ctx->flags & BIT(FLAGS_FINUP)) { 1094 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) { 1095 /* 1096 * OMAP HW accel works only with buffers >= 9 1097 * will switch to bypass in final() 1098 * final has the same request and data 1099 */ 1100 omap_sham_append_sg(ctx); 1101 return 0; 1102 } else if ((ctx->bufcnt + ctx->total <= bs) || 1103 dd->polling_mode) { 1104 /* 1105 * faster to use CPU for short transfers or 1106 * use cpu when dma is not present. 1107 */ 1108 ctx->flags |= BIT(FLAGS_CPU); 1109 } 1110 } else if (ctx->bufcnt + ctx->total < ctx->buflen) { 1111 omap_sham_append_sg(ctx); 1112 return 0; 1113 } 1114 1115 if (dd->polling_mode) 1116 ctx->flags |= BIT(FLAGS_CPU); 1117 1118 return omap_sham_enqueue(req, OP_UPDATE); 1119 } 1120 1121 static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags, 1122 const u8 *data, unsigned int len, u8 *out) 1123 { 1124 struct { 1125 struct shash_desc shash; 1126 char ctx[crypto_shash_descsize(shash)]; 1127 } desc; 1128 1129 desc.shash.tfm = shash; 1130 desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP; 1131 1132 return crypto_shash_digest(&desc.shash, data, len, out); 1133 } 1134 1135 static int omap_sham_final_shash(struct ahash_request *req) 1136 { 1137 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1138 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1139 1140 return omap_sham_shash_digest(tctx->fallback, req->base.flags, 1141 ctx->buffer, ctx->bufcnt, req->result); 1142 } 1143 1144 static int omap_sham_final(struct ahash_request *req) 1145 { 1146 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1147 1148 ctx->flags |= BIT(FLAGS_FINUP); 1149 1150 if (ctx->flags & BIT(FLAGS_ERROR)) 1151 return 0; /* uncompleted hash is not needed */ 1152 1153 /* OMAP HW accel works only with buffers >= 9 */ 1154 /* HMAC is always >= 9 because ipad == block size */ 1155 if ((ctx->digcnt + ctx->bufcnt) < 9) 1156 return omap_sham_final_shash(req); 1157 else if (ctx->bufcnt) 1158 return omap_sham_enqueue(req, OP_FINAL); 1159 1160 /* copy ready hash (+ finalize hmac) */ 1161 return omap_sham_finish(req); 1162 } 1163 1164 static int omap_sham_finup(struct ahash_request *req) 1165 { 1166 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1167 int err1, err2; 1168 1169 ctx->flags |= BIT(FLAGS_FINUP); 1170 1171 err1 = omap_sham_update(req); 1172 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1173 return err1; 1174 /* 1175 * final() has to be always called to cleanup resources 1176 * even if udpate() failed, except EINPROGRESS 1177 */ 1178 err2 = omap_sham_final(req); 1179 1180 return err1 ?: err2; 1181 } 1182 1183 static int omap_sham_digest(struct ahash_request *req) 1184 { 1185 return omap_sham_init(req) ?: omap_sham_finup(req); 1186 } 1187 1188 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1189 unsigned int keylen) 1190 { 1191 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1192 struct omap_sham_hmac_ctx *bctx = tctx->base; 1193 int bs = crypto_shash_blocksize(bctx->shash); 1194 int ds = crypto_shash_digestsize(bctx->shash); 1195 struct omap_sham_dev *dd = NULL, *tmp; 1196 int err, i; 1197 1198 spin_lock_bh(&sham.lock); 1199 if (!tctx->dd) { 1200 list_for_each_entry(tmp, &sham.dev_list, list) { 1201 dd = tmp; 1202 break; 1203 } 1204 tctx->dd = dd; 1205 } else { 1206 dd = tctx->dd; 1207 } 1208 spin_unlock_bh(&sham.lock); 1209 1210 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1211 if (err) 1212 return err; 1213 1214 if (keylen > bs) { 1215 err = omap_sham_shash_digest(bctx->shash, 1216 crypto_shash_get_flags(bctx->shash), 1217 key, keylen, bctx->ipad); 1218 if (err) 1219 return err; 1220 keylen = ds; 1221 } else { 1222 memcpy(bctx->ipad, key, keylen); 1223 } 1224 1225 memset(bctx->ipad + keylen, 0, bs - keylen); 1226 1227 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1228 memcpy(bctx->opad, bctx->ipad, bs); 1229 1230 for (i = 0; i < bs; i++) { 1231 bctx->ipad[i] ^= 0x36; 1232 bctx->opad[i] ^= 0x5c; 1233 } 1234 } 1235 1236 return err; 1237 } 1238 1239 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1240 { 1241 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1242 const char *alg_name = crypto_tfm_alg_name(tfm); 1243 1244 /* Allocate a fallback and abort if it failed. */ 1245 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1246 CRYPTO_ALG_NEED_FALLBACK); 1247 if (IS_ERR(tctx->fallback)) { 1248 pr_err("omap-sham: fallback driver '%s' " 1249 "could not be loaded.\n", alg_name); 1250 return PTR_ERR(tctx->fallback); 1251 } 1252 1253 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1254 sizeof(struct omap_sham_reqctx) + BUFLEN); 1255 1256 if (alg_base) { 1257 struct omap_sham_hmac_ctx *bctx = tctx->base; 1258 tctx->flags |= BIT(FLAGS_HMAC); 1259 bctx->shash = crypto_alloc_shash(alg_base, 0, 1260 CRYPTO_ALG_NEED_FALLBACK); 1261 if (IS_ERR(bctx->shash)) { 1262 pr_err("omap-sham: base driver '%s' " 1263 "could not be loaded.\n", alg_base); 1264 crypto_free_shash(tctx->fallback); 1265 return PTR_ERR(bctx->shash); 1266 } 1267 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1274 { 1275 return omap_sham_cra_init_alg(tfm, NULL); 1276 } 1277 1278 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1279 { 1280 return omap_sham_cra_init_alg(tfm, "sha1"); 1281 } 1282 1283 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1284 { 1285 return omap_sham_cra_init_alg(tfm, "sha224"); 1286 } 1287 1288 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1289 { 1290 return omap_sham_cra_init_alg(tfm, "sha256"); 1291 } 1292 1293 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1294 { 1295 return omap_sham_cra_init_alg(tfm, "md5"); 1296 } 1297 1298 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1299 { 1300 return omap_sham_cra_init_alg(tfm, "sha384"); 1301 } 1302 1303 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1304 { 1305 return omap_sham_cra_init_alg(tfm, "sha512"); 1306 } 1307 1308 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1309 { 1310 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1311 1312 crypto_free_shash(tctx->fallback); 1313 tctx->fallback = NULL; 1314 1315 if (tctx->flags & BIT(FLAGS_HMAC)) { 1316 struct omap_sham_hmac_ctx *bctx = tctx->base; 1317 crypto_free_shash(bctx->shash); 1318 } 1319 } 1320 1321 static struct ahash_alg algs_sha1_md5[] = { 1322 { 1323 .init = omap_sham_init, 1324 .update = omap_sham_update, 1325 .final = omap_sham_final, 1326 .finup = omap_sham_finup, 1327 .digest = omap_sham_digest, 1328 .halg.digestsize = SHA1_DIGEST_SIZE, 1329 .halg.base = { 1330 .cra_name = "sha1", 1331 .cra_driver_name = "omap-sha1", 1332 .cra_priority = 100, 1333 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1334 CRYPTO_ALG_KERN_DRIVER_ONLY | 1335 CRYPTO_ALG_ASYNC | 1336 CRYPTO_ALG_NEED_FALLBACK, 1337 .cra_blocksize = SHA1_BLOCK_SIZE, 1338 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1339 .cra_alignmask = 0, 1340 .cra_module = THIS_MODULE, 1341 .cra_init = omap_sham_cra_init, 1342 .cra_exit = omap_sham_cra_exit, 1343 } 1344 }, 1345 { 1346 .init = omap_sham_init, 1347 .update = omap_sham_update, 1348 .final = omap_sham_final, 1349 .finup = omap_sham_finup, 1350 .digest = omap_sham_digest, 1351 .halg.digestsize = MD5_DIGEST_SIZE, 1352 .halg.base = { 1353 .cra_name = "md5", 1354 .cra_driver_name = "omap-md5", 1355 .cra_priority = 100, 1356 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1357 CRYPTO_ALG_KERN_DRIVER_ONLY | 1358 CRYPTO_ALG_ASYNC | 1359 CRYPTO_ALG_NEED_FALLBACK, 1360 .cra_blocksize = SHA1_BLOCK_SIZE, 1361 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1362 .cra_alignmask = OMAP_ALIGN_MASK, 1363 .cra_module = THIS_MODULE, 1364 .cra_init = omap_sham_cra_init, 1365 .cra_exit = omap_sham_cra_exit, 1366 } 1367 }, 1368 { 1369 .init = omap_sham_init, 1370 .update = omap_sham_update, 1371 .final = omap_sham_final, 1372 .finup = omap_sham_finup, 1373 .digest = omap_sham_digest, 1374 .setkey = omap_sham_setkey, 1375 .halg.digestsize = SHA1_DIGEST_SIZE, 1376 .halg.base = { 1377 .cra_name = "hmac(sha1)", 1378 .cra_driver_name = "omap-hmac-sha1", 1379 .cra_priority = 100, 1380 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1381 CRYPTO_ALG_KERN_DRIVER_ONLY | 1382 CRYPTO_ALG_ASYNC | 1383 CRYPTO_ALG_NEED_FALLBACK, 1384 .cra_blocksize = SHA1_BLOCK_SIZE, 1385 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1386 sizeof(struct omap_sham_hmac_ctx), 1387 .cra_alignmask = OMAP_ALIGN_MASK, 1388 .cra_module = THIS_MODULE, 1389 .cra_init = omap_sham_cra_sha1_init, 1390 .cra_exit = omap_sham_cra_exit, 1391 } 1392 }, 1393 { 1394 .init = omap_sham_init, 1395 .update = omap_sham_update, 1396 .final = omap_sham_final, 1397 .finup = omap_sham_finup, 1398 .digest = omap_sham_digest, 1399 .setkey = omap_sham_setkey, 1400 .halg.digestsize = MD5_DIGEST_SIZE, 1401 .halg.base = { 1402 .cra_name = "hmac(md5)", 1403 .cra_driver_name = "omap-hmac-md5", 1404 .cra_priority = 100, 1405 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1406 CRYPTO_ALG_KERN_DRIVER_ONLY | 1407 CRYPTO_ALG_ASYNC | 1408 CRYPTO_ALG_NEED_FALLBACK, 1409 .cra_blocksize = SHA1_BLOCK_SIZE, 1410 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1411 sizeof(struct omap_sham_hmac_ctx), 1412 .cra_alignmask = OMAP_ALIGN_MASK, 1413 .cra_module = THIS_MODULE, 1414 .cra_init = omap_sham_cra_md5_init, 1415 .cra_exit = omap_sham_cra_exit, 1416 } 1417 } 1418 }; 1419 1420 /* OMAP4 has some algs in addition to what OMAP2 has */ 1421 static struct ahash_alg algs_sha224_sha256[] = { 1422 { 1423 .init = omap_sham_init, 1424 .update = omap_sham_update, 1425 .final = omap_sham_final, 1426 .finup = omap_sham_finup, 1427 .digest = omap_sham_digest, 1428 .halg.digestsize = SHA224_DIGEST_SIZE, 1429 .halg.base = { 1430 .cra_name = "sha224", 1431 .cra_driver_name = "omap-sha224", 1432 .cra_priority = 100, 1433 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1434 CRYPTO_ALG_ASYNC | 1435 CRYPTO_ALG_NEED_FALLBACK, 1436 .cra_blocksize = SHA224_BLOCK_SIZE, 1437 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1438 .cra_alignmask = 0, 1439 .cra_module = THIS_MODULE, 1440 .cra_init = omap_sham_cra_init, 1441 .cra_exit = omap_sham_cra_exit, 1442 } 1443 }, 1444 { 1445 .init = omap_sham_init, 1446 .update = omap_sham_update, 1447 .final = omap_sham_final, 1448 .finup = omap_sham_finup, 1449 .digest = omap_sham_digest, 1450 .halg.digestsize = SHA256_DIGEST_SIZE, 1451 .halg.base = { 1452 .cra_name = "sha256", 1453 .cra_driver_name = "omap-sha256", 1454 .cra_priority = 100, 1455 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1456 CRYPTO_ALG_ASYNC | 1457 CRYPTO_ALG_NEED_FALLBACK, 1458 .cra_blocksize = SHA256_BLOCK_SIZE, 1459 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1460 .cra_alignmask = 0, 1461 .cra_module = THIS_MODULE, 1462 .cra_init = omap_sham_cra_init, 1463 .cra_exit = omap_sham_cra_exit, 1464 } 1465 }, 1466 { 1467 .init = omap_sham_init, 1468 .update = omap_sham_update, 1469 .final = omap_sham_final, 1470 .finup = omap_sham_finup, 1471 .digest = omap_sham_digest, 1472 .setkey = omap_sham_setkey, 1473 .halg.digestsize = SHA224_DIGEST_SIZE, 1474 .halg.base = { 1475 .cra_name = "hmac(sha224)", 1476 .cra_driver_name = "omap-hmac-sha224", 1477 .cra_priority = 100, 1478 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1479 CRYPTO_ALG_ASYNC | 1480 CRYPTO_ALG_NEED_FALLBACK, 1481 .cra_blocksize = SHA224_BLOCK_SIZE, 1482 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1483 sizeof(struct omap_sham_hmac_ctx), 1484 .cra_alignmask = OMAP_ALIGN_MASK, 1485 .cra_module = THIS_MODULE, 1486 .cra_init = omap_sham_cra_sha224_init, 1487 .cra_exit = omap_sham_cra_exit, 1488 } 1489 }, 1490 { 1491 .init = omap_sham_init, 1492 .update = omap_sham_update, 1493 .final = omap_sham_final, 1494 .finup = omap_sham_finup, 1495 .digest = omap_sham_digest, 1496 .setkey = omap_sham_setkey, 1497 .halg.digestsize = SHA256_DIGEST_SIZE, 1498 .halg.base = { 1499 .cra_name = "hmac(sha256)", 1500 .cra_driver_name = "omap-hmac-sha256", 1501 .cra_priority = 100, 1502 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1503 CRYPTO_ALG_ASYNC | 1504 CRYPTO_ALG_NEED_FALLBACK, 1505 .cra_blocksize = SHA256_BLOCK_SIZE, 1506 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1507 sizeof(struct omap_sham_hmac_ctx), 1508 .cra_alignmask = OMAP_ALIGN_MASK, 1509 .cra_module = THIS_MODULE, 1510 .cra_init = omap_sham_cra_sha256_init, 1511 .cra_exit = omap_sham_cra_exit, 1512 } 1513 }, 1514 }; 1515 1516 static struct ahash_alg algs_sha384_sha512[] = { 1517 { 1518 .init = omap_sham_init, 1519 .update = omap_sham_update, 1520 .final = omap_sham_final, 1521 .finup = omap_sham_finup, 1522 .digest = omap_sham_digest, 1523 .halg.digestsize = SHA384_DIGEST_SIZE, 1524 .halg.base = { 1525 .cra_name = "sha384", 1526 .cra_driver_name = "omap-sha384", 1527 .cra_priority = 100, 1528 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1529 CRYPTO_ALG_ASYNC | 1530 CRYPTO_ALG_NEED_FALLBACK, 1531 .cra_blocksize = SHA384_BLOCK_SIZE, 1532 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1533 .cra_alignmask = 0, 1534 .cra_module = THIS_MODULE, 1535 .cra_init = omap_sham_cra_init, 1536 .cra_exit = omap_sham_cra_exit, 1537 } 1538 }, 1539 { 1540 .init = omap_sham_init, 1541 .update = omap_sham_update, 1542 .final = omap_sham_final, 1543 .finup = omap_sham_finup, 1544 .digest = omap_sham_digest, 1545 .halg.digestsize = SHA512_DIGEST_SIZE, 1546 .halg.base = { 1547 .cra_name = "sha512", 1548 .cra_driver_name = "omap-sha512", 1549 .cra_priority = 100, 1550 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1551 CRYPTO_ALG_ASYNC | 1552 CRYPTO_ALG_NEED_FALLBACK, 1553 .cra_blocksize = SHA512_BLOCK_SIZE, 1554 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1555 .cra_alignmask = 0, 1556 .cra_module = THIS_MODULE, 1557 .cra_init = omap_sham_cra_init, 1558 .cra_exit = omap_sham_cra_exit, 1559 } 1560 }, 1561 { 1562 .init = omap_sham_init, 1563 .update = omap_sham_update, 1564 .final = omap_sham_final, 1565 .finup = omap_sham_finup, 1566 .digest = omap_sham_digest, 1567 .setkey = omap_sham_setkey, 1568 .halg.digestsize = SHA384_DIGEST_SIZE, 1569 .halg.base = { 1570 .cra_name = "hmac(sha384)", 1571 .cra_driver_name = "omap-hmac-sha384", 1572 .cra_priority = 100, 1573 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1574 CRYPTO_ALG_ASYNC | 1575 CRYPTO_ALG_NEED_FALLBACK, 1576 .cra_blocksize = SHA384_BLOCK_SIZE, 1577 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1578 sizeof(struct omap_sham_hmac_ctx), 1579 .cra_alignmask = OMAP_ALIGN_MASK, 1580 .cra_module = THIS_MODULE, 1581 .cra_init = omap_sham_cra_sha384_init, 1582 .cra_exit = omap_sham_cra_exit, 1583 } 1584 }, 1585 { 1586 .init = omap_sham_init, 1587 .update = omap_sham_update, 1588 .final = omap_sham_final, 1589 .finup = omap_sham_finup, 1590 .digest = omap_sham_digest, 1591 .setkey = omap_sham_setkey, 1592 .halg.digestsize = SHA512_DIGEST_SIZE, 1593 .halg.base = { 1594 .cra_name = "hmac(sha512)", 1595 .cra_driver_name = "omap-hmac-sha512", 1596 .cra_priority = 100, 1597 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1598 CRYPTO_ALG_ASYNC | 1599 CRYPTO_ALG_NEED_FALLBACK, 1600 .cra_blocksize = SHA512_BLOCK_SIZE, 1601 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1602 sizeof(struct omap_sham_hmac_ctx), 1603 .cra_alignmask = OMAP_ALIGN_MASK, 1604 .cra_module = THIS_MODULE, 1605 .cra_init = omap_sham_cra_sha512_init, 1606 .cra_exit = omap_sham_cra_exit, 1607 } 1608 }, 1609 }; 1610 1611 static void omap_sham_done_task(unsigned long data) 1612 { 1613 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1614 int err = 0; 1615 1616 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1617 omap_sham_handle_queue(dd, NULL); 1618 return; 1619 } 1620 1621 if (test_bit(FLAGS_CPU, &dd->flags)) { 1622 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1623 /* hash or semi-hash ready */ 1624 err = omap_sham_update_cpu(dd); 1625 if (err != -EINPROGRESS) 1626 goto finish; 1627 } 1628 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1629 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1630 omap_sham_update_dma_stop(dd); 1631 if (dd->err) { 1632 err = dd->err; 1633 goto finish; 1634 } 1635 } 1636 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1637 /* hash or semi-hash ready */ 1638 clear_bit(FLAGS_DMA_READY, &dd->flags); 1639 err = omap_sham_update_dma_start(dd); 1640 if (err != -EINPROGRESS) 1641 goto finish; 1642 } 1643 } 1644 1645 return; 1646 1647 finish: 1648 dev_dbg(dd->dev, "update done: err: %d\n", err); 1649 /* finish curent request */ 1650 omap_sham_finish_req(dd->req, err); 1651 } 1652 1653 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1654 { 1655 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1656 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1657 } else { 1658 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1659 tasklet_schedule(&dd->done_task); 1660 } 1661 1662 return IRQ_HANDLED; 1663 } 1664 1665 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1666 { 1667 struct omap_sham_dev *dd = dev_id; 1668 1669 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1670 /* final -> allow device to go to power-saving mode */ 1671 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1672 1673 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1674 SHA_REG_CTRL_OUTPUT_READY); 1675 omap_sham_read(dd, SHA_REG_CTRL); 1676 1677 return omap_sham_irq_common(dd); 1678 } 1679 1680 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1681 { 1682 struct omap_sham_dev *dd = dev_id; 1683 1684 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1685 1686 return omap_sham_irq_common(dd); 1687 } 1688 1689 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1690 { 1691 .algs_list = algs_sha1_md5, 1692 .size = ARRAY_SIZE(algs_sha1_md5), 1693 }, 1694 }; 1695 1696 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1697 .algs_info = omap_sham_algs_info_omap2, 1698 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1699 .flags = BIT(FLAGS_BE32_SHA1), 1700 .digest_size = SHA1_DIGEST_SIZE, 1701 .copy_hash = omap_sham_copy_hash_omap2, 1702 .write_ctrl = omap_sham_write_ctrl_omap2, 1703 .trigger = omap_sham_trigger_omap2, 1704 .poll_irq = omap_sham_poll_irq_omap2, 1705 .intr_hdlr = omap_sham_irq_omap2, 1706 .idigest_ofs = 0x00, 1707 .din_ofs = 0x1c, 1708 .digcnt_ofs = 0x14, 1709 .rev_ofs = 0x5c, 1710 .mask_ofs = 0x60, 1711 .sysstatus_ofs = 0x64, 1712 .major_mask = 0xf0, 1713 .major_shift = 4, 1714 .minor_mask = 0x0f, 1715 .minor_shift = 0, 1716 }; 1717 1718 #ifdef CONFIG_OF 1719 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1720 { 1721 .algs_list = algs_sha1_md5, 1722 .size = ARRAY_SIZE(algs_sha1_md5), 1723 }, 1724 { 1725 .algs_list = algs_sha224_sha256, 1726 .size = ARRAY_SIZE(algs_sha224_sha256), 1727 }, 1728 }; 1729 1730 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1731 .algs_info = omap_sham_algs_info_omap4, 1732 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1733 .flags = BIT(FLAGS_AUTO_XOR), 1734 .digest_size = SHA256_DIGEST_SIZE, 1735 .copy_hash = omap_sham_copy_hash_omap4, 1736 .write_ctrl = omap_sham_write_ctrl_omap4, 1737 .trigger = omap_sham_trigger_omap4, 1738 .poll_irq = omap_sham_poll_irq_omap4, 1739 .intr_hdlr = omap_sham_irq_omap4, 1740 .idigest_ofs = 0x020, 1741 .odigest_ofs = 0x0, 1742 .din_ofs = 0x080, 1743 .digcnt_ofs = 0x040, 1744 .rev_ofs = 0x100, 1745 .mask_ofs = 0x110, 1746 .sysstatus_ofs = 0x114, 1747 .mode_ofs = 0x44, 1748 .length_ofs = 0x48, 1749 .major_mask = 0x0700, 1750 .major_shift = 8, 1751 .minor_mask = 0x003f, 1752 .minor_shift = 0, 1753 }; 1754 1755 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1756 { 1757 .algs_list = algs_sha1_md5, 1758 .size = ARRAY_SIZE(algs_sha1_md5), 1759 }, 1760 { 1761 .algs_list = algs_sha224_sha256, 1762 .size = ARRAY_SIZE(algs_sha224_sha256), 1763 }, 1764 { 1765 .algs_list = algs_sha384_sha512, 1766 .size = ARRAY_SIZE(algs_sha384_sha512), 1767 }, 1768 }; 1769 1770 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1771 .algs_info = omap_sham_algs_info_omap5, 1772 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1773 .flags = BIT(FLAGS_AUTO_XOR), 1774 .digest_size = SHA512_DIGEST_SIZE, 1775 .copy_hash = omap_sham_copy_hash_omap4, 1776 .write_ctrl = omap_sham_write_ctrl_omap4, 1777 .trigger = omap_sham_trigger_omap4, 1778 .poll_irq = omap_sham_poll_irq_omap4, 1779 .intr_hdlr = omap_sham_irq_omap4, 1780 .idigest_ofs = 0x240, 1781 .odigest_ofs = 0x200, 1782 .din_ofs = 0x080, 1783 .digcnt_ofs = 0x280, 1784 .rev_ofs = 0x100, 1785 .mask_ofs = 0x110, 1786 .sysstatus_ofs = 0x114, 1787 .mode_ofs = 0x284, 1788 .length_ofs = 0x288, 1789 .major_mask = 0x0700, 1790 .major_shift = 8, 1791 .minor_mask = 0x003f, 1792 .minor_shift = 0, 1793 }; 1794 1795 static const struct of_device_id omap_sham_of_match[] = { 1796 { 1797 .compatible = "ti,omap2-sham", 1798 .data = &omap_sham_pdata_omap2, 1799 }, 1800 { 1801 .compatible = "ti,omap4-sham", 1802 .data = &omap_sham_pdata_omap4, 1803 }, 1804 { 1805 .compatible = "ti,omap5-sham", 1806 .data = &omap_sham_pdata_omap5, 1807 }, 1808 {}, 1809 }; 1810 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1811 1812 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1813 struct device *dev, struct resource *res) 1814 { 1815 struct device_node *node = dev->of_node; 1816 const struct of_device_id *match; 1817 int err = 0; 1818 1819 match = of_match_device(of_match_ptr(omap_sham_of_match), dev); 1820 if (!match) { 1821 dev_err(dev, "no compatible OF match\n"); 1822 err = -EINVAL; 1823 goto err; 1824 } 1825 1826 err = of_address_to_resource(node, 0, res); 1827 if (err < 0) { 1828 dev_err(dev, "can't translate OF node address\n"); 1829 err = -EINVAL; 1830 goto err; 1831 } 1832 1833 dd->irq = irq_of_parse_and_map(node, 0); 1834 if (!dd->irq) { 1835 dev_err(dev, "can't translate OF irq value\n"); 1836 err = -EINVAL; 1837 goto err; 1838 } 1839 1840 dd->dma = -1; /* Dummy value that's unused */ 1841 dd->pdata = match->data; 1842 1843 err: 1844 return err; 1845 } 1846 #else 1847 static const struct of_device_id omap_sham_of_match[] = { 1848 {}, 1849 }; 1850 1851 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1852 struct device *dev, struct resource *res) 1853 { 1854 return -EINVAL; 1855 } 1856 #endif 1857 1858 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 1859 struct platform_device *pdev, struct resource *res) 1860 { 1861 struct device *dev = &pdev->dev; 1862 struct resource *r; 1863 int err = 0; 1864 1865 /* Get the base address */ 1866 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1867 if (!r) { 1868 dev_err(dev, "no MEM resource info\n"); 1869 err = -ENODEV; 1870 goto err; 1871 } 1872 memcpy(res, r, sizeof(*res)); 1873 1874 /* Get the IRQ */ 1875 dd->irq = platform_get_irq(pdev, 0); 1876 if (dd->irq < 0) { 1877 dev_err(dev, "no IRQ resource info\n"); 1878 err = dd->irq; 1879 goto err; 1880 } 1881 1882 /* Get the DMA */ 1883 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1884 if (!r) { 1885 dev_err(dev, "no DMA resource info\n"); 1886 err = -ENODEV; 1887 goto err; 1888 } 1889 dd->dma = r->start; 1890 1891 /* Only OMAP2/3 can be non-DT */ 1892 dd->pdata = &omap_sham_pdata_omap2; 1893 1894 err: 1895 return err; 1896 } 1897 1898 static int omap_sham_probe(struct platform_device *pdev) 1899 { 1900 struct omap_sham_dev *dd; 1901 struct device *dev = &pdev->dev; 1902 struct resource res; 1903 dma_cap_mask_t mask; 1904 int err, i, j; 1905 u32 rev; 1906 1907 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 1908 if (dd == NULL) { 1909 dev_err(dev, "unable to alloc data struct.\n"); 1910 err = -ENOMEM; 1911 goto data_err; 1912 } 1913 dd->dev = dev; 1914 platform_set_drvdata(pdev, dd); 1915 1916 INIT_LIST_HEAD(&dd->list); 1917 spin_lock_init(&dd->lock); 1918 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 1919 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 1920 1921 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 1922 omap_sham_get_res_pdev(dd, pdev, &res); 1923 if (err) 1924 goto data_err; 1925 1926 dd->io_base = devm_ioremap_resource(dev, &res); 1927 if (IS_ERR(dd->io_base)) { 1928 err = PTR_ERR(dd->io_base); 1929 goto data_err; 1930 } 1931 dd->phys_base = res.start; 1932 1933 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 1934 IRQF_TRIGGER_NONE, dev_name(dev), dd); 1935 if (err) { 1936 dev_err(dev, "unable to request irq %d, err = %d\n", 1937 dd->irq, err); 1938 goto data_err; 1939 } 1940 1941 dma_cap_zero(mask); 1942 dma_cap_set(DMA_SLAVE, mask); 1943 1944 dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1945 &dd->dma, dev, "rx"); 1946 if (!dd->dma_lch) { 1947 dd->polling_mode = 1; 1948 dev_dbg(dev, "using polling mode instead of dma\n"); 1949 } 1950 1951 dd->flags |= dd->pdata->flags; 1952 1953 pm_runtime_enable(dev); 1954 pm_runtime_get_sync(dev); 1955 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 1956 pm_runtime_put_sync(&pdev->dev); 1957 1958 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 1959 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 1960 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1961 1962 spin_lock(&sham.lock); 1963 list_add_tail(&dd->list, &sham.dev_list); 1964 spin_unlock(&sham.lock); 1965 1966 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1967 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1968 err = crypto_register_ahash( 1969 &dd->pdata->algs_info[i].algs_list[j]); 1970 if (err) 1971 goto err_algs; 1972 1973 dd->pdata->algs_info[i].registered++; 1974 } 1975 } 1976 1977 return 0; 1978 1979 err_algs: 1980 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1981 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1982 crypto_unregister_ahash( 1983 &dd->pdata->algs_info[i].algs_list[j]); 1984 pm_runtime_disable(dev); 1985 if (dd->dma_lch) 1986 dma_release_channel(dd->dma_lch); 1987 data_err: 1988 dev_err(dev, "initialization failed.\n"); 1989 1990 return err; 1991 } 1992 1993 static int omap_sham_remove(struct platform_device *pdev) 1994 { 1995 static struct omap_sham_dev *dd; 1996 int i, j; 1997 1998 dd = platform_get_drvdata(pdev); 1999 if (!dd) 2000 return -ENODEV; 2001 spin_lock(&sham.lock); 2002 list_del(&dd->list); 2003 spin_unlock(&sham.lock); 2004 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2005 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2006 crypto_unregister_ahash( 2007 &dd->pdata->algs_info[i].algs_list[j]); 2008 tasklet_kill(&dd->done_task); 2009 pm_runtime_disable(&pdev->dev); 2010 2011 if (dd->dma_lch) 2012 dma_release_channel(dd->dma_lch); 2013 2014 return 0; 2015 } 2016 2017 #ifdef CONFIG_PM_SLEEP 2018 static int omap_sham_suspend(struct device *dev) 2019 { 2020 pm_runtime_put_sync(dev); 2021 return 0; 2022 } 2023 2024 static int omap_sham_resume(struct device *dev) 2025 { 2026 pm_runtime_get_sync(dev); 2027 return 0; 2028 } 2029 #endif 2030 2031 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2032 2033 static struct platform_driver omap_sham_driver = { 2034 .probe = omap_sham_probe, 2035 .remove = omap_sham_remove, 2036 .driver = { 2037 .name = "omap-sham", 2038 .owner = THIS_MODULE, 2039 .pm = &omap_sham_pm_ops, 2040 .of_match_table = omap_sham_of_match, 2041 }, 2042 }; 2043 2044 module_platform_driver(omap_sham_driver); 2045 2046 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2047 MODULE_LICENSE("GPL v2"); 2048 MODULE_AUTHOR("Dmitry Kasatkin"); 2049 MODULE_ALIAS("platform:omap-sham"); 2050