1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP SHA1/MD5 HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 * 11 * Some ideas are from old omap-sha1-md5.c driver. 12 */ 13 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 16 #include <linux/err.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/irq.h> 24 #include <linux/io.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/of_irq.h> 34 #include <linux/delay.h> 35 #include <linux/crypto.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/algapi.h> 38 #include <crypto/sha.h> 39 #include <crypto/hash.h> 40 #include <crypto/hmac.h> 41 #include <crypto/internal/hash.h> 42 43 #define MD5_DIGEST_SIZE 16 44 45 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 46 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 47 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 48 49 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 50 51 #define SHA_REG_CTRL 0x18 52 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 53 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 54 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 55 #define SHA_REG_CTRL_ALGO (1 << 2) 56 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 57 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 58 59 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 60 61 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 62 #define SHA_REG_MASK_DMA_EN (1 << 3) 63 #define SHA_REG_MASK_IT_EN (1 << 2) 64 #define SHA_REG_MASK_SOFTRESET (1 << 1) 65 #define SHA_REG_AUTOIDLE (1 << 0) 66 67 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 68 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 69 70 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 71 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 72 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 73 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 74 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 75 76 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 77 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 78 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 79 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 80 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 81 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 82 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 83 84 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 85 86 #define SHA_REG_IRQSTATUS 0x118 87 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 88 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 89 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 90 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 91 92 #define SHA_REG_IRQENA 0x11C 93 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 94 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 95 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 96 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 97 98 #define DEFAULT_TIMEOUT_INTERVAL HZ 99 100 #define DEFAULT_AUTOSUSPEND_DELAY 1000 101 102 /* mostly device flags */ 103 #define FLAGS_BUSY 0 104 #define FLAGS_FINAL 1 105 #define FLAGS_DMA_ACTIVE 2 106 #define FLAGS_OUTPUT_READY 3 107 #define FLAGS_INIT 4 108 #define FLAGS_CPU 5 109 #define FLAGS_DMA_READY 6 110 #define FLAGS_AUTO_XOR 7 111 #define FLAGS_BE32_SHA1 8 112 #define FLAGS_SGS_COPIED 9 113 #define FLAGS_SGS_ALLOCED 10 114 #define FLAGS_HUGE 11 115 116 /* context flags */ 117 #define FLAGS_FINUP 16 118 119 #define FLAGS_MODE_SHIFT 18 120 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 126 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 127 128 #define FLAGS_HMAC 21 129 #define FLAGS_ERROR 22 130 131 #define OP_UPDATE 1 132 #define OP_FINAL 2 133 134 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 135 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 136 137 #define BUFLEN SHA512_BLOCK_SIZE 138 #define OMAP_SHA_DMA_THRESHOLD 256 139 140 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048) 141 142 struct omap_sham_dev; 143 144 struct omap_sham_reqctx { 145 struct omap_sham_dev *dd; 146 unsigned long flags; 147 unsigned long op; 148 149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 150 size_t digcnt; 151 size_t bufcnt; 152 size_t buflen; 153 154 /* walk state */ 155 struct scatterlist *sg; 156 struct scatterlist sgl[2]; 157 int offset; /* offset in current sg */ 158 int sg_len; 159 unsigned int total; /* total request */ 160 161 u8 buffer[] OMAP_ALIGNED; 162 }; 163 164 struct omap_sham_hmac_ctx { 165 struct crypto_shash *shash; 166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 168 }; 169 170 struct omap_sham_ctx { 171 struct omap_sham_dev *dd; 172 173 unsigned long flags; 174 175 /* fallback stuff */ 176 struct crypto_shash *fallback; 177 178 struct omap_sham_hmac_ctx base[]; 179 }; 180 181 #define OMAP_SHAM_QUEUE_LENGTH 10 182 183 struct omap_sham_algs_info { 184 struct ahash_alg *algs_list; 185 unsigned int size; 186 unsigned int registered; 187 }; 188 189 struct omap_sham_pdata { 190 struct omap_sham_algs_info *algs_info; 191 unsigned int algs_info_size; 192 unsigned long flags; 193 int digest_size; 194 195 void (*copy_hash)(struct ahash_request *req, int out); 196 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 197 int final, int dma); 198 void (*trigger)(struct omap_sham_dev *dd, size_t length); 199 int (*poll_irq)(struct omap_sham_dev *dd); 200 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 201 202 u32 odigest_ofs; 203 u32 idigest_ofs; 204 u32 din_ofs; 205 u32 digcnt_ofs; 206 u32 rev_ofs; 207 u32 mask_ofs; 208 u32 sysstatus_ofs; 209 u32 mode_ofs; 210 u32 length_ofs; 211 212 u32 major_mask; 213 u32 major_shift; 214 u32 minor_mask; 215 u32 minor_shift; 216 }; 217 218 struct omap_sham_dev { 219 struct list_head list; 220 unsigned long phys_base; 221 struct device *dev; 222 void __iomem *io_base; 223 int irq; 224 spinlock_t lock; 225 int err; 226 struct dma_chan *dma_lch; 227 struct tasklet_struct done_task; 228 u8 polling_mode; 229 u8 xmit_buf[BUFLEN] OMAP_ALIGNED; 230 231 unsigned long flags; 232 int fallback_sz; 233 struct crypto_queue queue; 234 struct ahash_request *req; 235 236 const struct omap_sham_pdata *pdata; 237 }; 238 239 struct omap_sham_drv { 240 struct list_head dev_list; 241 spinlock_t lock; 242 unsigned long flags; 243 }; 244 245 static struct omap_sham_drv sham = { 246 .dev_list = LIST_HEAD_INIT(sham.dev_list), 247 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 248 }; 249 250 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 251 { 252 return __raw_readl(dd->io_base + offset); 253 } 254 255 static inline void omap_sham_write(struct omap_sham_dev *dd, 256 u32 offset, u32 value) 257 { 258 __raw_writel(value, dd->io_base + offset); 259 } 260 261 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 262 u32 value, u32 mask) 263 { 264 u32 val; 265 266 val = omap_sham_read(dd, address); 267 val &= ~mask; 268 val |= value; 269 omap_sham_write(dd, address, val); 270 } 271 272 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 273 { 274 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 275 276 while (!(omap_sham_read(dd, offset) & bit)) { 277 if (time_is_before_jiffies(timeout)) 278 return -ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 285 { 286 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 287 struct omap_sham_dev *dd = ctx->dd; 288 u32 *hash = (u32 *)ctx->digest; 289 int i; 290 291 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 292 if (out) 293 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 294 else 295 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 296 } 297 } 298 299 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 300 { 301 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 302 struct omap_sham_dev *dd = ctx->dd; 303 int i; 304 305 if (ctx->flags & BIT(FLAGS_HMAC)) { 306 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 307 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 308 struct omap_sham_hmac_ctx *bctx = tctx->base; 309 u32 *opad = (u32 *)bctx->opad; 310 311 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 312 if (out) 313 opad[i] = omap_sham_read(dd, 314 SHA_REG_ODIGEST(dd, i)); 315 else 316 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 317 opad[i]); 318 } 319 } 320 321 omap_sham_copy_hash_omap2(req, out); 322 } 323 324 static void omap_sham_copy_ready_hash(struct ahash_request *req) 325 { 326 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 327 u32 *in = (u32 *)ctx->digest; 328 u32 *hash = (u32 *)req->result; 329 int i, d, big_endian = 0; 330 331 if (!hash) 332 return; 333 334 switch (ctx->flags & FLAGS_MODE_MASK) { 335 case FLAGS_MODE_MD5: 336 d = MD5_DIGEST_SIZE / sizeof(u32); 337 break; 338 case FLAGS_MODE_SHA1: 339 /* OMAP2 SHA1 is big endian */ 340 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 341 big_endian = 1; 342 d = SHA1_DIGEST_SIZE / sizeof(u32); 343 break; 344 case FLAGS_MODE_SHA224: 345 d = SHA224_DIGEST_SIZE / sizeof(u32); 346 break; 347 case FLAGS_MODE_SHA256: 348 d = SHA256_DIGEST_SIZE / sizeof(u32); 349 break; 350 case FLAGS_MODE_SHA384: 351 d = SHA384_DIGEST_SIZE / sizeof(u32); 352 break; 353 case FLAGS_MODE_SHA512: 354 d = SHA512_DIGEST_SIZE / sizeof(u32); 355 break; 356 default: 357 d = 0; 358 } 359 360 if (big_endian) 361 for (i = 0; i < d; i++) 362 hash[i] = be32_to_cpu(in[i]); 363 else 364 for (i = 0; i < d; i++) 365 hash[i] = le32_to_cpu(in[i]); 366 } 367 368 static int omap_sham_hw_init(struct omap_sham_dev *dd) 369 { 370 int err; 371 372 err = pm_runtime_get_sync(dd->dev); 373 if (err < 0) { 374 dev_err(dd->dev, "failed to get sync: %d\n", err); 375 return err; 376 } 377 378 if (!test_bit(FLAGS_INIT, &dd->flags)) { 379 set_bit(FLAGS_INIT, &dd->flags); 380 dd->err = 0; 381 } 382 383 return 0; 384 } 385 386 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 387 int final, int dma) 388 { 389 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 390 u32 val = length << 5, mask; 391 392 if (likely(ctx->digcnt)) 393 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 394 395 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 396 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 397 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 398 /* 399 * Setting ALGO_CONST only for the first iteration 400 * and CLOSE_HASH only for the last one. 401 */ 402 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 403 val |= SHA_REG_CTRL_ALGO; 404 if (!ctx->digcnt) 405 val |= SHA_REG_CTRL_ALGO_CONST; 406 if (final) 407 val |= SHA_REG_CTRL_CLOSE_HASH; 408 409 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 410 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 411 412 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 413 } 414 415 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 416 { 417 } 418 419 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 420 { 421 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 422 } 423 424 static int get_block_size(struct omap_sham_reqctx *ctx) 425 { 426 int d; 427 428 switch (ctx->flags & FLAGS_MODE_MASK) { 429 case FLAGS_MODE_MD5: 430 case FLAGS_MODE_SHA1: 431 d = SHA1_BLOCK_SIZE; 432 break; 433 case FLAGS_MODE_SHA224: 434 case FLAGS_MODE_SHA256: 435 d = SHA256_BLOCK_SIZE; 436 break; 437 case FLAGS_MODE_SHA384: 438 case FLAGS_MODE_SHA512: 439 d = SHA512_BLOCK_SIZE; 440 break; 441 default: 442 d = 0; 443 } 444 445 return d; 446 } 447 448 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 449 u32 *value, int count) 450 { 451 for (; count--; value++, offset += 4) 452 omap_sham_write(dd, offset, *value); 453 } 454 455 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 456 int final, int dma) 457 { 458 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 459 u32 val, mask; 460 461 /* 462 * Setting ALGO_CONST only for the first iteration and 463 * CLOSE_HASH only for the last one. Note that flags mode bits 464 * correspond to algorithm encoding in mode register. 465 */ 466 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 467 if (!ctx->digcnt) { 468 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 469 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 470 struct omap_sham_hmac_ctx *bctx = tctx->base; 471 int bs, nr_dr; 472 473 val |= SHA_REG_MODE_ALGO_CONSTANT; 474 475 if (ctx->flags & BIT(FLAGS_HMAC)) { 476 bs = get_block_size(ctx); 477 nr_dr = bs / (2 * sizeof(u32)); 478 val |= SHA_REG_MODE_HMAC_KEY_PROC; 479 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 480 (u32 *)bctx->ipad, nr_dr); 481 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 482 (u32 *)bctx->ipad + nr_dr, nr_dr); 483 ctx->digcnt += bs; 484 } 485 } 486 487 if (final) { 488 val |= SHA_REG_MODE_CLOSE_HASH; 489 490 if (ctx->flags & BIT(FLAGS_HMAC)) 491 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 492 } 493 494 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 495 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 496 SHA_REG_MODE_HMAC_KEY_PROC; 497 498 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 499 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 500 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 501 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 502 SHA_REG_MASK_IT_EN | 503 (dma ? SHA_REG_MASK_DMA_EN : 0), 504 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 505 } 506 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 508 { 509 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 510 } 511 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 513 { 514 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 515 SHA_REG_IRQSTATUS_INPUT_RDY); 516 } 517 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, 519 int final) 520 { 521 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 522 int count, len32, bs32, offset = 0; 523 const u32 *buffer; 524 int mlen; 525 struct sg_mapping_iter mi; 526 527 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 528 ctx->digcnt, length, final); 529 530 dd->pdata->write_ctrl(dd, length, final, 0); 531 dd->pdata->trigger(dd, length); 532 533 /* should be non-zero before next lines to disable clocks later */ 534 ctx->digcnt += length; 535 ctx->total -= length; 536 537 if (final) 538 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 539 540 set_bit(FLAGS_CPU, &dd->flags); 541 542 len32 = DIV_ROUND_UP(length, sizeof(u32)); 543 bs32 = get_block_size(ctx) / sizeof(u32); 544 545 sg_miter_start(&mi, ctx->sg, ctx->sg_len, 546 SG_MITER_FROM_SG | SG_MITER_ATOMIC); 547 548 mlen = 0; 549 550 while (len32) { 551 if (dd->pdata->poll_irq(dd)) 552 return -ETIMEDOUT; 553 554 for (count = 0; count < min(len32, bs32); count++, offset++) { 555 if (!mlen) { 556 sg_miter_next(&mi); 557 mlen = mi.length; 558 if (!mlen) { 559 pr_err("sg miter failure.\n"); 560 return -EINVAL; 561 } 562 offset = 0; 563 buffer = mi.addr; 564 } 565 omap_sham_write(dd, SHA_REG_DIN(dd, count), 566 buffer[offset]); 567 mlen -= 4; 568 } 569 len32 -= min(len32, bs32); 570 } 571 572 sg_miter_stop(&mi); 573 574 return -EINPROGRESS; 575 } 576 577 static void omap_sham_dma_callback(void *param) 578 { 579 struct omap_sham_dev *dd = param; 580 581 set_bit(FLAGS_DMA_READY, &dd->flags); 582 tasklet_schedule(&dd->done_task); 583 } 584 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, 586 int final) 587 { 588 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 589 struct dma_async_tx_descriptor *tx; 590 struct dma_slave_config cfg; 591 int ret; 592 593 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 594 ctx->digcnt, length, final); 595 596 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { 597 dev_err(dd->dev, "dma_map_sg error\n"); 598 return -EINVAL; 599 } 600 601 memset(&cfg, 0, sizeof(cfg)); 602 603 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 604 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 605 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; 606 607 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 608 if (ret) { 609 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 610 return ret; 611 } 612 613 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, 614 DMA_MEM_TO_DEV, 615 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 616 617 if (!tx) { 618 dev_err(dd->dev, "prep_slave_sg failed\n"); 619 return -EINVAL; 620 } 621 622 tx->callback = omap_sham_dma_callback; 623 tx->callback_param = dd; 624 625 dd->pdata->write_ctrl(dd, length, final, 1); 626 627 ctx->digcnt += length; 628 ctx->total -= length; 629 630 if (final) 631 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 632 633 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 634 635 dmaengine_submit(tx); 636 dma_async_issue_pending(dd->dma_lch); 637 638 dd->pdata->trigger(dd, length); 639 640 return -EINPROGRESS; 641 } 642 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, 644 struct scatterlist *sg, int bs, int new_len) 645 { 646 int n = sg_nents(sg); 647 struct scatterlist *tmp; 648 int offset = ctx->offset; 649 650 ctx->total = new_len; 651 652 if (ctx->bufcnt) 653 n++; 654 655 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 656 if (!ctx->sg) 657 return -ENOMEM; 658 659 sg_init_table(ctx->sg, n); 660 661 tmp = ctx->sg; 662 663 ctx->sg_len = 0; 664 665 if (ctx->bufcnt) { 666 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 667 tmp = sg_next(tmp); 668 ctx->sg_len++; 669 new_len -= ctx->bufcnt; 670 } 671 672 while (sg && new_len) { 673 int len = sg->length - offset; 674 675 if (len <= 0) { 676 offset -= sg->length; 677 sg = sg_next(sg); 678 continue; 679 } 680 681 if (new_len < len) 682 len = new_len; 683 684 if (len > 0) { 685 new_len -= len; 686 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset); 687 offset = 0; 688 ctx->offset = 0; 689 ctx->sg_len++; 690 if (new_len <= 0) 691 break; 692 tmp = sg_next(tmp); 693 } 694 695 sg = sg_next(sg); 696 } 697 698 if (tmp) 699 sg_mark_end(tmp); 700 701 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); 702 703 ctx->offset += new_len - ctx->bufcnt; 704 ctx->bufcnt = 0; 705 706 return 0; 707 } 708 709 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, 710 struct scatterlist *sg, int bs, 711 unsigned int new_len) 712 { 713 int pages; 714 void *buf; 715 716 pages = get_order(new_len); 717 718 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 719 if (!buf) { 720 pr_err("Couldn't allocate pages for unaligned cases.\n"); 721 return -ENOMEM; 722 } 723 724 if (ctx->bufcnt) 725 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 726 727 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, 728 min(new_len, ctx->total) - ctx->bufcnt, 0); 729 sg_init_table(ctx->sgl, 1); 730 sg_set_buf(ctx->sgl, buf, new_len); 731 ctx->sg = ctx->sgl; 732 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); 733 ctx->sg_len = 1; 734 ctx->offset += new_len - ctx->bufcnt; 735 ctx->bufcnt = 0; 736 ctx->total = new_len; 737 738 return 0; 739 } 740 741 static int omap_sham_align_sgs(struct scatterlist *sg, 742 int nbytes, int bs, bool final, 743 struct omap_sham_reqctx *rctx) 744 { 745 int n = 0; 746 bool aligned = true; 747 bool list_ok = true; 748 struct scatterlist *sg_tmp = sg; 749 int new_len; 750 int offset = rctx->offset; 751 int bufcnt = rctx->bufcnt; 752 753 if (!sg || !sg->length || !nbytes) 754 return 0; 755 756 new_len = nbytes; 757 758 if (offset) 759 list_ok = false; 760 761 if (final) 762 new_len = DIV_ROUND_UP(new_len, bs) * bs; 763 else 764 new_len = (new_len - 1) / bs * bs; 765 766 if (!new_len) 767 return 0; 768 769 if (nbytes != new_len) 770 list_ok = false; 771 772 while (nbytes > 0 && sg_tmp) { 773 n++; 774 775 if (bufcnt) { 776 if (!IS_ALIGNED(bufcnt, bs)) { 777 aligned = false; 778 break; 779 } 780 nbytes -= bufcnt; 781 bufcnt = 0; 782 if (!nbytes) 783 list_ok = false; 784 785 continue; 786 } 787 788 #ifdef CONFIG_ZONE_DMA 789 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { 790 aligned = false; 791 break; 792 } 793 #endif 794 795 if (offset < sg_tmp->length) { 796 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { 797 aligned = false; 798 break; 799 } 800 801 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { 802 aligned = false; 803 break; 804 } 805 } 806 807 if (offset) { 808 offset -= sg_tmp->length; 809 if (offset < 0) { 810 nbytes += offset; 811 offset = 0; 812 } 813 } else { 814 nbytes -= sg_tmp->length; 815 } 816 817 sg_tmp = sg_next(sg_tmp); 818 819 if (nbytes < 0) { 820 list_ok = false; 821 break; 822 } 823 } 824 825 if (new_len > OMAP_SHA_MAX_DMA_LEN) { 826 new_len = OMAP_SHA_MAX_DMA_LEN; 827 aligned = false; 828 } 829 830 if (!aligned) 831 return omap_sham_copy_sgs(rctx, sg, bs, new_len); 832 else if (!list_ok) 833 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); 834 835 rctx->total = new_len; 836 rctx->offset += new_len; 837 rctx->sg_len = n; 838 if (rctx->bufcnt) { 839 sg_init_table(rctx->sgl, 2); 840 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); 841 sg_chain(rctx->sgl, 2, sg); 842 rctx->sg = rctx->sgl; 843 } else { 844 rctx->sg = sg; 845 } 846 847 return 0; 848 } 849 850 static int omap_sham_prepare_request(struct ahash_request *req, bool update) 851 { 852 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 853 int bs; 854 int ret; 855 unsigned int nbytes; 856 bool final = rctx->flags & BIT(FLAGS_FINUP); 857 int hash_later; 858 859 bs = get_block_size(rctx); 860 861 nbytes = rctx->bufcnt; 862 863 if (update) 864 nbytes += req->nbytes - rctx->offset; 865 866 dev_dbg(rctx->dd->dev, 867 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n", 868 __func__, nbytes, bs, rctx->total, rctx->offset, 869 rctx->bufcnt); 870 871 if (!nbytes) 872 return 0; 873 874 rctx->total = nbytes; 875 876 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { 877 int len = bs - rctx->bufcnt % bs; 878 879 if (len > req->nbytes) 880 len = req->nbytes; 881 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, 882 0, len, 0); 883 rctx->bufcnt += len; 884 rctx->offset = len; 885 } 886 887 if (rctx->bufcnt) 888 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); 889 890 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); 891 if (ret) 892 return ret; 893 894 hash_later = nbytes - rctx->total; 895 if (hash_later < 0) 896 hash_later = 0; 897 898 if (hash_later) { 899 scatterwalk_map_and_copy(rctx->buffer, 900 req->src, 901 req->nbytes - hash_later, 902 hash_later, 0); 903 904 rctx->bufcnt = hash_later; 905 } else { 906 rctx->bufcnt = 0; 907 } 908 909 if (hash_later > rctx->buflen) 910 set_bit(FLAGS_HUGE, &rctx->dd->flags); 911 912 rctx->total = min(nbytes, rctx->total); 913 914 return 0; 915 } 916 917 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 918 { 919 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 920 921 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 922 923 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); 924 925 return 0; 926 } 927 928 static int omap_sham_init(struct ahash_request *req) 929 { 930 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 931 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 932 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 933 struct omap_sham_dev *dd = NULL, *tmp; 934 int bs = 0; 935 936 spin_lock_bh(&sham.lock); 937 if (!tctx->dd) { 938 list_for_each_entry(tmp, &sham.dev_list, list) { 939 dd = tmp; 940 break; 941 } 942 tctx->dd = dd; 943 } else { 944 dd = tctx->dd; 945 } 946 spin_unlock_bh(&sham.lock); 947 948 ctx->dd = dd; 949 950 ctx->flags = 0; 951 952 dev_dbg(dd->dev, "init: digest size: %d\n", 953 crypto_ahash_digestsize(tfm)); 954 955 switch (crypto_ahash_digestsize(tfm)) { 956 case MD5_DIGEST_SIZE: 957 ctx->flags |= FLAGS_MODE_MD5; 958 bs = SHA1_BLOCK_SIZE; 959 break; 960 case SHA1_DIGEST_SIZE: 961 ctx->flags |= FLAGS_MODE_SHA1; 962 bs = SHA1_BLOCK_SIZE; 963 break; 964 case SHA224_DIGEST_SIZE: 965 ctx->flags |= FLAGS_MODE_SHA224; 966 bs = SHA224_BLOCK_SIZE; 967 break; 968 case SHA256_DIGEST_SIZE: 969 ctx->flags |= FLAGS_MODE_SHA256; 970 bs = SHA256_BLOCK_SIZE; 971 break; 972 case SHA384_DIGEST_SIZE: 973 ctx->flags |= FLAGS_MODE_SHA384; 974 bs = SHA384_BLOCK_SIZE; 975 break; 976 case SHA512_DIGEST_SIZE: 977 ctx->flags |= FLAGS_MODE_SHA512; 978 bs = SHA512_BLOCK_SIZE; 979 break; 980 } 981 982 ctx->bufcnt = 0; 983 ctx->digcnt = 0; 984 ctx->total = 0; 985 ctx->offset = 0; 986 ctx->buflen = BUFLEN; 987 988 if (tctx->flags & BIT(FLAGS_HMAC)) { 989 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 990 struct omap_sham_hmac_ctx *bctx = tctx->base; 991 992 memcpy(ctx->buffer, bctx->ipad, bs); 993 ctx->bufcnt = bs; 994 } 995 996 ctx->flags |= BIT(FLAGS_HMAC); 997 } 998 999 return 0; 1000 1001 } 1002 1003 static int omap_sham_update_req(struct omap_sham_dev *dd) 1004 { 1005 struct ahash_request *req = dd->req; 1006 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1007 int err; 1008 bool final = (ctx->flags & BIT(FLAGS_FINUP)) && 1009 !(dd->flags & BIT(FLAGS_HUGE)); 1010 1011 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d", 1012 ctx->total, ctx->digcnt, final); 1013 1014 if (ctx->total < get_block_size(ctx) || 1015 ctx->total < dd->fallback_sz) 1016 ctx->flags |= BIT(FLAGS_CPU); 1017 1018 if (ctx->flags & BIT(FLAGS_CPU)) 1019 err = omap_sham_xmit_cpu(dd, ctx->total, final); 1020 else 1021 err = omap_sham_xmit_dma(dd, ctx->total, final); 1022 1023 /* wait for dma completion before can take more data */ 1024 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 1025 1026 return err; 1027 } 1028 1029 static int omap_sham_final_req(struct omap_sham_dev *dd) 1030 { 1031 struct ahash_request *req = dd->req; 1032 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1033 int err = 0, use_dma = 1; 1034 1035 if (dd->flags & BIT(FLAGS_HUGE)) 1036 return 0; 1037 1038 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) 1039 /* 1040 * faster to handle last block with cpu or 1041 * use cpu when dma is not present. 1042 */ 1043 use_dma = 0; 1044 1045 if (use_dma) 1046 err = omap_sham_xmit_dma(dd, ctx->total, 1); 1047 else 1048 err = omap_sham_xmit_cpu(dd, ctx->total, 1); 1049 1050 ctx->bufcnt = 0; 1051 1052 dev_dbg(dd->dev, "final_req: err: %d\n", err); 1053 1054 return err; 1055 } 1056 1057 static int omap_sham_finish_hmac(struct ahash_request *req) 1058 { 1059 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1060 struct omap_sham_hmac_ctx *bctx = tctx->base; 1061 int bs = crypto_shash_blocksize(bctx->shash); 1062 int ds = crypto_shash_digestsize(bctx->shash); 1063 SHASH_DESC_ON_STACK(shash, bctx->shash); 1064 1065 shash->tfm = bctx->shash; 1066 1067 return crypto_shash_init(shash) ?: 1068 crypto_shash_update(shash, bctx->opad, bs) ?: 1069 crypto_shash_finup(shash, req->result, ds, req->result); 1070 } 1071 1072 static int omap_sham_finish(struct ahash_request *req) 1073 { 1074 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1075 struct omap_sham_dev *dd = ctx->dd; 1076 int err = 0; 1077 1078 if (ctx->digcnt) { 1079 omap_sham_copy_ready_hash(req); 1080 if ((ctx->flags & BIT(FLAGS_HMAC)) && 1081 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 1082 err = omap_sham_finish_hmac(req); 1083 } 1084 1085 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 1086 1087 return err; 1088 } 1089 1090 static void omap_sham_finish_req(struct ahash_request *req, int err) 1091 { 1092 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1093 struct omap_sham_dev *dd = ctx->dd; 1094 1095 if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) 1096 free_pages((unsigned long)sg_virt(ctx->sg), 1097 get_order(ctx->sg->length)); 1098 1099 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) 1100 kfree(ctx->sg); 1101 1102 ctx->sg = NULL; 1103 1104 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); 1105 1106 if (dd->flags & BIT(FLAGS_HUGE)) { 1107 dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | 1108 BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE)); 1109 omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1110 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { 1111 err = omap_sham_update_req(dd); 1112 if (err != -EINPROGRESS && 1113 (ctx->flags & BIT(FLAGS_FINUP))) 1114 err = omap_sham_final_req(dd); 1115 } else if (ctx->op == OP_FINAL) { 1116 omap_sham_final_req(dd); 1117 } 1118 return; 1119 } 1120 1121 if (!err) { 1122 dd->pdata->copy_hash(req, 1); 1123 if (test_bit(FLAGS_FINAL, &dd->flags)) 1124 err = omap_sham_finish(req); 1125 } else { 1126 ctx->flags |= BIT(FLAGS_ERROR); 1127 } 1128 1129 /* atomic operation is not needed here */ 1130 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1131 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1132 1133 pm_runtime_mark_last_busy(dd->dev); 1134 pm_runtime_put_autosuspend(dd->dev); 1135 1136 ctx->offset = 0; 1137 1138 if (req->base.complete) 1139 req->base.complete(&req->base, err); 1140 } 1141 1142 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1143 struct ahash_request *req) 1144 { 1145 struct crypto_async_request *async_req, *backlog; 1146 struct omap_sham_reqctx *ctx; 1147 unsigned long flags; 1148 int err = 0, ret = 0; 1149 1150 retry: 1151 spin_lock_irqsave(&dd->lock, flags); 1152 if (req) 1153 ret = ahash_enqueue_request(&dd->queue, req); 1154 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1155 spin_unlock_irqrestore(&dd->lock, flags); 1156 return ret; 1157 } 1158 backlog = crypto_get_backlog(&dd->queue); 1159 async_req = crypto_dequeue_request(&dd->queue); 1160 if (async_req) 1161 set_bit(FLAGS_BUSY, &dd->flags); 1162 spin_unlock_irqrestore(&dd->lock, flags); 1163 1164 if (!async_req) 1165 return ret; 1166 1167 if (backlog) 1168 backlog->complete(backlog, -EINPROGRESS); 1169 1170 req = ahash_request_cast(async_req); 1171 dd->req = req; 1172 ctx = ahash_request_ctx(req); 1173 1174 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1175 if (err || !ctx->total) 1176 goto err1; 1177 1178 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1179 ctx->op, req->nbytes); 1180 1181 err = omap_sham_hw_init(dd); 1182 if (err) 1183 goto err1; 1184 1185 if (ctx->digcnt) 1186 /* request has changed - restore hash */ 1187 dd->pdata->copy_hash(req, 0); 1188 1189 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { 1190 err = omap_sham_update_req(dd); 1191 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1192 /* no final() after finup() */ 1193 err = omap_sham_final_req(dd); 1194 } else if (ctx->op == OP_FINAL) { 1195 err = omap_sham_final_req(dd); 1196 } 1197 err1: 1198 dev_dbg(dd->dev, "exit, err: %d\n", err); 1199 1200 if (err != -EINPROGRESS) { 1201 /* done_task will not finish it, so do it here */ 1202 omap_sham_finish_req(req, err); 1203 req = NULL; 1204 1205 /* 1206 * Execute next request immediately if there is anything 1207 * in queue. 1208 */ 1209 goto retry; 1210 } 1211 1212 return ret; 1213 } 1214 1215 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1216 { 1217 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1218 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1219 struct omap_sham_dev *dd = tctx->dd; 1220 1221 ctx->op = op; 1222 1223 return omap_sham_handle_queue(dd, req); 1224 } 1225 1226 static int omap_sham_update(struct ahash_request *req) 1227 { 1228 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1229 struct omap_sham_dev *dd = ctx->dd; 1230 1231 if (!req->nbytes) 1232 return 0; 1233 1234 if (ctx->bufcnt + req->nbytes <= ctx->buflen) { 1235 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1236 0, req->nbytes, 0); 1237 ctx->bufcnt += req->nbytes; 1238 return 0; 1239 } 1240 1241 if (dd->polling_mode) 1242 ctx->flags |= BIT(FLAGS_CPU); 1243 1244 return omap_sham_enqueue(req, OP_UPDATE); 1245 } 1246 1247 static int omap_sham_final_shash(struct ahash_request *req) 1248 { 1249 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1250 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1251 int offset = 0; 1252 1253 /* 1254 * If we are running HMAC on limited hardware support, skip 1255 * the ipad in the beginning of the buffer if we are going for 1256 * software fallback algorithm. 1257 */ 1258 if (test_bit(FLAGS_HMAC, &ctx->flags) && 1259 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) 1260 offset = get_block_size(ctx); 1261 1262 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset, 1263 ctx->bufcnt - offset, req->result); 1264 } 1265 1266 static int omap_sham_final(struct ahash_request *req) 1267 { 1268 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1269 1270 ctx->flags |= BIT(FLAGS_FINUP); 1271 1272 if (ctx->flags & BIT(FLAGS_ERROR)) 1273 return 0; /* uncompleted hash is not needed */ 1274 1275 /* 1276 * OMAP HW accel works only with buffers >= 9. 1277 * HMAC is always >= 9 because ipad == block size. 1278 * If buffersize is less than fallback_sz, we use fallback 1279 * SW encoding, as using DMA + HW in this case doesn't provide 1280 * any benefit. 1281 */ 1282 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) 1283 return omap_sham_final_shash(req); 1284 else if (ctx->bufcnt) 1285 return omap_sham_enqueue(req, OP_FINAL); 1286 1287 /* copy ready hash (+ finalize hmac) */ 1288 return omap_sham_finish(req); 1289 } 1290 1291 static int omap_sham_finup(struct ahash_request *req) 1292 { 1293 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1294 int err1, err2; 1295 1296 ctx->flags |= BIT(FLAGS_FINUP); 1297 1298 err1 = omap_sham_update(req); 1299 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1300 return err1; 1301 /* 1302 * final() has to be always called to cleanup resources 1303 * even if udpate() failed, except EINPROGRESS 1304 */ 1305 err2 = omap_sham_final(req); 1306 1307 return err1 ?: err2; 1308 } 1309 1310 static int omap_sham_digest(struct ahash_request *req) 1311 { 1312 return omap_sham_init(req) ?: omap_sham_finup(req); 1313 } 1314 1315 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1316 unsigned int keylen) 1317 { 1318 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1319 struct omap_sham_hmac_ctx *bctx = tctx->base; 1320 int bs = crypto_shash_blocksize(bctx->shash); 1321 int ds = crypto_shash_digestsize(bctx->shash); 1322 struct omap_sham_dev *dd = NULL, *tmp; 1323 int err, i; 1324 1325 spin_lock_bh(&sham.lock); 1326 if (!tctx->dd) { 1327 list_for_each_entry(tmp, &sham.dev_list, list) { 1328 dd = tmp; 1329 break; 1330 } 1331 tctx->dd = dd; 1332 } else { 1333 dd = tctx->dd; 1334 } 1335 spin_unlock_bh(&sham.lock); 1336 1337 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1338 if (err) 1339 return err; 1340 1341 if (keylen > bs) { 1342 err = crypto_shash_tfm_digest(bctx->shash, key, keylen, 1343 bctx->ipad); 1344 if (err) 1345 return err; 1346 keylen = ds; 1347 } else { 1348 memcpy(bctx->ipad, key, keylen); 1349 } 1350 1351 memset(bctx->ipad + keylen, 0, bs - keylen); 1352 1353 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1354 memcpy(bctx->opad, bctx->ipad, bs); 1355 1356 for (i = 0; i < bs; i++) { 1357 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 1358 bctx->opad[i] ^= HMAC_OPAD_VALUE; 1359 } 1360 } 1361 1362 return err; 1363 } 1364 1365 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1366 { 1367 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1368 const char *alg_name = crypto_tfm_alg_name(tfm); 1369 1370 /* Allocate a fallback and abort if it failed. */ 1371 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1372 CRYPTO_ALG_NEED_FALLBACK); 1373 if (IS_ERR(tctx->fallback)) { 1374 pr_err("omap-sham: fallback driver '%s' " 1375 "could not be loaded.\n", alg_name); 1376 return PTR_ERR(tctx->fallback); 1377 } 1378 1379 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1380 sizeof(struct omap_sham_reqctx) + BUFLEN); 1381 1382 if (alg_base) { 1383 struct omap_sham_hmac_ctx *bctx = tctx->base; 1384 tctx->flags |= BIT(FLAGS_HMAC); 1385 bctx->shash = crypto_alloc_shash(alg_base, 0, 1386 CRYPTO_ALG_NEED_FALLBACK); 1387 if (IS_ERR(bctx->shash)) { 1388 pr_err("omap-sham: base driver '%s' " 1389 "could not be loaded.\n", alg_base); 1390 crypto_free_shash(tctx->fallback); 1391 return PTR_ERR(bctx->shash); 1392 } 1393 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1400 { 1401 return omap_sham_cra_init_alg(tfm, NULL); 1402 } 1403 1404 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1405 { 1406 return omap_sham_cra_init_alg(tfm, "sha1"); 1407 } 1408 1409 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1410 { 1411 return omap_sham_cra_init_alg(tfm, "sha224"); 1412 } 1413 1414 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1415 { 1416 return omap_sham_cra_init_alg(tfm, "sha256"); 1417 } 1418 1419 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1420 { 1421 return omap_sham_cra_init_alg(tfm, "md5"); 1422 } 1423 1424 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1425 { 1426 return omap_sham_cra_init_alg(tfm, "sha384"); 1427 } 1428 1429 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1430 { 1431 return omap_sham_cra_init_alg(tfm, "sha512"); 1432 } 1433 1434 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1435 { 1436 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1437 1438 crypto_free_shash(tctx->fallback); 1439 tctx->fallback = NULL; 1440 1441 if (tctx->flags & BIT(FLAGS_HMAC)) { 1442 struct omap_sham_hmac_ctx *bctx = tctx->base; 1443 crypto_free_shash(bctx->shash); 1444 } 1445 } 1446 1447 static int omap_sham_export(struct ahash_request *req, void *out) 1448 { 1449 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1450 1451 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); 1452 1453 return 0; 1454 } 1455 1456 static int omap_sham_import(struct ahash_request *req, const void *in) 1457 { 1458 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1459 const struct omap_sham_reqctx *ctx_in = in; 1460 1461 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); 1462 1463 return 0; 1464 } 1465 1466 static struct ahash_alg algs_sha1_md5[] = { 1467 { 1468 .init = omap_sham_init, 1469 .update = omap_sham_update, 1470 .final = omap_sham_final, 1471 .finup = omap_sham_finup, 1472 .digest = omap_sham_digest, 1473 .halg.digestsize = SHA1_DIGEST_SIZE, 1474 .halg.base = { 1475 .cra_name = "sha1", 1476 .cra_driver_name = "omap-sha1", 1477 .cra_priority = 400, 1478 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1479 CRYPTO_ALG_ASYNC | 1480 CRYPTO_ALG_NEED_FALLBACK, 1481 .cra_blocksize = SHA1_BLOCK_SIZE, 1482 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1483 .cra_alignmask = OMAP_ALIGN_MASK, 1484 .cra_module = THIS_MODULE, 1485 .cra_init = omap_sham_cra_init, 1486 .cra_exit = omap_sham_cra_exit, 1487 } 1488 }, 1489 { 1490 .init = omap_sham_init, 1491 .update = omap_sham_update, 1492 .final = omap_sham_final, 1493 .finup = omap_sham_finup, 1494 .digest = omap_sham_digest, 1495 .halg.digestsize = MD5_DIGEST_SIZE, 1496 .halg.base = { 1497 .cra_name = "md5", 1498 .cra_driver_name = "omap-md5", 1499 .cra_priority = 400, 1500 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1501 CRYPTO_ALG_ASYNC | 1502 CRYPTO_ALG_NEED_FALLBACK, 1503 .cra_blocksize = SHA1_BLOCK_SIZE, 1504 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1505 .cra_alignmask = OMAP_ALIGN_MASK, 1506 .cra_module = THIS_MODULE, 1507 .cra_init = omap_sham_cra_init, 1508 .cra_exit = omap_sham_cra_exit, 1509 } 1510 }, 1511 { 1512 .init = omap_sham_init, 1513 .update = omap_sham_update, 1514 .final = omap_sham_final, 1515 .finup = omap_sham_finup, 1516 .digest = omap_sham_digest, 1517 .setkey = omap_sham_setkey, 1518 .halg.digestsize = SHA1_DIGEST_SIZE, 1519 .halg.base = { 1520 .cra_name = "hmac(sha1)", 1521 .cra_driver_name = "omap-hmac-sha1", 1522 .cra_priority = 400, 1523 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1524 CRYPTO_ALG_ASYNC | 1525 CRYPTO_ALG_NEED_FALLBACK, 1526 .cra_blocksize = SHA1_BLOCK_SIZE, 1527 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1528 sizeof(struct omap_sham_hmac_ctx), 1529 .cra_alignmask = OMAP_ALIGN_MASK, 1530 .cra_module = THIS_MODULE, 1531 .cra_init = omap_sham_cra_sha1_init, 1532 .cra_exit = omap_sham_cra_exit, 1533 } 1534 }, 1535 { 1536 .init = omap_sham_init, 1537 .update = omap_sham_update, 1538 .final = omap_sham_final, 1539 .finup = omap_sham_finup, 1540 .digest = omap_sham_digest, 1541 .setkey = omap_sham_setkey, 1542 .halg.digestsize = MD5_DIGEST_SIZE, 1543 .halg.base = { 1544 .cra_name = "hmac(md5)", 1545 .cra_driver_name = "omap-hmac-md5", 1546 .cra_priority = 400, 1547 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1548 CRYPTO_ALG_ASYNC | 1549 CRYPTO_ALG_NEED_FALLBACK, 1550 .cra_blocksize = SHA1_BLOCK_SIZE, 1551 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1552 sizeof(struct omap_sham_hmac_ctx), 1553 .cra_alignmask = OMAP_ALIGN_MASK, 1554 .cra_module = THIS_MODULE, 1555 .cra_init = omap_sham_cra_md5_init, 1556 .cra_exit = omap_sham_cra_exit, 1557 } 1558 } 1559 }; 1560 1561 /* OMAP4 has some algs in addition to what OMAP2 has */ 1562 static struct ahash_alg algs_sha224_sha256[] = { 1563 { 1564 .init = omap_sham_init, 1565 .update = omap_sham_update, 1566 .final = omap_sham_final, 1567 .finup = omap_sham_finup, 1568 .digest = omap_sham_digest, 1569 .halg.digestsize = SHA224_DIGEST_SIZE, 1570 .halg.base = { 1571 .cra_name = "sha224", 1572 .cra_driver_name = "omap-sha224", 1573 .cra_priority = 400, 1574 .cra_flags = CRYPTO_ALG_ASYNC | 1575 CRYPTO_ALG_NEED_FALLBACK, 1576 .cra_blocksize = SHA224_BLOCK_SIZE, 1577 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1578 .cra_alignmask = OMAP_ALIGN_MASK, 1579 .cra_module = THIS_MODULE, 1580 .cra_init = omap_sham_cra_init, 1581 .cra_exit = omap_sham_cra_exit, 1582 } 1583 }, 1584 { 1585 .init = omap_sham_init, 1586 .update = omap_sham_update, 1587 .final = omap_sham_final, 1588 .finup = omap_sham_finup, 1589 .digest = omap_sham_digest, 1590 .halg.digestsize = SHA256_DIGEST_SIZE, 1591 .halg.base = { 1592 .cra_name = "sha256", 1593 .cra_driver_name = "omap-sha256", 1594 .cra_priority = 400, 1595 .cra_flags = CRYPTO_ALG_ASYNC | 1596 CRYPTO_ALG_NEED_FALLBACK, 1597 .cra_blocksize = SHA256_BLOCK_SIZE, 1598 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1599 .cra_alignmask = OMAP_ALIGN_MASK, 1600 .cra_module = THIS_MODULE, 1601 .cra_init = omap_sham_cra_init, 1602 .cra_exit = omap_sham_cra_exit, 1603 } 1604 }, 1605 { 1606 .init = omap_sham_init, 1607 .update = omap_sham_update, 1608 .final = omap_sham_final, 1609 .finup = omap_sham_finup, 1610 .digest = omap_sham_digest, 1611 .setkey = omap_sham_setkey, 1612 .halg.digestsize = SHA224_DIGEST_SIZE, 1613 .halg.base = { 1614 .cra_name = "hmac(sha224)", 1615 .cra_driver_name = "omap-hmac-sha224", 1616 .cra_priority = 400, 1617 .cra_flags = CRYPTO_ALG_ASYNC | 1618 CRYPTO_ALG_NEED_FALLBACK, 1619 .cra_blocksize = SHA224_BLOCK_SIZE, 1620 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1621 sizeof(struct omap_sham_hmac_ctx), 1622 .cra_alignmask = OMAP_ALIGN_MASK, 1623 .cra_module = THIS_MODULE, 1624 .cra_init = omap_sham_cra_sha224_init, 1625 .cra_exit = omap_sham_cra_exit, 1626 } 1627 }, 1628 { 1629 .init = omap_sham_init, 1630 .update = omap_sham_update, 1631 .final = omap_sham_final, 1632 .finup = omap_sham_finup, 1633 .digest = omap_sham_digest, 1634 .setkey = omap_sham_setkey, 1635 .halg.digestsize = SHA256_DIGEST_SIZE, 1636 .halg.base = { 1637 .cra_name = "hmac(sha256)", 1638 .cra_driver_name = "omap-hmac-sha256", 1639 .cra_priority = 400, 1640 .cra_flags = CRYPTO_ALG_ASYNC | 1641 CRYPTO_ALG_NEED_FALLBACK, 1642 .cra_blocksize = SHA256_BLOCK_SIZE, 1643 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1644 sizeof(struct omap_sham_hmac_ctx), 1645 .cra_alignmask = OMAP_ALIGN_MASK, 1646 .cra_module = THIS_MODULE, 1647 .cra_init = omap_sham_cra_sha256_init, 1648 .cra_exit = omap_sham_cra_exit, 1649 } 1650 }, 1651 }; 1652 1653 static struct ahash_alg algs_sha384_sha512[] = { 1654 { 1655 .init = omap_sham_init, 1656 .update = omap_sham_update, 1657 .final = omap_sham_final, 1658 .finup = omap_sham_finup, 1659 .digest = omap_sham_digest, 1660 .halg.digestsize = SHA384_DIGEST_SIZE, 1661 .halg.base = { 1662 .cra_name = "sha384", 1663 .cra_driver_name = "omap-sha384", 1664 .cra_priority = 400, 1665 .cra_flags = CRYPTO_ALG_ASYNC | 1666 CRYPTO_ALG_NEED_FALLBACK, 1667 .cra_blocksize = SHA384_BLOCK_SIZE, 1668 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1669 .cra_alignmask = OMAP_ALIGN_MASK, 1670 .cra_module = THIS_MODULE, 1671 .cra_init = omap_sham_cra_init, 1672 .cra_exit = omap_sham_cra_exit, 1673 } 1674 }, 1675 { 1676 .init = omap_sham_init, 1677 .update = omap_sham_update, 1678 .final = omap_sham_final, 1679 .finup = omap_sham_finup, 1680 .digest = omap_sham_digest, 1681 .halg.digestsize = SHA512_DIGEST_SIZE, 1682 .halg.base = { 1683 .cra_name = "sha512", 1684 .cra_driver_name = "omap-sha512", 1685 .cra_priority = 400, 1686 .cra_flags = CRYPTO_ALG_ASYNC | 1687 CRYPTO_ALG_NEED_FALLBACK, 1688 .cra_blocksize = SHA512_BLOCK_SIZE, 1689 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1690 .cra_alignmask = OMAP_ALIGN_MASK, 1691 .cra_module = THIS_MODULE, 1692 .cra_init = omap_sham_cra_init, 1693 .cra_exit = omap_sham_cra_exit, 1694 } 1695 }, 1696 { 1697 .init = omap_sham_init, 1698 .update = omap_sham_update, 1699 .final = omap_sham_final, 1700 .finup = omap_sham_finup, 1701 .digest = omap_sham_digest, 1702 .setkey = omap_sham_setkey, 1703 .halg.digestsize = SHA384_DIGEST_SIZE, 1704 .halg.base = { 1705 .cra_name = "hmac(sha384)", 1706 .cra_driver_name = "omap-hmac-sha384", 1707 .cra_priority = 400, 1708 .cra_flags = CRYPTO_ALG_ASYNC | 1709 CRYPTO_ALG_NEED_FALLBACK, 1710 .cra_blocksize = SHA384_BLOCK_SIZE, 1711 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1712 sizeof(struct omap_sham_hmac_ctx), 1713 .cra_alignmask = OMAP_ALIGN_MASK, 1714 .cra_module = THIS_MODULE, 1715 .cra_init = omap_sham_cra_sha384_init, 1716 .cra_exit = omap_sham_cra_exit, 1717 } 1718 }, 1719 { 1720 .init = omap_sham_init, 1721 .update = omap_sham_update, 1722 .final = omap_sham_final, 1723 .finup = omap_sham_finup, 1724 .digest = omap_sham_digest, 1725 .setkey = omap_sham_setkey, 1726 .halg.digestsize = SHA512_DIGEST_SIZE, 1727 .halg.base = { 1728 .cra_name = "hmac(sha512)", 1729 .cra_driver_name = "omap-hmac-sha512", 1730 .cra_priority = 400, 1731 .cra_flags = CRYPTO_ALG_ASYNC | 1732 CRYPTO_ALG_NEED_FALLBACK, 1733 .cra_blocksize = SHA512_BLOCK_SIZE, 1734 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1735 sizeof(struct omap_sham_hmac_ctx), 1736 .cra_alignmask = OMAP_ALIGN_MASK, 1737 .cra_module = THIS_MODULE, 1738 .cra_init = omap_sham_cra_sha512_init, 1739 .cra_exit = omap_sham_cra_exit, 1740 } 1741 }, 1742 }; 1743 1744 static void omap_sham_done_task(unsigned long data) 1745 { 1746 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1747 int err = 0; 1748 1749 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags); 1750 1751 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1752 omap_sham_handle_queue(dd, NULL); 1753 return; 1754 } 1755 1756 if (test_bit(FLAGS_CPU, &dd->flags)) { 1757 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) 1758 goto finish; 1759 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1760 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1761 omap_sham_update_dma_stop(dd); 1762 if (dd->err) { 1763 err = dd->err; 1764 goto finish; 1765 } 1766 } 1767 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1768 /* hash or semi-hash ready */ 1769 clear_bit(FLAGS_DMA_READY, &dd->flags); 1770 goto finish; 1771 } 1772 } 1773 1774 return; 1775 1776 finish: 1777 dev_dbg(dd->dev, "update done: err: %d\n", err); 1778 /* finish curent request */ 1779 omap_sham_finish_req(dd->req, err); 1780 1781 /* If we are not busy, process next req */ 1782 if (!test_bit(FLAGS_BUSY, &dd->flags)) 1783 omap_sham_handle_queue(dd, NULL); 1784 } 1785 1786 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1787 { 1788 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1789 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1790 } else { 1791 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1792 tasklet_schedule(&dd->done_task); 1793 } 1794 1795 return IRQ_HANDLED; 1796 } 1797 1798 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1799 { 1800 struct omap_sham_dev *dd = dev_id; 1801 1802 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1803 /* final -> allow device to go to power-saving mode */ 1804 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1805 1806 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1807 SHA_REG_CTRL_OUTPUT_READY); 1808 omap_sham_read(dd, SHA_REG_CTRL); 1809 1810 return omap_sham_irq_common(dd); 1811 } 1812 1813 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1814 { 1815 struct omap_sham_dev *dd = dev_id; 1816 1817 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1818 1819 return omap_sham_irq_common(dd); 1820 } 1821 1822 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1823 { 1824 .algs_list = algs_sha1_md5, 1825 .size = ARRAY_SIZE(algs_sha1_md5), 1826 }, 1827 }; 1828 1829 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1830 .algs_info = omap_sham_algs_info_omap2, 1831 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1832 .flags = BIT(FLAGS_BE32_SHA1), 1833 .digest_size = SHA1_DIGEST_SIZE, 1834 .copy_hash = omap_sham_copy_hash_omap2, 1835 .write_ctrl = omap_sham_write_ctrl_omap2, 1836 .trigger = omap_sham_trigger_omap2, 1837 .poll_irq = omap_sham_poll_irq_omap2, 1838 .intr_hdlr = omap_sham_irq_omap2, 1839 .idigest_ofs = 0x00, 1840 .din_ofs = 0x1c, 1841 .digcnt_ofs = 0x14, 1842 .rev_ofs = 0x5c, 1843 .mask_ofs = 0x60, 1844 .sysstatus_ofs = 0x64, 1845 .major_mask = 0xf0, 1846 .major_shift = 4, 1847 .minor_mask = 0x0f, 1848 .minor_shift = 0, 1849 }; 1850 1851 #ifdef CONFIG_OF 1852 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1853 { 1854 .algs_list = algs_sha1_md5, 1855 .size = ARRAY_SIZE(algs_sha1_md5), 1856 }, 1857 { 1858 .algs_list = algs_sha224_sha256, 1859 .size = ARRAY_SIZE(algs_sha224_sha256), 1860 }, 1861 }; 1862 1863 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1864 .algs_info = omap_sham_algs_info_omap4, 1865 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1866 .flags = BIT(FLAGS_AUTO_XOR), 1867 .digest_size = SHA256_DIGEST_SIZE, 1868 .copy_hash = omap_sham_copy_hash_omap4, 1869 .write_ctrl = omap_sham_write_ctrl_omap4, 1870 .trigger = omap_sham_trigger_omap4, 1871 .poll_irq = omap_sham_poll_irq_omap4, 1872 .intr_hdlr = omap_sham_irq_omap4, 1873 .idigest_ofs = 0x020, 1874 .odigest_ofs = 0x0, 1875 .din_ofs = 0x080, 1876 .digcnt_ofs = 0x040, 1877 .rev_ofs = 0x100, 1878 .mask_ofs = 0x110, 1879 .sysstatus_ofs = 0x114, 1880 .mode_ofs = 0x44, 1881 .length_ofs = 0x48, 1882 .major_mask = 0x0700, 1883 .major_shift = 8, 1884 .minor_mask = 0x003f, 1885 .minor_shift = 0, 1886 }; 1887 1888 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1889 { 1890 .algs_list = algs_sha1_md5, 1891 .size = ARRAY_SIZE(algs_sha1_md5), 1892 }, 1893 { 1894 .algs_list = algs_sha224_sha256, 1895 .size = ARRAY_SIZE(algs_sha224_sha256), 1896 }, 1897 { 1898 .algs_list = algs_sha384_sha512, 1899 .size = ARRAY_SIZE(algs_sha384_sha512), 1900 }, 1901 }; 1902 1903 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1904 .algs_info = omap_sham_algs_info_omap5, 1905 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1906 .flags = BIT(FLAGS_AUTO_XOR), 1907 .digest_size = SHA512_DIGEST_SIZE, 1908 .copy_hash = omap_sham_copy_hash_omap4, 1909 .write_ctrl = omap_sham_write_ctrl_omap4, 1910 .trigger = omap_sham_trigger_omap4, 1911 .poll_irq = omap_sham_poll_irq_omap4, 1912 .intr_hdlr = omap_sham_irq_omap4, 1913 .idigest_ofs = 0x240, 1914 .odigest_ofs = 0x200, 1915 .din_ofs = 0x080, 1916 .digcnt_ofs = 0x280, 1917 .rev_ofs = 0x100, 1918 .mask_ofs = 0x110, 1919 .sysstatus_ofs = 0x114, 1920 .mode_ofs = 0x284, 1921 .length_ofs = 0x288, 1922 .major_mask = 0x0700, 1923 .major_shift = 8, 1924 .minor_mask = 0x003f, 1925 .minor_shift = 0, 1926 }; 1927 1928 static const struct of_device_id omap_sham_of_match[] = { 1929 { 1930 .compatible = "ti,omap2-sham", 1931 .data = &omap_sham_pdata_omap2, 1932 }, 1933 { 1934 .compatible = "ti,omap3-sham", 1935 .data = &omap_sham_pdata_omap2, 1936 }, 1937 { 1938 .compatible = "ti,omap4-sham", 1939 .data = &omap_sham_pdata_omap4, 1940 }, 1941 { 1942 .compatible = "ti,omap5-sham", 1943 .data = &omap_sham_pdata_omap5, 1944 }, 1945 {}, 1946 }; 1947 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1948 1949 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1950 struct device *dev, struct resource *res) 1951 { 1952 struct device_node *node = dev->of_node; 1953 int err = 0; 1954 1955 dd->pdata = of_device_get_match_data(dev); 1956 if (!dd->pdata) { 1957 dev_err(dev, "no compatible OF match\n"); 1958 err = -EINVAL; 1959 goto err; 1960 } 1961 1962 err = of_address_to_resource(node, 0, res); 1963 if (err < 0) { 1964 dev_err(dev, "can't translate OF node address\n"); 1965 err = -EINVAL; 1966 goto err; 1967 } 1968 1969 dd->irq = irq_of_parse_and_map(node, 0); 1970 if (!dd->irq) { 1971 dev_err(dev, "can't translate OF irq value\n"); 1972 err = -EINVAL; 1973 goto err; 1974 } 1975 1976 err: 1977 return err; 1978 } 1979 #else 1980 static const struct of_device_id omap_sham_of_match[] = { 1981 {}, 1982 }; 1983 1984 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1985 struct device *dev, struct resource *res) 1986 { 1987 return -EINVAL; 1988 } 1989 #endif 1990 1991 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 1992 struct platform_device *pdev, struct resource *res) 1993 { 1994 struct device *dev = &pdev->dev; 1995 struct resource *r; 1996 int err = 0; 1997 1998 /* Get the base address */ 1999 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2000 if (!r) { 2001 dev_err(dev, "no MEM resource info\n"); 2002 err = -ENODEV; 2003 goto err; 2004 } 2005 memcpy(res, r, sizeof(*res)); 2006 2007 /* Get the IRQ */ 2008 dd->irq = platform_get_irq(pdev, 0); 2009 if (dd->irq < 0) { 2010 err = dd->irq; 2011 goto err; 2012 } 2013 2014 /* Only OMAP2/3 can be non-DT */ 2015 dd->pdata = &omap_sham_pdata_omap2; 2016 2017 err: 2018 return err; 2019 } 2020 2021 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 2022 char *buf) 2023 { 2024 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2025 2026 return sprintf(buf, "%d\n", dd->fallback_sz); 2027 } 2028 2029 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 2030 const char *buf, size_t size) 2031 { 2032 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2033 ssize_t status; 2034 long value; 2035 2036 status = kstrtol(buf, 0, &value); 2037 if (status) 2038 return status; 2039 2040 /* HW accelerator only works with buffers > 9 */ 2041 if (value < 9) { 2042 dev_err(dev, "minimum fallback size 9\n"); 2043 return -EINVAL; 2044 } 2045 2046 dd->fallback_sz = value; 2047 2048 return size; 2049 } 2050 2051 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 2052 char *buf) 2053 { 2054 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2055 2056 return sprintf(buf, "%d\n", dd->queue.max_qlen); 2057 } 2058 2059 static ssize_t queue_len_store(struct device *dev, 2060 struct device_attribute *attr, const char *buf, 2061 size_t size) 2062 { 2063 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2064 ssize_t status; 2065 long value; 2066 unsigned long flags; 2067 2068 status = kstrtol(buf, 0, &value); 2069 if (status) 2070 return status; 2071 2072 if (value < 1) 2073 return -EINVAL; 2074 2075 /* 2076 * Changing the queue size in fly is safe, if size becomes smaller 2077 * than current size, it will just not accept new entries until 2078 * it has shrank enough. 2079 */ 2080 spin_lock_irqsave(&dd->lock, flags); 2081 dd->queue.max_qlen = value; 2082 spin_unlock_irqrestore(&dd->lock, flags); 2083 2084 return size; 2085 } 2086 2087 static DEVICE_ATTR_RW(queue_len); 2088 static DEVICE_ATTR_RW(fallback); 2089 2090 static struct attribute *omap_sham_attrs[] = { 2091 &dev_attr_queue_len.attr, 2092 &dev_attr_fallback.attr, 2093 NULL, 2094 }; 2095 2096 static struct attribute_group omap_sham_attr_group = { 2097 .attrs = omap_sham_attrs, 2098 }; 2099 2100 static int omap_sham_probe(struct platform_device *pdev) 2101 { 2102 struct omap_sham_dev *dd; 2103 struct device *dev = &pdev->dev; 2104 struct resource res; 2105 dma_cap_mask_t mask; 2106 int err, i, j; 2107 u32 rev; 2108 2109 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 2110 if (dd == NULL) { 2111 dev_err(dev, "unable to alloc data struct.\n"); 2112 err = -ENOMEM; 2113 goto data_err; 2114 } 2115 dd->dev = dev; 2116 platform_set_drvdata(pdev, dd); 2117 2118 INIT_LIST_HEAD(&dd->list); 2119 spin_lock_init(&dd->lock); 2120 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 2121 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 2122 2123 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 2124 omap_sham_get_res_pdev(dd, pdev, &res); 2125 if (err) 2126 goto data_err; 2127 2128 dd->io_base = devm_ioremap_resource(dev, &res); 2129 if (IS_ERR(dd->io_base)) { 2130 err = PTR_ERR(dd->io_base); 2131 goto data_err; 2132 } 2133 dd->phys_base = res.start; 2134 2135 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 2136 IRQF_TRIGGER_NONE, dev_name(dev), dd); 2137 if (err) { 2138 dev_err(dev, "unable to request irq %d, err = %d\n", 2139 dd->irq, err); 2140 goto data_err; 2141 } 2142 2143 dma_cap_zero(mask); 2144 dma_cap_set(DMA_SLAVE, mask); 2145 2146 dd->dma_lch = dma_request_chan(dev, "rx"); 2147 if (IS_ERR(dd->dma_lch)) { 2148 err = PTR_ERR(dd->dma_lch); 2149 if (err == -EPROBE_DEFER) 2150 goto data_err; 2151 2152 dd->polling_mode = 1; 2153 dev_dbg(dev, "using polling mode instead of dma\n"); 2154 } 2155 2156 dd->flags |= dd->pdata->flags; 2157 2158 pm_runtime_use_autosuspend(dev); 2159 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 2160 2161 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; 2162 2163 pm_runtime_enable(dev); 2164 pm_runtime_irq_safe(dev); 2165 2166 err = pm_runtime_get_sync(dev); 2167 if (err < 0) { 2168 dev_err(dev, "failed to get sync: %d\n", err); 2169 goto err_pm; 2170 } 2171 2172 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 2173 pm_runtime_put_sync(&pdev->dev); 2174 2175 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 2176 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 2177 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 2178 2179 spin_lock(&sham.lock); 2180 list_add_tail(&dd->list, &sham.dev_list); 2181 spin_unlock(&sham.lock); 2182 2183 for (i = 0; i < dd->pdata->algs_info_size; i++) { 2184 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2185 struct ahash_alg *alg; 2186 2187 alg = &dd->pdata->algs_info[i].algs_list[j]; 2188 alg->export = omap_sham_export; 2189 alg->import = omap_sham_import; 2190 alg->halg.statesize = sizeof(struct omap_sham_reqctx) + 2191 BUFLEN; 2192 err = crypto_register_ahash(alg); 2193 if (err) 2194 goto err_algs; 2195 2196 dd->pdata->algs_info[i].registered++; 2197 } 2198 } 2199 2200 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); 2201 if (err) { 2202 dev_err(dev, "could not create sysfs device attrs\n"); 2203 goto err_algs; 2204 } 2205 2206 return 0; 2207 2208 err_algs: 2209 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2210 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2211 crypto_unregister_ahash( 2212 &dd->pdata->algs_info[i].algs_list[j]); 2213 err_pm: 2214 pm_runtime_disable(dev); 2215 if (!dd->polling_mode) 2216 dma_release_channel(dd->dma_lch); 2217 data_err: 2218 dev_err(dev, "initialization failed.\n"); 2219 2220 return err; 2221 } 2222 2223 static int omap_sham_remove(struct platform_device *pdev) 2224 { 2225 struct omap_sham_dev *dd; 2226 int i, j; 2227 2228 dd = platform_get_drvdata(pdev); 2229 if (!dd) 2230 return -ENODEV; 2231 spin_lock(&sham.lock); 2232 list_del(&dd->list); 2233 spin_unlock(&sham.lock); 2234 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2235 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2236 crypto_unregister_ahash( 2237 &dd->pdata->algs_info[i].algs_list[j]); 2238 tasklet_kill(&dd->done_task); 2239 pm_runtime_disable(&pdev->dev); 2240 2241 if (!dd->polling_mode) 2242 dma_release_channel(dd->dma_lch); 2243 2244 sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group); 2245 2246 return 0; 2247 } 2248 2249 #ifdef CONFIG_PM_SLEEP 2250 static int omap_sham_suspend(struct device *dev) 2251 { 2252 pm_runtime_put_sync(dev); 2253 return 0; 2254 } 2255 2256 static int omap_sham_resume(struct device *dev) 2257 { 2258 int err = pm_runtime_get_sync(dev); 2259 if (err < 0) { 2260 dev_err(dev, "failed to get sync: %d\n", err); 2261 return err; 2262 } 2263 return 0; 2264 } 2265 #endif 2266 2267 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2268 2269 static struct platform_driver omap_sham_driver = { 2270 .probe = omap_sham_probe, 2271 .remove = omap_sham_remove, 2272 .driver = { 2273 .name = "omap-sham", 2274 .pm = &omap_sham_pm_ops, 2275 .of_match_table = omap_sham_of_match, 2276 }, 2277 }; 2278 2279 module_platform_driver(omap_sham_driver); 2280 2281 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2282 MODULE_LICENSE("GPL v2"); 2283 MODULE_AUTHOR("Dmitry Kasatkin"); 2284 MODULE_ALIAS("platform:omap-sham"); 2285