1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP SHA1/MD5 HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 * 11 * Some ideas are from old omap-sha1-md5.c driver. 12 */ 13 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 16 #include <linux/err.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/irq.h> 24 #include <linux/io.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/of_irq.h> 34 #include <linux/delay.h> 35 #include <linux/crypto.h> 36 #include <linux/cryptohash.h> 37 #include <crypto/scatterwalk.h> 38 #include <crypto/algapi.h> 39 #include <crypto/sha.h> 40 #include <crypto/hash.h> 41 #include <crypto/hmac.h> 42 #include <crypto/internal/hash.h> 43 44 #define MD5_DIGEST_SIZE 16 45 46 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 47 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 48 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 49 50 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 51 52 #define SHA_REG_CTRL 0x18 53 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 54 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 55 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 56 #define SHA_REG_CTRL_ALGO (1 << 2) 57 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 58 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 59 60 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 61 62 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 63 #define SHA_REG_MASK_DMA_EN (1 << 3) 64 #define SHA_REG_MASK_IT_EN (1 << 2) 65 #define SHA_REG_MASK_SOFTRESET (1 << 1) 66 #define SHA_REG_AUTOIDLE (1 << 0) 67 68 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 69 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 70 71 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 72 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 73 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 74 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 75 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 76 77 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 78 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 79 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 80 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 81 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 82 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 83 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 84 85 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 86 87 #define SHA_REG_IRQSTATUS 0x118 88 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 90 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 92 93 #define SHA_REG_IRQENA 0x11C 94 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 95 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 96 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 97 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 98 99 #define DEFAULT_TIMEOUT_INTERVAL HZ 100 101 #define DEFAULT_AUTOSUSPEND_DELAY 1000 102 103 /* mostly device flags */ 104 #define FLAGS_BUSY 0 105 #define FLAGS_FINAL 1 106 #define FLAGS_DMA_ACTIVE 2 107 #define FLAGS_OUTPUT_READY 3 108 #define FLAGS_INIT 4 109 #define FLAGS_CPU 5 110 #define FLAGS_DMA_READY 6 111 #define FLAGS_AUTO_XOR 7 112 #define FLAGS_BE32_SHA1 8 113 #define FLAGS_SGS_COPIED 9 114 #define FLAGS_SGS_ALLOCED 10 115 /* context flags */ 116 #define FLAGS_FINUP 16 117 118 #define FLAGS_MODE_SHIFT 18 119 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 120 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 126 127 #define FLAGS_HMAC 21 128 #define FLAGS_ERROR 22 129 130 #define OP_UPDATE 1 131 #define OP_FINAL 2 132 133 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 134 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 135 136 #define BUFLEN SHA512_BLOCK_SIZE 137 #define OMAP_SHA_DMA_THRESHOLD 256 138 139 struct omap_sham_dev; 140 141 struct omap_sham_reqctx { 142 struct omap_sham_dev *dd; 143 unsigned long flags; 144 unsigned long op; 145 146 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 147 size_t digcnt; 148 size_t bufcnt; 149 size_t buflen; 150 151 /* walk state */ 152 struct scatterlist *sg; 153 struct scatterlist sgl[2]; 154 int offset; /* offset in current sg */ 155 int sg_len; 156 unsigned int total; /* total request */ 157 158 u8 buffer[0] OMAP_ALIGNED; 159 }; 160 161 struct omap_sham_hmac_ctx { 162 struct crypto_shash *shash; 163 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 164 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 165 }; 166 167 struct omap_sham_ctx { 168 struct omap_sham_dev *dd; 169 170 unsigned long flags; 171 172 /* fallback stuff */ 173 struct crypto_shash *fallback; 174 175 struct omap_sham_hmac_ctx base[0]; 176 }; 177 178 #define OMAP_SHAM_QUEUE_LENGTH 10 179 180 struct omap_sham_algs_info { 181 struct ahash_alg *algs_list; 182 unsigned int size; 183 unsigned int registered; 184 }; 185 186 struct omap_sham_pdata { 187 struct omap_sham_algs_info *algs_info; 188 unsigned int algs_info_size; 189 unsigned long flags; 190 int digest_size; 191 192 void (*copy_hash)(struct ahash_request *req, int out); 193 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 194 int final, int dma); 195 void (*trigger)(struct omap_sham_dev *dd, size_t length); 196 int (*poll_irq)(struct omap_sham_dev *dd); 197 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 198 199 u32 odigest_ofs; 200 u32 idigest_ofs; 201 u32 din_ofs; 202 u32 digcnt_ofs; 203 u32 rev_ofs; 204 u32 mask_ofs; 205 u32 sysstatus_ofs; 206 u32 mode_ofs; 207 u32 length_ofs; 208 209 u32 major_mask; 210 u32 major_shift; 211 u32 minor_mask; 212 u32 minor_shift; 213 }; 214 215 struct omap_sham_dev { 216 struct list_head list; 217 unsigned long phys_base; 218 struct device *dev; 219 void __iomem *io_base; 220 int irq; 221 spinlock_t lock; 222 int err; 223 struct dma_chan *dma_lch; 224 struct tasklet_struct done_task; 225 u8 polling_mode; 226 u8 xmit_buf[BUFLEN] OMAP_ALIGNED; 227 228 unsigned long flags; 229 int fallback_sz; 230 struct crypto_queue queue; 231 struct ahash_request *req; 232 233 const struct omap_sham_pdata *pdata; 234 }; 235 236 struct omap_sham_drv { 237 struct list_head dev_list; 238 spinlock_t lock; 239 unsigned long flags; 240 }; 241 242 static struct omap_sham_drv sham = { 243 .dev_list = LIST_HEAD_INIT(sham.dev_list), 244 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 245 }; 246 247 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 248 { 249 return __raw_readl(dd->io_base + offset); 250 } 251 252 static inline void omap_sham_write(struct omap_sham_dev *dd, 253 u32 offset, u32 value) 254 { 255 __raw_writel(value, dd->io_base + offset); 256 } 257 258 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 259 u32 value, u32 mask) 260 { 261 u32 val; 262 263 val = omap_sham_read(dd, address); 264 val &= ~mask; 265 val |= value; 266 omap_sham_write(dd, address, val); 267 } 268 269 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 270 { 271 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 272 273 while (!(omap_sham_read(dd, offset) & bit)) { 274 if (time_is_before_jiffies(timeout)) 275 return -ETIMEDOUT; 276 } 277 278 return 0; 279 } 280 281 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 282 { 283 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 284 struct omap_sham_dev *dd = ctx->dd; 285 u32 *hash = (u32 *)ctx->digest; 286 int i; 287 288 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 289 if (out) 290 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 291 else 292 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 293 } 294 } 295 296 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 297 { 298 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 299 struct omap_sham_dev *dd = ctx->dd; 300 int i; 301 302 if (ctx->flags & BIT(FLAGS_HMAC)) { 303 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 304 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 305 struct omap_sham_hmac_ctx *bctx = tctx->base; 306 u32 *opad = (u32 *)bctx->opad; 307 308 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 309 if (out) 310 opad[i] = omap_sham_read(dd, 311 SHA_REG_ODIGEST(dd, i)); 312 else 313 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 314 opad[i]); 315 } 316 } 317 318 omap_sham_copy_hash_omap2(req, out); 319 } 320 321 static void omap_sham_copy_ready_hash(struct ahash_request *req) 322 { 323 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 324 u32 *in = (u32 *)ctx->digest; 325 u32 *hash = (u32 *)req->result; 326 int i, d, big_endian = 0; 327 328 if (!hash) 329 return; 330 331 switch (ctx->flags & FLAGS_MODE_MASK) { 332 case FLAGS_MODE_MD5: 333 d = MD5_DIGEST_SIZE / sizeof(u32); 334 break; 335 case FLAGS_MODE_SHA1: 336 /* OMAP2 SHA1 is big endian */ 337 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 338 big_endian = 1; 339 d = SHA1_DIGEST_SIZE / sizeof(u32); 340 break; 341 case FLAGS_MODE_SHA224: 342 d = SHA224_DIGEST_SIZE / sizeof(u32); 343 break; 344 case FLAGS_MODE_SHA256: 345 d = SHA256_DIGEST_SIZE / sizeof(u32); 346 break; 347 case FLAGS_MODE_SHA384: 348 d = SHA384_DIGEST_SIZE / sizeof(u32); 349 break; 350 case FLAGS_MODE_SHA512: 351 d = SHA512_DIGEST_SIZE / sizeof(u32); 352 break; 353 default: 354 d = 0; 355 } 356 357 if (big_endian) 358 for (i = 0; i < d; i++) 359 hash[i] = be32_to_cpu(in[i]); 360 else 361 for (i = 0; i < d; i++) 362 hash[i] = le32_to_cpu(in[i]); 363 } 364 365 static int omap_sham_hw_init(struct omap_sham_dev *dd) 366 { 367 int err; 368 369 err = pm_runtime_get_sync(dd->dev); 370 if (err < 0) { 371 dev_err(dd->dev, "failed to get sync: %d\n", err); 372 return err; 373 } 374 375 if (!test_bit(FLAGS_INIT, &dd->flags)) { 376 set_bit(FLAGS_INIT, &dd->flags); 377 dd->err = 0; 378 } 379 380 return 0; 381 } 382 383 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 384 int final, int dma) 385 { 386 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 387 u32 val = length << 5, mask; 388 389 if (likely(ctx->digcnt)) 390 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 391 392 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 393 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 394 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 395 /* 396 * Setting ALGO_CONST only for the first iteration 397 * and CLOSE_HASH only for the last one. 398 */ 399 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 400 val |= SHA_REG_CTRL_ALGO; 401 if (!ctx->digcnt) 402 val |= SHA_REG_CTRL_ALGO_CONST; 403 if (final) 404 val |= SHA_REG_CTRL_CLOSE_HASH; 405 406 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 407 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 408 409 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 410 } 411 412 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 413 { 414 } 415 416 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 417 { 418 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 419 } 420 421 static int get_block_size(struct omap_sham_reqctx *ctx) 422 { 423 int d; 424 425 switch (ctx->flags & FLAGS_MODE_MASK) { 426 case FLAGS_MODE_MD5: 427 case FLAGS_MODE_SHA1: 428 d = SHA1_BLOCK_SIZE; 429 break; 430 case FLAGS_MODE_SHA224: 431 case FLAGS_MODE_SHA256: 432 d = SHA256_BLOCK_SIZE; 433 break; 434 case FLAGS_MODE_SHA384: 435 case FLAGS_MODE_SHA512: 436 d = SHA512_BLOCK_SIZE; 437 break; 438 default: 439 d = 0; 440 } 441 442 return d; 443 } 444 445 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 446 u32 *value, int count) 447 { 448 for (; count--; value++, offset += 4) 449 omap_sham_write(dd, offset, *value); 450 } 451 452 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 453 int final, int dma) 454 { 455 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 456 u32 val, mask; 457 458 /* 459 * Setting ALGO_CONST only for the first iteration and 460 * CLOSE_HASH only for the last one. Note that flags mode bits 461 * correspond to algorithm encoding in mode register. 462 */ 463 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 464 if (!ctx->digcnt) { 465 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 466 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 467 struct omap_sham_hmac_ctx *bctx = tctx->base; 468 int bs, nr_dr; 469 470 val |= SHA_REG_MODE_ALGO_CONSTANT; 471 472 if (ctx->flags & BIT(FLAGS_HMAC)) { 473 bs = get_block_size(ctx); 474 nr_dr = bs / (2 * sizeof(u32)); 475 val |= SHA_REG_MODE_HMAC_KEY_PROC; 476 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 477 (u32 *)bctx->ipad, nr_dr); 478 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 479 (u32 *)bctx->ipad + nr_dr, nr_dr); 480 ctx->digcnt += bs; 481 } 482 } 483 484 if (final) { 485 val |= SHA_REG_MODE_CLOSE_HASH; 486 487 if (ctx->flags & BIT(FLAGS_HMAC)) 488 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 489 } 490 491 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 492 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 493 SHA_REG_MODE_HMAC_KEY_PROC; 494 495 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 496 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 497 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 498 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 499 SHA_REG_MASK_IT_EN | 500 (dma ? SHA_REG_MASK_DMA_EN : 0), 501 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 502 } 503 504 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 505 { 506 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 507 } 508 509 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 510 { 511 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 512 SHA_REG_IRQSTATUS_INPUT_RDY); 513 } 514 515 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, 516 int final) 517 { 518 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 519 int count, len32, bs32, offset = 0; 520 const u32 *buffer; 521 int mlen; 522 struct sg_mapping_iter mi; 523 524 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 525 ctx->digcnt, length, final); 526 527 dd->pdata->write_ctrl(dd, length, final, 0); 528 dd->pdata->trigger(dd, length); 529 530 /* should be non-zero before next lines to disable clocks later */ 531 ctx->digcnt += length; 532 ctx->total -= length; 533 534 if (final) 535 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 536 537 set_bit(FLAGS_CPU, &dd->flags); 538 539 len32 = DIV_ROUND_UP(length, sizeof(u32)); 540 bs32 = get_block_size(ctx) / sizeof(u32); 541 542 sg_miter_start(&mi, ctx->sg, ctx->sg_len, 543 SG_MITER_FROM_SG | SG_MITER_ATOMIC); 544 545 mlen = 0; 546 547 while (len32) { 548 if (dd->pdata->poll_irq(dd)) 549 return -ETIMEDOUT; 550 551 for (count = 0; count < min(len32, bs32); count++, offset++) { 552 if (!mlen) { 553 sg_miter_next(&mi); 554 mlen = mi.length; 555 if (!mlen) { 556 pr_err("sg miter failure.\n"); 557 return -EINVAL; 558 } 559 offset = 0; 560 buffer = mi.addr; 561 } 562 omap_sham_write(dd, SHA_REG_DIN(dd, count), 563 buffer[offset]); 564 mlen -= 4; 565 } 566 len32 -= min(len32, bs32); 567 } 568 569 sg_miter_stop(&mi); 570 571 return -EINPROGRESS; 572 } 573 574 static void omap_sham_dma_callback(void *param) 575 { 576 struct omap_sham_dev *dd = param; 577 578 set_bit(FLAGS_DMA_READY, &dd->flags); 579 tasklet_schedule(&dd->done_task); 580 } 581 582 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, 583 int final) 584 { 585 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 586 struct dma_async_tx_descriptor *tx; 587 struct dma_slave_config cfg; 588 int ret; 589 590 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 591 ctx->digcnt, length, final); 592 593 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { 594 dev_err(dd->dev, "dma_map_sg error\n"); 595 return -EINVAL; 596 } 597 598 memset(&cfg, 0, sizeof(cfg)); 599 600 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 601 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 602 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; 603 604 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 605 if (ret) { 606 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 607 return ret; 608 } 609 610 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, 611 DMA_MEM_TO_DEV, 612 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 613 614 if (!tx) { 615 dev_err(dd->dev, "prep_slave_sg failed\n"); 616 return -EINVAL; 617 } 618 619 tx->callback = omap_sham_dma_callback; 620 tx->callback_param = dd; 621 622 dd->pdata->write_ctrl(dd, length, final, 1); 623 624 ctx->digcnt += length; 625 ctx->total -= length; 626 627 if (final) 628 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 629 630 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 631 632 dmaengine_submit(tx); 633 dma_async_issue_pending(dd->dma_lch); 634 635 dd->pdata->trigger(dd, length); 636 637 return -EINPROGRESS; 638 } 639 640 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, 641 struct scatterlist *sg, int bs, int new_len) 642 { 643 int n = sg_nents(sg); 644 struct scatterlist *tmp; 645 int offset = ctx->offset; 646 647 if (ctx->bufcnt) 648 n++; 649 650 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 651 if (!ctx->sg) 652 return -ENOMEM; 653 654 sg_init_table(ctx->sg, n); 655 656 tmp = ctx->sg; 657 658 ctx->sg_len = 0; 659 660 if (ctx->bufcnt) { 661 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 662 tmp = sg_next(tmp); 663 ctx->sg_len++; 664 } 665 666 while (sg && new_len) { 667 int len = sg->length - offset; 668 669 if (offset) { 670 offset -= sg->length; 671 if (offset < 0) 672 offset = 0; 673 } 674 675 if (new_len < len) 676 len = new_len; 677 678 if (len > 0) { 679 new_len -= len; 680 sg_set_page(tmp, sg_page(sg), len, sg->offset); 681 if (new_len <= 0) 682 sg_mark_end(tmp); 683 tmp = sg_next(tmp); 684 ctx->sg_len++; 685 } 686 687 sg = sg_next(sg); 688 } 689 690 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); 691 692 ctx->bufcnt = 0; 693 694 return 0; 695 } 696 697 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, 698 struct scatterlist *sg, int bs, int new_len) 699 { 700 int pages; 701 void *buf; 702 int len; 703 704 len = new_len + ctx->bufcnt; 705 706 pages = get_order(ctx->total); 707 708 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 709 if (!buf) { 710 pr_err("Couldn't allocate pages for unaligned cases.\n"); 711 return -ENOMEM; 712 } 713 714 if (ctx->bufcnt) 715 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 716 717 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, 718 ctx->total - ctx->bufcnt, 0); 719 sg_init_table(ctx->sgl, 1); 720 sg_set_buf(ctx->sgl, buf, len); 721 ctx->sg = ctx->sgl; 722 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); 723 ctx->sg_len = 1; 724 ctx->bufcnt = 0; 725 ctx->offset = 0; 726 727 return 0; 728 } 729 730 static int omap_sham_align_sgs(struct scatterlist *sg, 731 int nbytes, int bs, bool final, 732 struct omap_sham_reqctx *rctx) 733 { 734 int n = 0; 735 bool aligned = true; 736 bool list_ok = true; 737 struct scatterlist *sg_tmp = sg; 738 int new_len; 739 int offset = rctx->offset; 740 741 if (!sg || !sg->length || !nbytes) 742 return 0; 743 744 new_len = nbytes; 745 746 if (offset) 747 list_ok = false; 748 749 if (final) 750 new_len = DIV_ROUND_UP(new_len, bs) * bs; 751 else 752 new_len = (new_len - 1) / bs * bs; 753 754 if (nbytes != new_len) 755 list_ok = false; 756 757 while (nbytes > 0 && sg_tmp) { 758 n++; 759 760 #ifdef CONFIG_ZONE_DMA 761 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { 762 aligned = false; 763 break; 764 } 765 #endif 766 767 if (offset < sg_tmp->length) { 768 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { 769 aligned = false; 770 break; 771 } 772 773 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { 774 aligned = false; 775 break; 776 } 777 } 778 779 if (offset) { 780 offset -= sg_tmp->length; 781 if (offset < 0) { 782 nbytes += offset; 783 offset = 0; 784 } 785 } else { 786 nbytes -= sg_tmp->length; 787 } 788 789 sg_tmp = sg_next(sg_tmp); 790 791 if (nbytes < 0) { 792 list_ok = false; 793 break; 794 } 795 } 796 797 if (!aligned) 798 return omap_sham_copy_sgs(rctx, sg, bs, new_len); 799 else if (!list_ok) 800 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); 801 802 rctx->sg_len = n; 803 rctx->sg = sg; 804 805 return 0; 806 } 807 808 static int omap_sham_prepare_request(struct ahash_request *req, bool update) 809 { 810 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 811 int bs; 812 int ret; 813 int nbytes; 814 bool final = rctx->flags & BIT(FLAGS_FINUP); 815 int xmit_len, hash_later; 816 817 bs = get_block_size(rctx); 818 819 if (update) 820 nbytes = req->nbytes; 821 else 822 nbytes = 0; 823 824 rctx->total = nbytes + rctx->bufcnt; 825 826 if (!rctx->total) 827 return 0; 828 829 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { 830 int len = bs - rctx->bufcnt % bs; 831 832 if (len > nbytes) 833 len = nbytes; 834 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, 835 0, len, 0); 836 rctx->bufcnt += len; 837 nbytes -= len; 838 rctx->offset = len; 839 } 840 841 if (rctx->bufcnt) 842 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); 843 844 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); 845 if (ret) 846 return ret; 847 848 xmit_len = rctx->total; 849 850 if (!IS_ALIGNED(xmit_len, bs)) { 851 if (final) 852 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs; 853 else 854 xmit_len = xmit_len / bs * bs; 855 } else if (!final) { 856 xmit_len -= bs; 857 } 858 859 hash_later = rctx->total - xmit_len; 860 if (hash_later < 0) 861 hash_later = 0; 862 863 if (rctx->bufcnt && nbytes) { 864 /* have data from previous operation and current */ 865 sg_init_table(rctx->sgl, 2); 866 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); 867 868 sg_chain(rctx->sgl, 2, req->src); 869 870 rctx->sg = rctx->sgl; 871 872 rctx->sg_len++; 873 } else if (rctx->bufcnt) { 874 /* have buffered data only */ 875 sg_init_table(rctx->sgl, 1); 876 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len); 877 878 rctx->sg = rctx->sgl; 879 880 rctx->sg_len = 1; 881 } 882 883 if (hash_later) { 884 int offset = 0; 885 886 if (hash_later > req->nbytes) { 887 memcpy(rctx->buffer, rctx->buffer + xmit_len, 888 hash_later - req->nbytes); 889 offset = hash_later - req->nbytes; 890 } 891 892 if (req->nbytes) { 893 scatterwalk_map_and_copy(rctx->buffer + offset, 894 req->src, 895 offset + req->nbytes - 896 hash_later, hash_later, 0); 897 } 898 899 rctx->bufcnt = hash_later; 900 } else { 901 rctx->bufcnt = 0; 902 } 903 904 if (!final) 905 rctx->total = xmit_len; 906 907 return 0; 908 } 909 910 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 911 { 912 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 913 914 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 915 916 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); 917 918 return 0; 919 } 920 921 static int omap_sham_init(struct ahash_request *req) 922 { 923 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 924 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 925 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 926 struct omap_sham_dev *dd = NULL, *tmp; 927 int bs = 0; 928 929 spin_lock_bh(&sham.lock); 930 if (!tctx->dd) { 931 list_for_each_entry(tmp, &sham.dev_list, list) { 932 dd = tmp; 933 break; 934 } 935 tctx->dd = dd; 936 } else { 937 dd = tctx->dd; 938 } 939 spin_unlock_bh(&sham.lock); 940 941 ctx->dd = dd; 942 943 ctx->flags = 0; 944 945 dev_dbg(dd->dev, "init: digest size: %d\n", 946 crypto_ahash_digestsize(tfm)); 947 948 switch (crypto_ahash_digestsize(tfm)) { 949 case MD5_DIGEST_SIZE: 950 ctx->flags |= FLAGS_MODE_MD5; 951 bs = SHA1_BLOCK_SIZE; 952 break; 953 case SHA1_DIGEST_SIZE: 954 ctx->flags |= FLAGS_MODE_SHA1; 955 bs = SHA1_BLOCK_SIZE; 956 break; 957 case SHA224_DIGEST_SIZE: 958 ctx->flags |= FLAGS_MODE_SHA224; 959 bs = SHA224_BLOCK_SIZE; 960 break; 961 case SHA256_DIGEST_SIZE: 962 ctx->flags |= FLAGS_MODE_SHA256; 963 bs = SHA256_BLOCK_SIZE; 964 break; 965 case SHA384_DIGEST_SIZE: 966 ctx->flags |= FLAGS_MODE_SHA384; 967 bs = SHA384_BLOCK_SIZE; 968 break; 969 case SHA512_DIGEST_SIZE: 970 ctx->flags |= FLAGS_MODE_SHA512; 971 bs = SHA512_BLOCK_SIZE; 972 break; 973 } 974 975 ctx->bufcnt = 0; 976 ctx->digcnt = 0; 977 ctx->total = 0; 978 ctx->offset = 0; 979 ctx->buflen = BUFLEN; 980 981 if (tctx->flags & BIT(FLAGS_HMAC)) { 982 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 983 struct omap_sham_hmac_ctx *bctx = tctx->base; 984 985 memcpy(ctx->buffer, bctx->ipad, bs); 986 ctx->bufcnt = bs; 987 } 988 989 ctx->flags |= BIT(FLAGS_HMAC); 990 } 991 992 return 0; 993 994 } 995 996 static int omap_sham_update_req(struct omap_sham_dev *dd) 997 { 998 struct ahash_request *req = dd->req; 999 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1000 int err; 1001 bool final = ctx->flags & BIT(FLAGS_FINUP); 1002 1003 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", 1004 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); 1005 1006 if (ctx->total < get_block_size(ctx) || 1007 ctx->total < dd->fallback_sz) 1008 ctx->flags |= BIT(FLAGS_CPU); 1009 1010 if (ctx->flags & BIT(FLAGS_CPU)) 1011 err = omap_sham_xmit_cpu(dd, ctx->total, final); 1012 else 1013 err = omap_sham_xmit_dma(dd, ctx->total, final); 1014 1015 /* wait for dma completion before can take more data */ 1016 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 1017 1018 return err; 1019 } 1020 1021 static int omap_sham_final_req(struct omap_sham_dev *dd) 1022 { 1023 struct ahash_request *req = dd->req; 1024 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1025 int err = 0, use_dma = 1; 1026 1027 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) 1028 /* 1029 * faster to handle last block with cpu or 1030 * use cpu when dma is not present. 1031 */ 1032 use_dma = 0; 1033 1034 if (use_dma) 1035 err = omap_sham_xmit_dma(dd, ctx->total, 1); 1036 else 1037 err = omap_sham_xmit_cpu(dd, ctx->total, 1); 1038 1039 ctx->bufcnt = 0; 1040 1041 dev_dbg(dd->dev, "final_req: err: %d\n", err); 1042 1043 return err; 1044 } 1045 1046 static int omap_sham_finish_hmac(struct ahash_request *req) 1047 { 1048 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1049 struct omap_sham_hmac_ctx *bctx = tctx->base; 1050 int bs = crypto_shash_blocksize(bctx->shash); 1051 int ds = crypto_shash_digestsize(bctx->shash); 1052 SHASH_DESC_ON_STACK(shash, bctx->shash); 1053 1054 shash->tfm = bctx->shash; 1055 1056 return crypto_shash_init(shash) ?: 1057 crypto_shash_update(shash, bctx->opad, bs) ?: 1058 crypto_shash_finup(shash, req->result, ds, req->result); 1059 } 1060 1061 static int omap_sham_finish(struct ahash_request *req) 1062 { 1063 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1064 struct omap_sham_dev *dd = ctx->dd; 1065 int err = 0; 1066 1067 if (ctx->digcnt) { 1068 omap_sham_copy_ready_hash(req); 1069 if ((ctx->flags & BIT(FLAGS_HMAC)) && 1070 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 1071 err = omap_sham_finish_hmac(req); 1072 } 1073 1074 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 1075 1076 return err; 1077 } 1078 1079 static void omap_sham_finish_req(struct ahash_request *req, int err) 1080 { 1081 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1082 struct omap_sham_dev *dd = ctx->dd; 1083 1084 if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) 1085 free_pages((unsigned long)sg_virt(ctx->sg), 1086 get_order(ctx->sg->length + ctx->bufcnt)); 1087 1088 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) 1089 kfree(ctx->sg); 1090 1091 ctx->sg = NULL; 1092 1093 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); 1094 1095 if (!err) { 1096 dd->pdata->copy_hash(req, 1); 1097 if (test_bit(FLAGS_FINAL, &dd->flags)) 1098 err = omap_sham_finish(req); 1099 } else { 1100 ctx->flags |= BIT(FLAGS_ERROR); 1101 } 1102 1103 /* atomic operation is not needed here */ 1104 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1105 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1106 1107 pm_runtime_mark_last_busy(dd->dev); 1108 pm_runtime_put_autosuspend(dd->dev); 1109 1110 if (req->base.complete) 1111 req->base.complete(&req->base, err); 1112 } 1113 1114 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1115 struct ahash_request *req) 1116 { 1117 struct crypto_async_request *async_req, *backlog; 1118 struct omap_sham_reqctx *ctx; 1119 unsigned long flags; 1120 int err = 0, ret = 0; 1121 1122 retry: 1123 spin_lock_irqsave(&dd->lock, flags); 1124 if (req) 1125 ret = ahash_enqueue_request(&dd->queue, req); 1126 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1127 spin_unlock_irqrestore(&dd->lock, flags); 1128 return ret; 1129 } 1130 backlog = crypto_get_backlog(&dd->queue); 1131 async_req = crypto_dequeue_request(&dd->queue); 1132 if (async_req) 1133 set_bit(FLAGS_BUSY, &dd->flags); 1134 spin_unlock_irqrestore(&dd->lock, flags); 1135 1136 if (!async_req) 1137 return ret; 1138 1139 if (backlog) 1140 backlog->complete(backlog, -EINPROGRESS); 1141 1142 req = ahash_request_cast(async_req); 1143 dd->req = req; 1144 ctx = ahash_request_ctx(req); 1145 1146 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1147 if (err || !ctx->total) 1148 goto err1; 1149 1150 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1151 ctx->op, req->nbytes); 1152 1153 err = omap_sham_hw_init(dd); 1154 if (err) 1155 goto err1; 1156 1157 if (ctx->digcnt) 1158 /* request has changed - restore hash */ 1159 dd->pdata->copy_hash(req, 0); 1160 1161 if (ctx->op == OP_UPDATE) { 1162 err = omap_sham_update_req(dd); 1163 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1164 /* no final() after finup() */ 1165 err = omap_sham_final_req(dd); 1166 } else if (ctx->op == OP_FINAL) { 1167 err = omap_sham_final_req(dd); 1168 } 1169 err1: 1170 dev_dbg(dd->dev, "exit, err: %d\n", err); 1171 1172 if (err != -EINPROGRESS) { 1173 /* done_task will not finish it, so do it here */ 1174 omap_sham_finish_req(req, err); 1175 req = NULL; 1176 1177 /* 1178 * Execute next request immediately if there is anything 1179 * in queue. 1180 */ 1181 goto retry; 1182 } 1183 1184 return ret; 1185 } 1186 1187 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1188 { 1189 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1190 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1191 struct omap_sham_dev *dd = tctx->dd; 1192 1193 ctx->op = op; 1194 1195 return omap_sham_handle_queue(dd, req); 1196 } 1197 1198 static int omap_sham_update(struct ahash_request *req) 1199 { 1200 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1201 struct omap_sham_dev *dd = ctx->dd; 1202 1203 if (!req->nbytes) 1204 return 0; 1205 1206 if (ctx->bufcnt + req->nbytes <= ctx->buflen) { 1207 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1208 0, req->nbytes, 0); 1209 ctx->bufcnt += req->nbytes; 1210 return 0; 1211 } 1212 1213 if (dd->polling_mode) 1214 ctx->flags |= BIT(FLAGS_CPU); 1215 1216 return omap_sham_enqueue(req, OP_UPDATE); 1217 } 1218 1219 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags, 1220 const u8 *data, unsigned int len, u8 *out) 1221 { 1222 SHASH_DESC_ON_STACK(shash, tfm); 1223 1224 shash->tfm = tfm; 1225 1226 return crypto_shash_digest(shash, data, len, out); 1227 } 1228 1229 static int omap_sham_final_shash(struct ahash_request *req) 1230 { 1231 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1232 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1233 int offset = 0; 1234 1235 /* 1236 * If we are running HMAC on limited hardware support, skip 1237 * the ipad in the beginning of the buffer if we are going for 1238 * software fallback algorithm. 1239 */ 1240 if (test_bit(FLAGS_HMAC, &ctx->flags) && 1241 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) 1242 offset = get_block_size(ctx); 1243 1244 return omap_sham_shash_digest(tctx->fallback, req->base.flags, 1245 ctx->buffer + offset, 1246 ctx->bufcnt - offset, req->result); 1247 } 1248 1249 static int omap_sham_final(struct ahash_request *req) 1250 { 1251 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1252 1253 ctx->flags |= BIT(FLAGS_FINUP); 1254 1255 if (ctx->flags & BIT(FLAGS_ERROR)) 1256 return 0; /* uncompleted hash is not needed */ 1257 1258 /* 1259 * OMAP HW accel works only with buffers >= 9. 1260 * HMAC is always >= 9 because ipad == block size. 1261 * If buffersize is less than fallback_sz, we use fallback 1262 * SW encoding, as using DMA + HW in this case doesn't provide 1263 * any benefit. 1264 */ 1265 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) 1266 return omap_sham_final_shash(req); 1267 else if (ctx->bufcnt) 1268 return omap_sham_enqueue(req, OP_FINAL); 1269 1270 /* copy ready hash (+ finalize hmac) */ 1271 return omap_sham_finish(req); 1272 } 1273 1274 static int omap_sham_finup(struct ahash_request *req) 1275 { 1276 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1277 int err1, err2; 1278 1279 ctx->flags |= BIT(FLAGS_FINUP); 1280 1281 err1 = omap_sham_update(req); 1282 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1283 return err1; 1284 /* 1285 * final() has to be always called to cleanup resources 1286 * even if udpate() failed, except EINPROGRESS 1287 */ 1288 err2 = omap_sham_final(req); 1289 1290 return err1 ?: err2; 1291 } 1292 1293 static int omap_sham_digest(struct ahash_request *req) 1294 { 1295 return omap_sham_init(req) ?: omap_sham_finup(req); 1296 } 1297 1298 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1299 unsigned int keylen) 1300 { 1301 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1302 struct omap_sham_hmac_ctx *bctx = tctx->base; 1303 int bs = crypto_shash_blocksize(bctx->shash); 1304 int ds = crypto_shash_digestsize(bctx->shash); 1305 struct omap_sham_dev *dd = NULL, *tmp; 1306 int err, i; 1307 1308 spin_lock_bh(&sham.lock); 1309 if (!tctx->dd) { 1310 list_for_each_entry(tmp, &sham.dev_list, list) { 1311 dd = tmp; 1312 break; 1313 } 1314 tctx->dd = dd; 1315 } else { 1316 dd = tctx->dd; 1317 } 1318 spin_unlock_bh(&sham.lock); 1319 1320 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1321 if (err) 1322 return err; 1323 1324 if (keylen > bs) { 1325 err = omap_sham_shash_digest(bctx->shash, 1326 crypto_shash_get_flags(bctx->shash), 1327 key, keylen, bctx->ipad); 1328 if (err) 1329 return err; 1330 keylen = ds; 1331 } else { 1332 memcpy(bctx->ipad, key, keylen); 1333 } 1334 1335 memset(bctx->ipad + keylen, 0, bs - keylen); 1336 1337 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1338 memcpy(bctx->opad, bctx->ipad, bs); 1339 1340 for (i = 0; i < bs; i++) { 1341 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 1342 bctx->opad[i] ^= HMAC_OPAD_VALUE; 1343 } 1344 } 1345 1346 return err; 1347 } 1348 1349 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1350 { 1351 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1352 const char *alg_name = crypto_tfm_alg_name(tfm); 1353 1354 /* Allocate a fallback and abort if it failed. */ 1355 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1356 CRYPTO_ALG_NEED_FALLBACK); 1357 if (IS_ERR(tctx->fallback)) { 1358 pr_err("omap-sham: fallback driver '%s' " 1359 "could not be loaded.\n", alg_name); 1360 return PTR_ERR(tctx->fallback); 1361 } 1362 1363 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1364 sizeof(struct omap_sham_reqctx) + BUFLEN); 1365 1366 if (alg_base) { 1367 struct omap_sham_hmac_ctx *bctx = tctx->base; 1368 tctx->flags |= BIT(FLAGS_HMAC); 1369 bctx->shash = crypto_alloc_shash(alg_base, 0, 1370 CRYPTO_ALG_NEED_FALLBACK); 1371 if (IS_ERR(bctx->shash)) { 1372 pr_err("omap-sham: base driver '%s' " 1373 "could not be loaded.\n", alg_base); 1374 crypto_free_shash(tctx->fallback); 1375 return PTR_ERR(bctx->shash); 1376 } 1377 1378 } 1379 1380 return 0; 1381 } 1382 1383 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1384 { 1385 return omap_sham_cra_init_alg(tfm, NULL); 1386 } 1387 1388 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1389 { 1390 return omap_sham_cra_init_alg(tfm, "sha1"); 1391 } 1392 1393 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1394 { 1395 return omap_sham_cra_init_alg(tfm, "sha224"); 1396 } 1397 1398 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1399 { 1400 return omap_sham_cra_init_alg(tfm, "sha256"); 1401 } 1402 1403 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1404 { 1405 return omap_sham_cra_init_alg(tfm, "md5"); 1406 } 1407 1408 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1409 { 1410 return omap_sham_cra_init_alg(tfm, "sha384"); 1411 } 1412 1413 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1414 { 1415 return omap_sham_cra_init_alg(tfm, "sha512"); 1416 } 1417 1418 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1419 { 1420 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1421 1422 crypto_free_shash(tctx->fallback); 1423 tctx->fallback = NULL; 1424 1425 if (tctx->flags & BIT(FLAGS_HMAC)) { 1426 struct omap_sham_hmac_ctx *bctx = tctx->base; 1427 crypto_free_shash(bctx->shash); 1428 } 1429 } 1430 1431 static int omap_sham_export(struct ahash_request *req, void *out) 1432 { 1433 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1434 1435 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); 1436 1437 return 0; 1438 } 1439 1440 static int omap_sham_import(struct ahash_request *req, const void *in) 1441 { 1442 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1443 const struct omap_sham_reqctx *ctx_in = in; 1444 1445 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); 1446 1447 return 0; 1448 } 1449 1450 static struct ahash_alg algs_sha1_md5[] = { 1451 { 1452 .init = omap_sham_init, 1453 .update = omap_sham_update, 1454 .final = omap_sham_final, 1455 .finup = omap_sham_finup, 1456 .digest = omap_sham_digest, 1457 .halg.digestsize = SHA1_DIGEST_SIZE, 1458 .halg.base = { 1459 .cra_name = "sha1", 1460 .cra_driver_name = "omap-sha1", 1461 .cra_priority = 400, 1462 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1463 CRYPTO_ALG_ASYNC | 1464 CRYPTO_ALG_NEED_FALLBACK, 1465 .cra_blocksize = SHA1_BLOCK_SIZE, 1466 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1467 .cra_alignmask = OMAP_ALIGN_MASK, 1468 .cra_module = THIS_MODULE, 1469 .cra_init = omap_sham_cra_init, 1470 .cra_exit = omap_sham_cra_exit, 1471 } 1472 }, 1473 { 1474 .init = omap_sham_init, 1475 .update = omap_sham_update, 1476 .final = omap_sham_final, 1477 .finup = omap_sham_finup, 1478 .digest = omap_sham_digest, 1479 .halg.digestsize = MD5_DIGEST_SIZE, 1480 .halg.base = { 1481 .cra_name = "md5", 1482 .cra_driver_name = "omap-md5", 1483 .cra_priority = 400, 1484 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1485 CRYPTO_ALG_ASYNC | 1486 CRYPTO_ALG_NEED_FALLBACK, 1487 .cra_blocksize = SHA1_BLOCK_SIZE, 1488 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1489 .cra_alignmask = OMAP_ALIGN_MASK, 1490 .cra_module = THIS_MODULE, 1491 .cra_init = omap_sham_cra_init, 1492 .cra_exit = omap_sham_cra_exit, 1493 } 1494 }, 1495 { 1496 .init = omap_sham_init, 1497 .update = omap_sham_update, 1498 .final = omap_sham_final, 1499 .finup = omap_sham_finup, 1500 .digest = omap_sham_digest, 1501 .setkey = omap_sham_setkey, 1502 .halg.digestsize = SHA1_DIGEST_SIZE, 1503 .halg.base = { 1504 .cra_name = "hmac(sha1)", 1505 .cra_driver_name = "omap-hmac-sha1", 1506 .cra_priority = 400, 1507 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1508 CRYPTO_ALG_ASYNC | 1509 CRYPTO_ALG_NEED_FALLBACK, 1510 .cra_blocksize = SHA1_BLOCK_SIZE, 1511 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1512 sizeof(struct omap_sham_hmac_ctx), 1513 .cra_alignmask = OMAP_ALIGN_MASK, 1514 .cra_module = THIS_MODULE, 1515 .cra_init = omap_sham_cra_sha1_init, 1516 .cra_exit = omap_sham_cra_exit, 1517 } 1518 }, 1519 { 1520 .init = omap_sham_init, 1521 .update = omap_sham_update, 1522 .final = omap_sham_final, 1523 .finup = omap_sham_finup, 1524 .digest = omap_sham_digest, 1525 .setkey = omap_sham_setkey, 1526 .halg.digestsize = MD5_DIGEST_SIZE, 1527 .halg.base = { 1528 .cra_name = "hmac(md5)", 1529 .cra_driver_name = "omap-hmac-md5", 1530 .cra_priority = 400, 1531 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1532 CRYPTO_ALG_ASYNC | 1533 CRYPTO_ALG_NEED_FALLBACK, 1534 .cra_blocksize = SHA1_BLOCK_SIZE, 1535 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1536 sizeof(struct omap_sham_hmac_ctx), 1537 .cra_alignmask = OMAP_ALIGN_MASK, 1538 .cra_module = THIS_MODULE, 1539 .cra_init = omap_sham_cra_md5_init, 1540 .cra_exit = omap_sham_cra_exit, 1541 } 1542 } 1543 }; 1544 1545 /* OMAP4 has some algs in addition to what OMAP2 has */ 1546 static struct ahash_alg algs_sha224_sha256[] = { 1547 { 1548 .init = omap_sham_init, 1549 .update = omap_sham_update, 1550 .final = omap_sham_final, 1551 .finup = omap_sham_finup, 1552 .digest = omap_sham_digest, 1553 .halg.digestsize = SHA224_DIGEST_SIZE, 1554 .halg.base = { 1555 .cra_name = "sha224", 1556 .cra_driver_name = "omap-sha224", 1557 .cra_priority = 400, 1558 .cra_flags = CRYPTO_ALG_ASYNC | 1559 CRYPTO_ALG_NEED_FALLBACK, 1560 .cra_blocksize = SHA224_BLOCK_SIZE, 1561 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1562 .cra_alignmask = OMAP_ALIGN_MASK, 1563 .cra_module = THIS_MODULE, 1564 .cra_init = omap_sham_cra_init, 1565 .cra_exit = omap_sham_cra_exit, 1566 } 1567 }, 1568 { 1569 .init = omap_sham_init, 1570 .update = omap_sham_update, 1571 .final = omap_sham_final, 1572 .finup = omap_sham_finup, 1573 .digest = omap_sham_digest, 1574 .halg.digestsize = SHA256_DIGEST_SIZE, 1575 .halg.base = { 1576 .cra_name = "sha256", 1577 .cra_driver_name = "omap-sha256", 1578 .cra_priority = 400, 1579 .cra_flags = CRYPTO_ALG_ASYNC | 1580 CRYPTO_ALG_NEED_FALLBACK, 1581 .cra_blocksize = SHA256_BLOCK_SIZE, 1582 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1583 .cra_alignmask = OMAP_ALIGN_MASK, 1584 .cra_module = THIS_MODULE, 1585 .cra_init = omap_sham_cra_init, 1586 .cra_exit = omap_sham_cra_exit, 1587 } 1588 }, 1589 { 1590 .init = omap_sham_init, 1591 .update = omap_sham_update, 1592 .final = omap_sham_final, 1593 .finup = omap_sham_finup, 1594 .digest = omap_sham_digest, 1595 .setkey = omap_sham_setkey, 1596 .halg.digestsize = SHA224_DIGEST_SIZE, 1597 .halg.base = { 1598 .cra_name = "hmac(sha224)", 1599 .cra_driver_name = "omap-hmac-sha224", 1600 .cra_priority = 400, 1601 .cra_flags = CRYPTO_ALG_ASYNC | 1602 CRYPTO_ALG_NEED_FALLBACK, 1603 .cra_blocksize = SHA224_BLOCK_SIZE, 1604 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1605 sizeof(struct omap_sham_hmac_ctx), 1606 .cra_alignmask = OMAP_ALIGN_MASK, 1607 .cra_module = THIS_MODULE, 1608 .cra_init = omap_sham_cra_sha224_init, 1609 .cra_exit = omap_sham_cra_exit, 1610 } 1611 }, 1612 { 1613 .init = omap_sham_init, 1614 .update = omap_sham_update, 1615 .final = omap_sham_final, 1616 .finup = omap_sham_finup, 1617 .digest = omap_sham_digest, 1618 .setkey = omap_sham_setkey, 1619 .halg.digestsize = SHA256_DIGEST_SIZE, 1620 .halg.base = { 1621 .cra_name = "hmac(sha256)", 1622 .cra_driver_name = "omap-hmac-sha256", 1623 .cra_priority = 400, 1624 .cra_flags = CRYPTO_ALG_ASYNC | 1625 CRYPTO_ALG_NEED_FALLBACK, 1626 .cra_blocksize = SHA256_BLOCK_SIZE, 1627 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1628 sizeof(struct omap_sham_hmac_ctx), 1629 .cra_alignmask = OMAP_ALIGN_MASK, 1630 .cra_module = THIS_MODULE, 1631 .cra_init = omap_sham_cra_sha256_init, 1632 .cra_exit = omap_sham_cra_exit, 1633 } 1634 }, 1635 }; 1636 1637 static struct ahash_alg algs_sha384_sha512[] = { 1638 { 1639 .init = omap_sham_init, 1640 .update = omap_sham_update, 1641 .final = omap_sham_final, 1642 .finup = omap_sham_finup, 1643 .digest = omap_sham_digest, 1644 .halg.digestsize = SHA384_DIGEST_SIZE, 1645 .halg.base = { 1646 .cra_name = "sha384", 1647 .cra_driver_name = "omap-sha384", 1648 .cra_priority = 400, 1649 .cra_flags = CRYPTO_ALG_ASYNC | 1650 CRYPTO_ALG_NEED_FALLBACK, 1651 .cra_blocksize = SHA384_BLOCK_SIZE, 1652 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1653 .cra_alignmask = OMAP_ALIGN_MASK, 1654 .cra_module = THIS_MODULE, 1655 .cra_init = omap_sham_cra_init, 1656 .cra_exit = omap_sham_cra_exit, 1657 } 1658 }, 1659 { 1660 .init = omap_sham_init, 1661 .update = omap_sham_update, 1662 .final = omap_sham_final, 1663 .finup = omap_sham_finup, 1664 .digest = omap_sham_digest, 1665 .halg.digestsize = SHA512_DIGEST_SIZE, 1666 .halg.base = { 1667 .cra_name = "sha512", 1668 .cra_driver_name = "omap-sha512", 1669 .cra_priority = 400, 1670 .cra_flags = CRYPTO_ALG_ASYNC | 1671 CRYPTO_ALG_NEED_FALLBACK, 1672 .cra_blocksize = SHA512_BLOCK_SIZE, 1673 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1674 .cra_alignmask = OMAP_ALIGN_MASK, 1675 .cra_module = THIS_MODULE, 1676 .cra_init = omap_sham_cra_init, 1677 .cra_exit = omap_sham_cra_exit, 1678 } 1679 }, 1680 { 1681 .init = omap_sham_init, 1682 .update = omap_sham_update, 1683 .final = omap_sham_final, 1684 .finup = omap_sham_finup, 1685 .digest = omap_sham_digest, 1686 .setkey = omap_sham_setkey, 1687 .halg.digestsize = SHA384_DIGEST_SIZE, 1688 .halg.base = { 1689 .cra_name = "hmac(sha384)", 1690 .cra_driver_name = "omap-hmac-sha384", 1691 .cra_priority = 400, 1692 .cra_flags = CRYPTO_ALG_ASYNC | 1693 CRYPTO_ALG_NEED_FALLBACK, 1694 .cra_blocksize = SHA384_BLOCK_SIZE, 1695 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1696 sizeof(struct omap_sham_hmac_ctx), 1697 .cra_alignmask = OMAP_ALIGN_MASK, 1698 .cra_module = THIS_MODULE, 1699 .cra_init = omap_sham_cra_sha384_init, 1700 .cra_exit = omap_sham_cra_exit, 1701 } 1702 }, 1703 { 1704 .init = omap_sham_init, 1705 .update = omap_sham_update, 1706 .final = omap_sham_final, 1707 .finup = omap_sham_finup, 1708 .digest = omap_sham_digest, 1709 .setkey = omap_sham_setkey, 1710 .halg.digestsize = SHA512_DIGEST_SIZE, 1711 .halg.base = { 1712 .cra_name = "hmac(sha512)", 1713 .cra_driver_name = "omap-hmac-sha512", 1714 .cra_priority = 400, 1715 .cra_flags = CRYPTO_ALG_ASYNC | 1716 CRYPTO_ALG_NEED_FALLBACK, 1717 .cra_blocksize = SHA512_BLOCK_SIZE, 1718 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1719 sizeof(struct omap_sham_hmac_ctx), 1720 .cra_alignmask = OMAP_ALIGN_MASK, 1721 .cra_module = THIS_MODULE, 1722 .cra_init = omap_sham_cra_sha512_init, 1723 .cra_exit = omap_sham_cra_exit, 1724 } 1725 }, 1726 }; 1727 1728 static void omap_sham_done_task(unsigned long data) 1729 { 1730 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1731 int err = 0; 1732 1733 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1734 omap_sham_handle_queue(dd, NULL); 1735 return; 1736 } 1737 1738 if (test_bit(FLAGS_CPU, &dd->flags)) { 1739 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) 1740 goto finish; 1741 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1742 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1743 omap_sham_update_dma_stop(dd); 1744 if (dd->err) { 1745 err = dd->err; 1746 goto finish; 1747 } 1748 } 1749 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1750 /* hash or semi-hash ready */ 1751 clear_bit(FLAGS_DMA_READY, &dd->flags); 1752 goto finish; 1753 } 1754 } 1755 1756 return; 1757 1758 finish: 1759 dev_dbg(dd->dev, "update done: err: %d\n", err); 1760 /* finish curent request */ 1761 omap_sham_finish_req(dd->req, err); 1762 1763 /* If we are not busy, process next req */ 1764 if (!test_bit(FLAGS_BUSY, &dd->flags)) 1765 omap_sham_handle_queue(dd, NULL); 1766 } 1767 1768 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1769 { 1770 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1771 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1772 } else { 1773 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1774 tasklet_schedule(&dd->done_task); 1775 } 1776 1777 return IRQ_HANDLED; 1778 } 1779 1780 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1781 { 1782 struct omap_sham_dev *dd = dev_id; 1783 1784 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1785 /* final -> allow device to go to power-saving mode */ 1786 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1787 1788 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1789 SHA_REG_CTRL_OUTPUT_READY); 1790 omap_sham_read(dd, SHA_REG_CTRL); 1791 1792 return omap_sham_irq_common(dd); 1793 } 1794 1795 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1796 { 1797 struct omap_sham_dev *dd = dev_id; 1798 1799 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1800 1801 return omap_sham_irq_common(dd); 1802 } 1803 1804 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1805 { 1806 .algs_list = algs_sha1_md5, 1807 .size = ARRAY_SIZE(algs_sha1_md5), 1808 }, 1809 }; 1810 1811 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1812 .algs_info = omap_sham_algs_info_omap2, 1813 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1814 .flags = BIT(FLAGS_BE32_SHA1), 1815 .digest_size = SHA1_DIGEST_SIZE, 1816 .copy_hash = omap_sham_copy_hash_omap2, 1817 .write_ctrl = omap_sham_write_ctrl_omap2, 1818 .trigger = omap_sham_trigger_omap2, 1819 .poll_irq = omap_sham_poll_irq_omap2, 1820 .intr_hdlr = omap_sham_irq_omap2, 1821 .idigest_ofs = 0x00, 1822 .din_ofs = 0x1c, 1823 .digcnt_ofs = 0x14, 1824 .rev_ofs = 0x5c, 1825 .mask_ofs = 0x60, 1826 .sysstatus_ofs = 0x64, 1827 .major_mask = 0xf0, 1828 .major_shift = 4, 1829 .minor_mask = 0x0f, 1830 .minor_shift = 0, 1831 }; 1832 1833 #ifdef CONFIG_OF 1834 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1835 { 1836 .algs_list = algs_sha1_md5, 1837 .size = ARRAY_SIZE(algs_sha1_md5), 1838 }, 1839 { 1840 .algs_list = algs_sha224_sha256, 1841 .size = ARRAY_SIZE(algs_sha224_sha256), 1842 }, 1843 }; 1844 1845 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1846 .algs_info = omap_sham_algs_info_omap4, 1847 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1848 .flags = BIT(FLAGS_AUTO_XOR), 1849 .digest_size = SHA256_DIGEST_SIZE, 1850 .copy_hash = omap_sham_copy_hash_omap4, 1851 .write_ctrl = omap_sham_write_ctrl_omap4, 1852 .trigger = omap_sham_trigger_omap4, 1853 .poll_irq = omap_sham_poll_irq_omap4, 1854 .intr_hdlr = omap_sham_irq_omap4, 1855 .idigest_ofs = 0x020, 1856 .odigest_ofs = 0x0, 1857 .din_ofs = 0x080, 1858 .digcnt_ofs = 0x040, 1859 .rev_ofs = 0x100, 1860 .mask_ofs = 0x110, 1861 .sysstatus_ofs = 0x114, 1862 .mode_ofs = 0x44, 1863 .length_ofs = 0x48, 1864 .major_mask = 0x0700, 1865 .major_shift = 8, 1866 .minor_mask = 0x003f, 1867 .minor_shift = 0, 1868 }; 1869 1870 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1871 { 1872 .algs_list = algs_sha1_md5, 1873 .size = ARRAY_SIZE(algs_sha1_md5), 1874 }, 1875 { 1876 .algs_list = algs_sha224_sha256, 1877 .size = ARRAY_SIZE(algs_sha224_sha256), 1878 }, 1879 { 1880 .algs_list = algs_sha384_sha512, 1881 .size = ARRAY_SIZE(algs_sha384_sha512), 1882 }, 1883 }; 1884 1885 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1886 .algs_info = omap_sham_algs_info_omap5, 1887 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1888 .flags = BIT(FLAGS_AUTO_XOR), 1889 .digest_size = SHA512_DIGEST_SIZE, 1890 .copy_hash = omap_sham_copy_hash_omap4, 1891 .write_ctrl = omap_sham_write_ctrl_omap4, 1892 .trigger = omap_sham_trigger_omap4, 1893 .poll_irq = omap_sham_poll_irq_omap4, 1894 .intr_hdlr = omap_sham_irq_omap4, 1895 .idigest_ofs = 0x240, 1896 .odigest_ofs = 0x200, 1897 .din_ofs = 0x080, 1898 .digcnt_ofs = 0x280, 1899 .rev_ofs = 0x100, 1900 .mask_ofs = 0x110, 1901 .sysstatus_ofs = 0x114, 1902 .mode_ofs = 0x284, 1903 .length_ofs = 0x288, 1904 .major_mask = 0x0700, 1905 .major_shift = 8, 1906 .minor_mask = 0x003f, 1907 .minor_shift = 0, 1908 }; 1909 1910 static const struct of_device_id omap_sham_of_match[] = { 1911 { 1912 .compatible = "ti,omap2-sham", 1913 .data = &omap_sham_pdata_omap2, 1914 }, 1915 { 1916 .compatible = "ti,omap3-sham", 1917 .data = &omap_sham_pdata_omap2, 1918 }, 1919 { 1920 .compatible = "ti,omap4-sham", 1921 .data = &omap_sham_pdata_omap4, 1922 }, 1923 { 1924 .compatible = "ti,omap5-sham", 1925 .data = &omap_sham_pdata_omap5, 1926 }, 1927 {}, 1928 }; 1929 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1930 1931 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1932 struct device *dev, struct resource *res) 1933 { 1934 struct device_node *node = dev->of_node; 1935 int err = 0; 1936 1937 dd->pdata = of_device_get_match_data(dev); 1938 if (!dd->pdata) { 1939 dev_err(dev, "no compatible OF match\n"); 1940 err = -EINVAL; 1941 goto err; 1942 } 1943 1944 err = of_address_to_resource(node, 0, res); 1945 if (err < 0) { 1946 dev_err(dev, "can't translate OF node address\n"); 1947 err = -EINVAL; 1948 goto err; 1949 } 1950 1951 dd->irq = irq_of_parse_and_map(node, 0); 1952 if (!dd->irq) { 1953 dev_err(dev, "can't translate OF irq value\n"); 1954 err = -EINVAL; 1955 goto err; 1956 } 1957 1958 err: 1959 return err; 1960 } 1961 #else 1962 static const struct of_device_id omap_sham_of_match[] = { 1963 {}, 1964 }; 1965 1966 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1967 struct device *dev, struct resource *res) 1968 { 1969 return -EINVAL; 1970 } 1971 #endif 1972 1973 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 1974 struct platform_device *pdev, struct resource *res) 1975 { 1976 struct device *dev = &pdev->dev; 1977 struct resource *r; 1978 int err = 0; 1979 1980 /* Get the base address */ 1981 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1982 if (!r) { 1983 dev_err(dev, "no MEM resource info\n"); 1984 err = -ENODEV; 1985 goto err; 1986 } 1987 memcpy(res, r, sizeof(*res)); 1988 1989 /* Get the IRQ */ 1990 dd->irq = platform_get_irq(pdev, 0); 1991 if (dd->irq < 0) { 1992 dev_err(dev, "no IRQ resource info\n"); 1993 err = dd->irq; 1994 goto err; 1995 } 1996 1997 /* Only OMAP2/3 can be non-DT */ 1998 dd->pdata = &omap_sham_pdata_omap2; 1999 2000 err: 2001 return err; 2002 } 2003 2004 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 2005 char *buf) 2006 { 2007 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2008 2009 return sprintf(buf, "%d\n", dd->fallback_sz); 2010 } 2011 2012 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 2013 const char *buf, size_t size) 2014 { 2015 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2016 ssize_t status; 2017 long value; 2018 2019 status = kstrtol(buf, 0, &value); 2020 if (status) 2021 return status; 2022 2023 /* HW accelerator only works with buffers > 9 */ 2024 if (value < 9) { 2025 dev_err(dev, "minimum fallback size 9\n"); 2026 return -EINVAL; 2027 } 2028 2029 dd->fallback_sz = value; 2030 2031 return size; 2032 } 2033 2034 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 2035 char *buf) 2036 { 2037 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2038 2039 return sprintf(buf, "%d\n", dd->queue.max_qlen); 2040 } 2041 2042 static ssize_t queue_len_store(struct device *dev, 2043 struct device_attribute *attr, const char *buf, 2044 size_t size) 2045 { 2046 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2047 ssize_t status; 2048 long value; 2049 unsigned long flags; 2050 2051 status = kstrtol(buf, 0, &value); 2052 if (status) 2053 return status; 2054 2055 if (value < 1) 2056 return -EINVAL; 2057 2058 /* 2059 * Changing the queue size in fly is safe, if size becomes smaller 2060 * than current size, it will just not accept new entries until 2061 * it has shrank enough. 2062 */ 2063 spin_lock_irqsave(&dd->lock, flags); 2064 dd->queue.max_qlen = value; 2065 spin_unlock_irqrestore(&dd->lock, flags); 2066 2067 return size; 2068 } 2069 2070 static DEVICE_ATTR_RW(queue_len); 2071 static DEVICE_ATTR_RW(fallback); 2072 2073 static struct attribute *omap_sham_attrs[] = { 2074 &dev_attr_queue_len.attr, 2075 &dev_attr_fallback.attr, 2076 NULL, 2077 }; 2078 2079 static struct attribute_group omap_sham_attr_group = { 2080 .attrs = omap_sham_attrs, 2081 }; 2082 2083 static int omap_sham_probe(struct platform_device *pdev) 2084 { 2085 struct omap_sham_dev *dd; 2086 struct device *dev = &pdev->dev; 2087 struct resource res; 2088 dma_cap_mask_t mask; 2089 int err, i, j; 2090 u32 rev; 2091 2092 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 2093 if (dd == NULL) { 2094 dev_err(dev, "unable to alloc data struct.\n"); 2095 err = -ENOMEM; 2096 goto data_err; 2097 } 2098 dd->dev = dev; 2099 platform_set_drvdata(pdev, dd); 2100 2101 INIT_LIST_HEAD(&dd->list); 2102 spin_lock_init(&dd->lock); 2103 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 2104 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 2105 2106 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 2107 omap_sham_get_res_pdev(dd, pdev, &res); 2108 if (err) 2109 goto data_err; 2110 2111 dd->io_base = devm_ioremap_resource(dev, &res); 2112 if (IS_ERR(dd->io_base)) { 2113 err = PTR_ERR(dd->io_base); 2114 goto data_err; 2115 } 2116 dd->phys_base = res.start; 2117 2118 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 2119 IRQF_TRIGGER_NONE, dev_name(dev), dd); 2120 if (err) { 2121 dev_err(dev, "unable to request irq %d, err = %d\n", 2122 dd->irq, err); 2123 goto data_err; 2124 } 2125 2126 dma_cap_zero(mask); 2127 dma_cap_set(DMA_SLAVE, mask); 2128 2129 dd->dma_lch = dma_request_chan(dev, "rx"); 2130 if (IS_ERR(dd->dma_lch)) { 2131 err = PTR_ERR(dd->dma_lch); 2132 if (err == -EPROBE_DEFER) 2133 goto data_err; 2134 2135 dd->polling_mode = 1; 2136 dev_dbg(dev, "using polling mode instead of dma\n"); 2137 } 2138 2139 dd->flags |= dd->pdata->flags; 2140 2141 pm_runtime_use_autosuspend(dev); 2142 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 2143 2144 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; 2145 2146 pm_runtime_enable(dev); 2147 pm_runtime_irq_safe(dev); 2148 2149 err = pm_runtime_get_sync(dev); 2150 if (err < 0) { 2151 dev_err(dev, "failed to get sync: %d\n", err); 2152 goto err_pm; 2153 } 2154 2155 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 2156 pm_runtime_put_sync(&pdev->dev); 2157 2158 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 2159 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 2160 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 2161 2162 spin_lock(&sham.lock); 2163 list_add_tail(&dd->list, &sham.dev_list); 2164 spin_unlock(&sham.lock); 2165 2166 for (i = 0; i < dd->pdata->algs_info_size; i++) { 2167 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2168 struct ahash_alg *alg; 2169 2170 alg = &dd->pdata->algs_info[i].algs_list[j]; 2171 alg->export = omap_sham_export; 2172 alg->import = omap_sham_import; 2173 alg->halg.statesize = sizeof(struct omap_sham_reqctx) + 2174 BUFLEN; 2175 err = crypto_register_ahash(alg); 2176 if (err) 2177 goto err_algs; 2178 2179 dd->pdata->algs_info[i].registered++; 2180 } 2181 } 2182 2183 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); 2184 if (err) { 2185 dev_err(dev, "could not create sysfs device attrs\n"); 2186 goto err_algs; 2187 } 2188 2189 return 0; 2190 2191 err_algs: 2192 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2193 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2194 crypto_unregister_ahash( 2195 &dd->pdata->algs_info[i].algs_list[j]); 2196 err_pm: 2197 pm_runtime_disable(dev); 2198 if (!dd->polling_mode) 2199 dma_release_channel(dd->dma_lch); 2200 data_err: 2201 dev_err(dev, "initialization failed.\n"); 2202 2203 return err; 2204 } 2205 2206 static int omap_sham_remove(struct platform_device *pdev) 2207 { 2208 struct omap_sham_dev *dd; 2209 int i, j; 2210 2211 dd = platform_get_drvdata(pdev); 2212 if (!dd) 2213 return -ENODEV; 2214 spin_lock(&sham.lock); 2215 list_del(&dd->list); 2216 spin_unlock(&sham.lock); 2217 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2218 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2219 crypto_unregister_ahash( 2220 &dd->pdata->algs_info[i].algs_list[j]); 2221 tasklet_kill(&dd->done_task); 2222 pm_runtime_disable(&pdev->dev); 2223 2224 if (!dd->polling_mode) 2225 dma_release_channel(dd->dma_lch); 2226 2227 return 0; 2228 } 2229 2230 #ifdef CONFIG_PM_SLEEP 2231 static int omap_sham_suspend(struct device *dev) 2232 { 2233 pm_runtime_put_sync(dev); 2234 return 0; 2235 } 2236 2237 static int omap_sham_resume(struct device *dev) 2238 { 2239 int err = pm_runtime_get_sync(dev); 2240 if (err < 0) { 2241 dev_err(dev, "failed to get sync: %d\n", err); 2242 return err; 2243 } 2244 return 0; 2245 } 2246 #endif 2247 2248 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2249 2250 static struct platform_driver omap_sham_driver = { 2251 .probe = omap_sham_probe, 2252 .remove = omap_sham_remove, 2253 .driver = { 2254 .name = "omap-sham", 2255 .pm = &omap_sham_pm_ops, 2256 .of_match_table = omap_sham_of_match, 2257 }, 2258 }; 2259 2260 module_platform_driver(omap_sham_driver); 2261 2262 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2263 MODULE_LICENSE("GPL v2"); 2264 MODULE_AUTHOR("Dmitry Kasatkin"); 2265 MODULE_ALIAS("platform:omap-sham"); 2266