1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP SHA1/MD5 HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * Some ideas are from old omap-sha1-md5.c driver. 15 */ 16 17 #define pr_fmt(fmt) "%s: " fmt, __func__ 18 19 #include <linux/err.h> 20 #include <linux/device.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/irq.h> 27 #include <linux/io.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/delay.h> 38 #include <linux/crypto.h> 39 #include <linux/cryptohash.h> 40 #include <crypto/scatterwalk.h> 41 #include <crypto/algapi.h> 42 #include <crypto/sha.h> 43 #include <crypto/hash.h> 44 #include <crypto/hmac.h> 45 #include <crypto/internal/hash.h> 46 47 #define MD5_DIGEST_SIZE 16 48 49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 52 53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 54 55 #define SHA_REG_CTRL 0x18 56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 59 #define SHA_REG_CTRL_ALGO (1 << 2) 60 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 62 63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 64 65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 66 #define SHA_REG_MASK_DMA_EN (1 << 3) 67 #define SHA_REG_MASK_IT_EN (1 << 2) 68 #define SHA_REG_MASK_SOFTRESET (1 << 1) 69 #define SHA_REG_AUTOIDLE (1 << 0) 70 71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 73 74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 79 80 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 87 88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 89 90 #define SHA_REG_IRQSTATUS 0x118 91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 95 96 #define SHA_REG_IRQENA 0x11C 97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 101 102 #define DEFAULT_TIMEOUT_INTERVAL HZ 103 104 #define DEFAULT_AUTOSUSPEND_DELAY 1000 105 106 /* mostly device flags */ 107 #define FLAGS_BUSY 0 108 #define FLAGS_FINAL 1 109 #define FLAGS_DMA_ACTIVE 2 110 #define FLAGS_OUTPUT_READY 3 111 #define FLAGS_INIT 4 112 #define FLAGS_CPU 5 113 #define FLAGS_DMA_READY 6 114 #define FLAGS_AUTO_XOR 7 115 #define FLAGS_BE32_SHA1 8 116 #define FLAGS_SGS_COPIED 9 117 #define FLAGS_SGS_ALLOCED 10 118 /* context flags */ 119 #define FLAGS_FINUP 16 120 121 #define FLAGS_MODE_SHIFT 18 122 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 126 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 127 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 128 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 129 130 #define FLAGS_HMAC 21 131 #define FLAGS_ERROR 22 132 133 #define OP_UPDATE 1 134 #define OP_FINAL 2 135 136 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 137 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 138 139 #define BUFLEN SHA512_BLOCK_SIZE 140 #define OMAP_SHA_DMA_THRESHOLD 256 141 142 struct omap_sham_dev; 143 144 struct omap_sham_reqctx { 145 struct omap_sham_dev *dd; 146 unsigned long flags; 147 unsigned long op; 148 149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 150 size_t digcnt; 151 size_t bufcnt; 152 size_t buflen; 153 154 /* walk state */ 155 struct scatterlist *sg; 156 struct scatterlist sgl[2]; 157 int offset; /* offset in current sg */ 158 int sg_len; 159 unsigned int total; /* total request */ 160 161 u8 buffer[0] OMAP_ALIGNED; 162 }; 163 164 struct omap_sham_hmac_ctx { 165 struct crypto_shash *shash; 166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 168 }; 169 170 struct omap_sham_ctx { 171 struct omap_sham_dev *dd; 172 173 unsigned long flags; 174 175 /* fallback stuff */ 176 struct crypto_shash *fallback; 177 178 struct omap_sham_hmac_ctx base[0]; 179 }; 180 181 #define OMAP_SHAM_QUEUE_LENGTH 10 182 183 struct omap_sham_algs_info { 184 struct ahash_alg *algs_list; 185 unsigned int size; 186 unsigned int registered; 187 }; 188 189 struct omap_sham_pdata { 190 struct omap_sham_algs_info *algs_info; 191 unsigned int algs_info_size; 192 unsigned long flags; 193 int digest_size; 194 195 void (*copy_hash)(struct ahash_request *req, int out); 196 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 197 int final, int dma); 198 void (*trigger)(struct omap_sham_dev *dd, size_t length); 199 int (*poll_irq)(struct omap_sham_dev *dd); 200 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 201 202 u32 odigest_ofs; 203 u32 idigest_ofs; 204 u32 din_ofs; 205 u32 digcnt_ofs; 206 u32 rev_ofs; 207 u32 mask_ofs; 208 u32 sysstatus_ofs; 209 u32 mode_ofs; 210 u32 length_ofs; 211 212 u32 major_mask; 213 u32 major_shift; 214 u32 minor_mask; 215 u32 minor_shift; 216 }; 217 218 struct omap_sham_dev { 219 struct list_head list; 220 unsigned long phys_base; 221 struct device *dev; 222 void __iomem *io_base; 223 int irq; 224 spinlock_t lock; 225 int err; 226 struct dma_chan *dma_lch; 227 struct tasklet_struct done_task; 228 u8 polling_mode; 229 u8 xmit_buf[BUFLEN] OMAP_ALIGNED; 230 231 unsigned long flags; 232 int fallback_sz; 233 struct crypto_queue queue; 234 struct ahash_request *req; 235 236 const struct omap_sham_pdata *pdata; 237 }; 238 239 struct omap_sham_drv { 240 struct list_head dev_list; 241 spinlock_t lock; 242 unsigned long flags; 243 }; 244 245 static struct omap_sham_drv sham = { 246 .dev_list = LIST_HEAD_INIT(sham.dev_list), 247 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 248 }; 249 250 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 251 { 252 return __raw_readl(dd->io_base + offset); 253 } 254 255 static inline void omap_sham_write(struct omap_sham_dev *dd, 256 u32 offset, u32 value) 257 { 258 __raw_writel(value, dd->io_base + offset); 259 } 260 261 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 262 u32 value, u32 mask) 263 { 264 u32 val; 265 266 val = omap_sham_read(dd, address); 267 val &= ~mask; 268 val |= value; 269 omap_sham_write(dd, address, val); 270 } 271 272 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 273 { 274 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 275 276 while (!(omap_sham_read(dd, offset) & bit)) { 277 if (time_is_before_jiffies(timeout)) 278 return -ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 285 { 286 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 287 struct omap_sham_dev *dd = ctx->dd; 288 u32 *hash = (u32 *)ctx->digest; 289 int i; 290 291 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 292 if (out) 293 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 294 else 295 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 296 } 297 } 298 299 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 300 { 301 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 302 struct omap_sham_dev *dd = ctx->dd; 303 int i; 304 305 if (ctx->flags & BIT(FLAGS_HMAC)) { 306 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 307 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 308 struct omap_sham_hmac_ctx *bctx = tctx->base; 309 u32 *opad = (u32 *)bctx->opad; 310 311 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 312 if (out) 313 opad[i] = omap_sham_read(dd, 314 SHA_REG_ODIGEST(dd, i)); 315 else 316 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 317 opad[i]); 318 } 319 } 320 321 omap_sham_copy_hash_omap2(req, out); 322 } 323 324 static void omap_sham_copy_ready_hash(struct ahash_request *req) 325 { 326 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 327 u32 *in = (u32 *)ctx->digest; 328 u32 *hash = (u32 *)req->result; 329 int i, d, big_endian = 0; 330 331 if (!hash) 332 return; 333 334 switch (ctx->flags & FLAGS_MODE_MASK) { 335 case FLAGS_MODE_MD5: 336 d = MD5_DIGEST_SIZE / sizeof(u32); 337 break; 338 case FLAGS_MODE_SHA1: 339 /* OMAP2 SHA1 is big endian */ 340 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 341 big_endian = 1; 342 d = SHA1_DIGEST_SIZE / sizeof(u32); 343 break; 344 case FLAGS_MODE_SHA224: 345 d = SHA224_DIGEST_SIZE / sizeof(u32); 346 break; 347 case FLAGS_MODE_SHA256: 348 d = SHA256_DIGEST_SIZE / sizeof(u32); 349 break; 350 case FLAGS_MODE_SHA384: 351 d = SHA384_DIGEST_SIZE / sizeof(u32); 352 break; 353 case FLAGS_MODE_SHA512: 354 d = SHA512_DIGEST_SIZE / sizeof(u32); 355 break; 356 default: 357 d = 0; 358 } 359 360 if (big_endian) 361 for (i = 0; i < d; i++) 362 hash[i] = be32_to_cpu(in[i]); 363 else 364 for (i = 0; i < d; i++) 365 hash[i] = le32_to_cpu(in[i]); 366 } 367 368 static int omap_sham_hw_init(struct omap_sham_dev *dd) 369 { 370 int err; 371 372 err = pm_runtime_get_sync(dd->dev); 373 if (err < 0) { 374 dev_err(dd->dev, "failed to get sync: %d\n", err); 375 return err; 376 } 377 378 if (!test_bit(FLAGS_INIT, &dd->flags)) { 379 set_bit(FLAGS_INIT, &dd->flags); 380 dd->err = 0; 381 } 382 383 return 0; 384 } 385 386 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 387 int final, int dma) 388 { 389 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 390 u32 val = length << 5, mask; 391 392 if (likely(ctx->digcnt)) 393 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 394 395 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 396 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 397 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 398 /* 399 * Setting ALGO_CONST only for the first iteration 400 * and CLOSE_HASH only for the last one. 401 */ 402 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 403 val |= SHA_REG_CTRL_ALGO; 404 if (!ctx->digcnt) 405 val |= SHA_REG_CTRL_ALGO_CONST; 406 if (final) 407 val |= SHA_REG_CTRL_CLOSE_HASH; 408 409 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 410 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 411 412 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 413 } 414 415 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 416 { 417 } 418 419 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 420 { 421 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 422 } 423 424 static int get_block_size(struct omap_sham_reqctx *ctx) 425 { 426 int d; 427 428 switch (ctx->flags & FLAGS_MODE_MASK) { 429 case FLAGS_MODE_MD5: 430 case FLAGS_MODE_SHA1: 431 d = SHA1_BLOCK_SIZE; 432 break; 433 case FLAGS_MODE_SHA224: 434 case FLAGS_MODE_SHA256: 435 d = SHA256_BLOCK_SIZE; 436 break; 437 case FLAGS_MODE_SHA384: 438 case FLAGS_MODE_SHA512: 439 d = SHA512_BLOCK_SIZE; 440 break; 441 default: 442 d = 0; 443 } 444 445 return d; 446 } 447 448 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 449 u32 *value, int count) 450 { 451 for (; count--; value++, offset += 4) 452 omap_sham_write(dd, offset, *value); 453 } 454 455 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 456 int final, int dma) 457 { 458 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 459 u32 val, mask; 460 461 /* 462 * Setting ALGO_CONST only for the first iteration and 463 * CLOSE_HASH only for the last one. Note that flags mode bits 464 * correspond to algorithm encoding in mode register. 465 */ 466 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 467 if (!ctx->digcnt) { 468 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 469 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 470 struct omap_sham_hmac_ctx *bctx = tctx->base; 471 int bs, nr_dr; 472 473 val |= SHA_REG_MODE_ALGO_CONSTANT; 474 475 if (ctx->flags & BIT(FLAGS_HMAC)) { 476 bs = get_block_size(ctx); 477 nr_dr = bs / (2 * sizeof(u32)); 478 val |= SHA_REG_MODE_HMAC_KEY_PROC; 479 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 480 (u32 *)bctx->ipad, nr_dr); 481 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 482 (u32 *)bctx->ipad + nr_dr, nr_dr); 483 ctx->digcnt += bs; 484 } 485 } 486 487 if (final) { 488 val |= SHA_REG_MODE_CLOSE_HASH; 489 490 if (ctx->flags & BIT(FLAGS_HMAC)) 491 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 492 } 493 494 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 495 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 496 SHA_REG_MODE_HMAC_KEY_PROC; 497 498 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 499 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 500 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 501 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 502 SHA_REG_MASK_IT_EN | 503 (dma ? SHA_REG_MASK_DMA_EN : 0), 504 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 505 } 506 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 508 { 509 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 510 } 511 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 513 { 514 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 515 SHA_REG_IRQSTATUS_INPUT_RDY); 516 } 517 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, 519 int final) 520 { 521 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 522 int count, len32, bs32, offset = 0; 523 const u32 *buffer; 524 int mlen; 525 struct sg_mapping_iter mi; 526 527 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 528 ctx->digcnt, length, final); 529 530 dd->pdata->write_ctrl(dd, length, final, 0); 531 dd->pdata->trigger(dd, length); 532 533 /* should be non-zero before next lines to disable clocks later */ 534 ctx->digcnt += length; 535 ctx->total -= length; 536 537 if (final) 538 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 539 540 set_bit(FLAGS_CPU, &dd->flags); 541 542 len32 = DIV_ROUND_UP(length, sizeof(u32)); 543 bs32 = get_block_size(ctx) / sizeof(u32); 544 545 sg_miter_start(&mi, ctx->sg, ctx->sg_len, 546 SG_MITER_FROM_SG | SG_MITER_ATOMIC); 547 548 mlen = 0; 549 550 while (len32) { 551 if (dd->pdata->poll_irq(dd)) 552 return -ETIMEDOUT; 553 554 for (count = 0; count < min(len32, bs32); count++, offset++) { 555 if (!mlen) { 556 sg_miter_next(&mi); 557 mlen = mi.length; 558 if (!mlen) { 559 pr_err("sg miter failure.\n"); 560 return -EINVAL; 561 } 562 offset = 0; 563 buffer = mi.addr; 564 } 565 omap_sham_write(dd, SHA_REG_DIN(dd, count), 566 buffer[offset]); 567 mlen -= 4; 568 } 569 len32 -= min(len32, bs32); 570 } 571 572 sg_miter_stop(&mi); 573 574 return -EINPROGRESS; 575 } 576 577 static void omap_sham_dma_callback(void *param) 578 { 579 struct omap_sham_dev *dd = param; 580 581 set_bit(FLAGS_DMA_READY, &dd->flags); 582 tasklet_schedule(&dd->done_task); 583 } 584 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, 586 int final) 587 { 588 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 589 struct dma_async_tx_descriptor *tx; 590 struct dma_slave_config cfg; 591 int ret; 592 593 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 594 ctx->digcnt, length, final); 595 596 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { 597 dev_err(dd->dev, "dma_map_sg error\n"); 598 return -EINVAL; 599 } 600 601 memset(&cfg, 0, sizeof(cfg)); 602 603 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 604 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 605 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; 606 607 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 608 if (ret) { 609 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 610 return ret; 611 } 612 613 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, 614 DMA_MEM_TO_DEV, 615 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 616 617 if (!tx) { 618 dev_err(dd->dev, "prep_slave_sg failed\n"); 619 return -EINVAL; 620 } 621 622 tx->callback = omap_sham_dma_callback; 623 tx->callback_param = dd; 624 625 dd->pdata->write_ctrl(dd, length, final, 1); 626 627 ctx->digcnt += length; 628 ctx->total -= length; 629 630 if (final) 631 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 632 633 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 634 635 dmaengine_submit(tx); 636 dma_async_issue_pending(dd->dma_lch); 637 638 dd->pdata->trigger(dd, length); 639 640 return -EINPROGRESS; 641 } 642 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, 644 struct scatterlist *sg, int bs, int new_len) 645 { 646 int n = sg_nents(sg); 647 struct scatterlist *tmp; 648 int offset = ctx->offset; 649 650 if (ctx->bufcnt) 651 n++; 652 653 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 654 if (!ctx->sg) 655 return -ENOMEM; 656 657 sg_init_table(ctx->sg, n); 658 659 tmp = ctx->sg; 660 661 ctx->sg_len = 0; 662 663 if (ctx->bufcnt) { 664 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 665 tmp = sg_next(tmp); 666 ctx->sg_len++; 667 } 668 669 while (sg && new_len) { 670 int len = sg->length - offset; 671 672 if (offset) { 673 offset -= sg->length; 674 if (offset < 0) 675 offset = 0; 676 } 677 678 if (new_len < len) 679 len = new_len; 680 681 if (len > 0) { 682 new_len -= len; 683 sg_set_page(tmp, sg_page(sg), len, sg->offset); 684 if (new_len <= 0) 685 sg_mark_end(tmp); 686 tmp = sg_next(tmp); 687 ctx->sg_len++; 688 } 689 690 sg = sg_next(sg); 691 } 692 693 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); 694 695 ctx->bufcnt = 0; 696 697 return 0; 698 } 699 700 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, 701 struct scatterlist *sg, int bs, int new_len) 702 { 703 int pages; 704 void *buf; 705 int len; 706 707 len = new_len + ctx->bufcnt; 708 709 pages = get_order(ctx->total); 710 711 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 712 if (!buf) { 713 pr_err("Couldn't allocate pages for unaligned cases.\n"); 714 return -ENOMEM; 715 } 716 717 if (ctx->bufcnt) 718 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 719 720 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, 721 ctx->total - ctx->bufcnt, 0); 722 sg_init_table(ctx->sgl, 1); 723 sg_set_buf(ctx->sgl, buf, len); 724 ctx->sg = ctx->sgl; 725 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); 726 ctx->sg_len = 1; 727 ctx->bufcnt = 0; 728 ctx->offset = 0; 729 730 return 0; 731 } 732 733 static int omap_sham_align_sgs(struct scatterlist *sg, 734 int nbytes, int bs, bool final, 735 struct omap_sham_reqctx *rctx) 736 { 737 int n = 0; 738 bool aligned = true; 739 bool list_ok = true; 740 struct scatterlist *sg_tmp = sg; 741 int new_len; 742 int offset = rctx->offset; 743 744 if (!sg || !sg->length || !nbytes) 745 return 0; 746 747 new_len = nbytes; 748 749 if (offset) 750 list_ok = false; 751 752 if (final) 753 new_len = DIV_ROUND_UP(new_len, bs) * bs; 754 else 755 new_len = (new_len - 1) / bs * bs; 756 757 if (nbytes != new_len) 758 list_ok = false; 759 760 while (nbytes > 0 && sg_tmp) { 761 n++; 762 763 #ifdef CONFIG_ZONE_DMA 764 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { 765 aligned = false; 766 break; 767 } 768 #endif 769 770 if (offset < sg_tmp->length) { 771 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { 772 aligned = false; 773 break; 774 } 775 776 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { 777 aligned = false; 778 break; 779 } 780 } 781 782 if (offset) { 783 offset -= sg_tmp->length; 784 if (offset < 0) { 785 nbytes += offset; 786 offset = 0; 787 } 788 } else { 789 nbytes -= sg_tmp->length; 790 } 791 792 sg_tmp = sg_next(sg_tmp); 793 794 if (nbytes < 0) { 795 list_ok = false; 796 break; 797 } 798 } 799 800 if (!aligned) 801 return omap_sham_copy_sgs(rctx, sg, bs, new_len); 802 else if (!list_ok) 803 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); 804 805 rctx->sg_len = n; 806 rctx->sg = sg; 807 808 return 0; 809 } 810 811 static int omap_sham_prepare_request(struct ahash_request *req, bool update) 812 { 813 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 814 int bs; 815 int ret; 816 int nbytes; 817 bool final = rctx->flags & BIT(FLAGS_FINUP); 818 int xmit_len, hash_later; 819 820 bs = get_block_size(rctx); 821 822 if (update) 823 nbytes = req->nbytes; 824 else 825 nbytes = 0; 826 827 rctx->total = nbytes + rctx->bufcnt; 828 829 if (!rctx->total) 830 return 0; 831 832 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { 833 int len = bs - rctx->bufcnt % bs; 834 835 if (len > nbytes) 836 len = nbytes; 837 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, 838 0, len, 0); 839 rctx->bufcnt += len; 840 nbytes -= len; 841 rctx->offset = len; 842 } 843 844 if (rctx->bufcnt) 845 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); 846 847 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); 848 if (ret) 849 return ret; 850 851 xmit_len = rctx->total; 852 853 if (!IS_ALIGNED(xmit_len, bs)) { 854 if (final) 855 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs; 856 else 857 xmit_len = xmit_len / bs * bs; 858 } else if (!final) { 859 xmit_len -= bs; 860 } 861 862 hash_later = rctx->total - xmit_len; 863 if (hash_later < 0) 864 hash_later = 0; 865 866 if (rctx->bufcnt && nbytes) { 867 /* have data from previous operation and current */ 868 sg_init_table(rctx->sgl, 2); 869 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); 870 871 sg_chain(rctx->sgl, 2, req->src); 872 873 rctx->sg = rctx->sgl; 874 875 rctx->sg_len++; 876 } else if (rctx->bufcnt) { 877 /* have buffered data only */ 878 sg_init_table(rctx->sgl, 1); 879 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len); 880 881 rctx->sg = rctx->sgl; 882 883 rctx->sg_len = 1; 884 } 885 886 if (hash_later) { 887 int offset = 0; 888 889 if (hash_later > req->nbytes) { 890 memcpy(rctx->buffer, rctx->buffer + xmit_len, 891 hash_later - req->nbytes); 892 offset = hash_later - req->nbytes; 893 } 894 895 if (req->nbytes) { 896 scatterwalk_map_and_copy(rctx->buffer + offset, 897 req->src, 898 offset + req->nbytes - 899 hash_later, hash_later, 0); 900 } 901 902 rctx->bufcnt = hash_later; 903 } else { 904 rctx->bufcnt = 0; 905 } 906 907 if (!final) 908 rctx->total = xmit_len; 909 910 return 0; 911 } 912 913 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 914 { 915 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 916 917 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 918 919 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); 920 921 return 0; 922 } 923 924 static int omap_sham_init(struct ahash_request *req) 925 { 926 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 927 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 928 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 929 struct omap_sham_dev *dd = NULL, *tmp; 930 int bs = 0; 931 932 spin_lock_bh(&sham.lock); 933 if (!tctx->dd) { 934 list_for_each_entry(tmp, &sham.dev_list, list) { 935 dd = tmp; 936 break; 937 } 938 tctx->dd = dd; 939 } else { 940 dd = tctx->dd; 941 } 942 spin_unlock_bh(&sham.lock); 943 944 ctx->dd = dd; 945 946 ctx->flags = 0; 947 948 dev_dbg(dd->dev, "init: digest size: %d\n", 949 crypto_ahash_digestsize(tfm)); 950 951 switch (crypto_ahash_digestsize(tfm)) { 952 case MD5_DIGEST_SIZE: 953 ctx->flags |= FLAGS_MODE_MD5; 954 bs = SHA1_BLOCK_SIZE; 955 break; 956 case SHA1_DIGEST_SIZE: 957 ctx->flags |= FLAGS_MODE_SHA1; 958 bs = SHA1_BLOCK_SIZE; 959 break; 960 case SHA224_DIGEST_SIZE: 961 ctx->flags |= FLAGS_MODE_SHA224; 962 bs = SHA224_BLOCK_SIZE; 963 break; 964 case SHA256_DIGEST_SIZE: 965 ctx->flags |= FLAGS_MODE_SHA256; 966 bs = SHA256_BLOCK_SIZE; 967 break; 968 case SHA384_DIGEST_SIZE: 969 ctx->flags |= FLAGS_MODE_SHA384; 970 bs = SHA384_BLOCK_SIZE; 971 break; 972 case SHA512_DIGEST_SIZE: 973 ctx->flags |= FLAGS_MODE_SHA512; 974 bs = SHA512_BLOCK_SIZE; 975 break; 976 } 977 978 ctx->bufcnt = 0; 979 ctx->digcnt = 0; 980 ctx->total = 0; 981 ctx->offset = 0; 982 ctx->buflen = BUFLEN; 983 984 if (tctx->flags & BIT(FLAGS_HMAC)) { 985 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 986 struct omap_sham_hmac_ctx *bctx = tctx->base; 987 988 memcpy(ctx->buffer, bctx->ipad, bs); 989 ctx->bufcnt = bs; 990 } 991 992 ctx->flags |= BIT(FLAGS_HMAC); 993 } 994 995 return 0; 996 997 } 998 999 static int omap_sham_update_req(struct omap_sham_dev *dd) 1000 { 1001 struct ahash_request *req = dd->req; 1002 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1003 int err; 1004 bool final = ctx->flags & BIT(FLAGS_FINUP); 1005 1006 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", 1007 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); 1008 1009 if (ctx->total < get_block_size(ctx) || 1010 ctx->total < dd->fallback_sz) 1011 ctx->flags |= BIT(FLAGS_CPU); 1012 1013 if (ctx->flags & BIT(FLAGS_CPU)) 1014 err = omap_sham_xmit_cpu(dd, ctx->total, final); 1015 else 1016 err = omap_sham_xmit_dma(dd, ctx->total, final); 1017 1018 /* wait for dma completion before can take more data */ 1019 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 1020 1021 return err; 1022 } 1023 1024 static int omap_sham_final_req(struct omap_sham_dev *dd) 1025 { 1026 struct ahash_request *req = dd->req; 1027 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1028 int err = 0, use_dma = 1; 1029 1030 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) 1031 /* 1032 * faster to handle last block with cpu or 1033 * use cpu when dma is not present. 1034 */ 1035 use_dma = 0; 1036 1037 if (use_dma) 1038 err = omap_sham_xmit_dma(dd, ctx->total, 1); 1039 else 1040 err = omap_sham_xmit_cpu(dd, ctx->total, 1); 1041 1042 ctx->bufcnt = 0; 1043 1044 dev_dbg(dd->dev, "final_req: err: %d\n", err); 1045 1046 return err; 1047 } 1048 1049 static int omap_sham_finish_hmac(struct ahash_request *req) 1050 { 1051 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1052 struct omap_sham_hmac_ctx *bctx = tctx->base; 1053 int bs = crypto_shash_blocksize(bctx->shash); 1054 int ds = crypto_shash_digestsize(bctx->shash); 1055 SHASH_DESC_ON_STACK(shash, bctx->shash); 1056 1057 shash->tfm = bctx->shash; 1058 1059 return crypto_shash_init(shash) ?: 1060 crypto_shash_update(shash, bctx->opad, bs) ?: 1061 crypto_shash_finup(shash, req->result, ds, req->result); 1062 } 1063 1064 static int omap_sham_finish(struct ahash_request *req) 1065 { 1066 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1067 struct omap_sham_dev *dd = ctx->dd; 1068 int err = 0; 1069 1070 if (ctx->digcnt) { 1071 omap_sham_copy_ready_hash(req); 1072 if ((ctx->flags & BIT(FLAGS_HMAC)) && 1073 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 1074 err = omap_sham_finish_hmac(req); 1075 } 1076 1077 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 1078 1079 return err; 1080 } 1081 1082 static void omap_sham_finish_req(struct ahash_request *req, int err) 1083 { 1084 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1085 struct omap_sham_dev *dd = ctx->dd; 1086 1087 if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) 1088 free_pages((unsigned long)sg_virt(ctx->sg), 1089 get_order(ctx->sg->length + ctx->bufcnt)); 1090 1091 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) 1092 kfree(ctx->sg); 1093 1094 ctx->sg = NULL; 1095 1096 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); 1097 1098 if (!err) { 1099 dd->pdata->copy_hash(req, 1); 1100 if (test_bit(FLAGS_FINAL, &dd->flags)) 1101 err = omap_sham_finish(req); 1102 } else { 1103 ctx->flags |= BIT(FLAGS_ERROR); 1104 } 1105 1106 /* atomic operation is not needed here */ 1107 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1108 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1109 1110 pm_runtime_mark_last_busy(dd->dev); 1111 pm_runtime_put_autosuspend(dd->dev); 1112 1113 if (req->base.complete) 1114 req->base.complete(&req->base, err); 1115 } 1116 1117 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1118 struct ahash_request *req) 1119 { 1120 struct crypto_async_request *async_req, *backlog; 1121 struct omap_sham_reqctx *ctx; 1122 unsigned long flags; 1123 int err = 0, ret = 0; 1124 1125 retry: 1126 spin_lock_irqsave(&dd->lock, flags); 1127 if (req) 1128 ret = ahash_enqueue_request(&dd->queue, req); 1129 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1130 spin_unlock_irqrestore(&dd->lock, flags); 1131 return ret; 1132 } 1133 backlog = crypto_get_backlog(&dd->queue); 1134 async_req = crypto_dequeue_request(&dd->queue); 1135 if (async_req) 1136 set_bit(FLAGS_BUSY, &dd->flags); 1137 spin_unlock_irqrestore(&dd->lock, flags); 1138 1139 if (!async_req) 1140 return ret; 1141 1142 if (backlog) 1143 backlog->complete(backlog, -EINPROGRESS); 1144 1145 req = ahash_request_cast(async_req); 1146 dd->req = req; 1147 ctx = ahash_request_ctx(req); 1148 1149 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1150 if (err || !ctx->total) 1151 goto err1; 1152 1153 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1154 ctx->op, req->nbytes); 1155 1156 err = omap_sham_hw_init(dd); 1157 if (err) 1158 goto err1; 1159 1160 if (ctx->digcnt) 1161 /* request has changed - restore hash */ 1162 dd->pdata->copy_hash(req, 0); 1163 1164 if (ctx->op == OP_UPDATE) { 1165 err = omap_sham_update_req(dd); 1166 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1167 /* no final() after finup() */ 1168 err = omap_sham_final_req(dd); 1169 } else if (ctx->op == OP_FINAL) { 1170 err = omap_sham_final_req(dd); 1171 } 1172 err1: 1173 dev_dbg(dd->dev, "exit, err: %d\n", err); 1174 1175 if (err != -EINPROGRESS) { 1176 /* done_task will not finish it, so do it here */ 1177 omap_sham_finish_req(req, err); 1178 req = NULL; 1179 1180 /* 1181 * Execute next request immediately if there is anything 1182 * in queue. 1183 */ 1184 goto retry; 1185 } 1186 1187 return ret; 1188 } 1189 1190 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1191 { 1192 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1193 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1194 struct omap_sham_dev *dd = tctx->dd; 1195 1196 ctx->op = op; 1197 1198 return omap_sham_handle_queue(dd, req); 1199 } 1200 1201 static int omap_sham_update(struct ahash_request *req) 1202 { 1203 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1204 struct omap_sham_dev *dd = ctx->dd; 1205 1206 if (!req->nbytes) 1207 return 0; 1208 1209 if (ctx->bufcnt + req->nbytes <= ctx->buflen) { 1210 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1211 0, req->nbytes, 0); 1212 ctx->bufcnt += req->nbytes; 1213 return 0; 1214 } 1215 1216 if (dd->polling_mode) 1217 ctx->flags |= BIT(FLAGS_CPU); 1218 1219 return omap_sham_enqueue(req, OP_UPDATE); 1220 } 1221 1222 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags, 1223 const u8 *data, unsigned int len, u8 *out) 1224 { 1225 SHASH_DESC_ON_STACK(shash, tfm); 1226 1227 shash->tfm = tfm; 1228 1229 return crypto_shash_digest(shash, data, len, out); 1230 } 1231 1232 static int omap_sham_final_shash(struct ahash_request *req) 1233 { 1234 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1235 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1236 int offset = 0; 1237 1238 /* 1239 * If we are running HMAC on limited hardware support, skip 1240 * the ipad in the beginning of the buffer if we are going for 1241 * software fallback algorithm. 1242 */ 1243 if (test_bit(FLAGS_HMAC, &ctx->flags) && 1244 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) 1245 offset = get_block_size(ctx); 1246 1247 return omap_sham_shash_digest(tctx->fallback, req->base.flags, 1248 ctx->buffer + offset, 1249 ctx->bufcnt - offset, req->result); 1250 } 1251 1252 static int omap_sham_final(struct ahash_request *req) 1253 { 1254 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1255 1256 ctx->flags |= BIT(FLAGS_FINUP); 1257 1258 if (ctx->flags & BIT(FLAGS_ERROR)) 1259 return 0; /* uncompleted hash is not needed */ 1260 1261 /* 1262 * OMAP HW accel works only with buffers >= 9. 1263 * HMAC is always >= 9 because ipad == block size. 1264 * If buffersize is less than fallback_sz, we use fallback 1265 * SW encoding, as using DMA + HW in this case doesn't provide 1266 * any benefit. 1267 */ 1268 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) 1269 return omap_sham_final_shash(req); 1270 else if (ctx->bufcnt) 1271 return omap_sham_enqueue(req, OP_FINAL); 1272 1273 /* copy ready hash (+ finalize hmac) */ 1274 return omap_sham_finish(req); 1275 } 1276 1277 static int omap_sham_finup(struct ahash_request *req) 1278 { 1279 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1280 int err1, err2; 1281 1282 ctx->flags |= BIT(FLAGS_FINUP); 1283 1284 err1 = omap_sham_update(req); 1285 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1286 return err1; 1287 /* 1288 * final() has to be always called to cleanup resources 1289 * even if udpate() failed, except EINPROGRESS 1290 */ 1291 err2 = omap_sham_final(req); 1292 1293 return err1 ?: err2; 1294 } 1295 1296 static int omap_sham_digest(struct ahash_request *req) 1297 { 1298 return omap_sham_init(req) ?: omap_sham_finup(req); 1299 } 1300 1301 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1302 unsigned int keylen) 1303 { 1304 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1305 struct omap_sham_hmac_ctx *bctx = tctx->base; 1306 int bs = crypto_shash_blocksize(bctx->shash); 1307 int ds = crypto_shash_digestsize(bctx->shash); 1308 struct omap_sham_dev *dd = NULL, *tmp; 1309 int err, i; 1310 1311 spin_lock_bh(&sham.lock); 1312 if (!tctx->dd) { 1313 list_for_each_entry(tmp, &sham.dev_list, list) { 1314 dd = tmp; 1315 break; 1316 } 1317 tctx->dd = dd; 1318 } else { 1319 dd = tctx->dd; 1320 } 1321 spin_unlock_bh(&sham.lock); 1322 1323 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1324 if (err) 1325 return err; 1326 1327 if (keylen > bs) { 1328 err = omap_sham_shash_digest(bctx->shash, 1329 crypto_shash_get_flags(bctx->shash), 1330 key, keylen, bctx->ipad); 1331 if (err) 1332 return err; 1333 keylen = ds; 1334 } else { 1335 memcpy(bctx->ipad, key, keylen); 1336 } 1337 1338 memset(bctx->ipad + keylen, 0, bs - keylen); 1339 1340 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1341 memcpy(bctx->opad, bctx->ipad, bs); 1342 1343 for (i = 0; i < bs; i++) { 1344 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 1345 bctx->opad[i] ^= HMAC_OPAD_VALUE; 1346 } 1347 } 1348 1349 return err; 1350 } 1351 1352 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1353 { 1354 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1355 const char *alg_name = crypto_tfm_alg_name(tfm); 1356 1357 /* Allocate a fallback and abort if it failed. */ 1358 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1359 CRYPTO_ALG_NEED_FALLBACK); 1360 if (IS_ERR(tctx->fallback)) { 1361 pr_err("omap-sham: fallback driver '%s' " 1362 "could not be loaded.\n", alg_name); 1363 return PTR_ERR(tctx->fallback); 1364 } 1365 1366 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1367 sizeof(struct omap_sham_reqctx) + BUFLEN); 1368 1369 if (alg_base) { 1370 struct omap_sham_hmac_ctx *bctx = tctx->base; 1371 tctx->flags |= BIT(FLAGS_HMAC); 1372 bctx->shash = crypto_alloc_shash(alg_base, 0, 1373 CRYPTO_ALG_NEED_FALLBACK); 1374 if (IS_ERR(bctx->shash)) { 1375 pr_err("omap-sham: base driver '%s' " 1376 "could not be loaded.\n", alg_base); 1377 crypto_free_shash(tctx->fallback); 1378 return PTR_ERR(bctx->shash); 1379 } 1380 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1387 { 1388 return omap_sham_cra_init_alg(tfm, NULL); 1389 } 1390 1391 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1392 { 1393 return omap_sham_cra_init_alg(tfm, "sha1"); 1394 } 1395 1396 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1397 { 1398 return omap_sham_cra_init_alg(tfm, "sha224"); 1399 } 1400 1401 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1402 { 1403 return omap_sham_cra_init_alg(tfm, "sha256"); 1404 } 1405 1406 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1407 { 1408 return omap_sham_cra_init_alg(tfm, "md5"); 1409 } 1410 1411 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1412 { 1413 return omap_sham_cra_init_alg(tfm, "sha384"); 1414 } 1415 1416 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1417 { 1418 return omap_sham_cra_init_alg(tfm, "sha512"); 1419 } 1420 1421 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1422 { 1423 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1424 1425 crypto_free_shash(tctx->fallback); 1426 tctx->fallback = NULL; 1427 1428 if (tctx->flags & BIT(FLAGS_HMAC)) { 1429 struct omap_sham_hmac_ctx *bctx = tctx->base; 1430 crypto_free_shash(bctx->shash); 1431 } 1432 } 1433 1434 static int omap_sham_export(struct ahash_request *req, void *out) 1435 { 1436 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1437 1438 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); 1439 1440 return 0; 1441 } 1442 1443 static int omap_sham_import(struct ahash_request *req, const void *in) 1444 { 1445 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1446 const struct omap_sham_reqctx *ctx_in = in; 1447 1448 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); 1449 1450 return 0; 1451 } 1452 1453 static struct ahash_alg algs_sha1_md5[] = { 1454 { 1455 .init = omap_sham_init, 1456 .update = omap_sham_update, 1457 .final = omap_sham_final, 1458 .finup = omap_sham_finup, 1459 .digest = omap_sham_digest, 1460 .halg.digestsize = SHA1_DIGEST_SIZE, 1461 .halg.base = { 1462 .cra_name = "sha1", 1463 .cra_driver_name = "omap-sha1", 1464 .cra_priority = 400, 1465 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1466 CRYPTO_ALG_ASYNC | 1467 CRYPTO_ALG_NEED_FALLBACK, 1468 .cra_blocksize = SHA1_BLOCK_SIZE, 1469 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1470 .cra_alignmask = OMAP_ALIGN_MASK, 1471 .cra_module = THIS_MODULE, 1472 .cra_init = omap_sham_cra_init, 1473 .cra_exit = omap_sham_cra_exit, 1474 } 1475 }, 1476 { 1477 .init = omap_sham_init, 1478 .update = omap_sham_update, 1479 .final = omap_sham_final, 1480 .finup = omap_sham_finup, 1481 .digest = omap_sham_digest, 1482 .halg.digestsize = MD5_DIGEST_SIZE, 1483 .halg.base = { 1484 .cra_name = "md5", 1485 .cra_driver_name = "omap-md5", 1486 .cra_priority = 400, 1487 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1488 CRYPTO_ALG_ASYNC | 1489 CRYPTO_ALG_NEED_FALLBACK, 1490 .cra_blocksize = SHA1_BLOCK_SIZE, 1491 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1492 .cra_alignmask = OMAP_ALIGN_MASK, 1493 .cra_module = THIS_MODULE, 1494 .cra_init = omap_sham_cra_init, 1495 .cra_exit = omap_sham_cra_exit, 1496 } 1497 }, 1498 { 1499 .init = omap_sham_init, 1500 .update = omap_sham_update, 1501 .final = omap_sham_final, 1502 .finup = omap_sham_finup, 1503 .digest = omap_sham_digest, 1504 .setkey = omap_sham_setkey, 1505 .halg.digestsize = SHA1_DIGEST_SIZE, 1506 .halg.base = { 1507 .cra_name = "hmac(sha1)", 1508 .cra_driver_name = "omap-hmac-sha1", 1509 .cra_priority = 400, 1510 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1511 CRYPTO_ALG_ASYNC | 1512 CRYPTO_ALG_NEED_FALLBACK, 1513 .cra_blocksize = SHA1_BLOCK_SIZE, 1514 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1515 sizeof(struct omap_sham_hmac_ctx), 1516 .cra_alignmask = OMAP_ALIGN_MASK, 1517 .cra_module = THIS_MODULE, 1518 .cra_init = omap_sham_cra_sha1_init, 1519 .cra_exit = omap_sham_cra_exit, 1520 } 1521 }, 1522 { 1523 .init = omap_sham_init, 1524 .update = omap_sham_update, 1525 .final = omap_sham_final, 1526 .finup = omap_sham_finup, 1527 .digest = omap_sham_digest, 1528 .setkey = omap_sham_setkey, 1529 .halg.digestsize = MD5_DIGEST_SIZE, 1530 .halg.base = { 1531 .cra_name = "hmac(md5)", 1532 .cra_driver_name = "omap-hmac-md5", 1533 .cra_priority = 400, 1534 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1535 CRYPTO_ALG_ASYNC | 1536 CRYPTO_ALG_NEED_FALLBACK, 1537 .cra_blocksize = SHA1_BLOCK_SIZE, 1538 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1539 sizeof(struct omap_sham_hmac_ctx), 1540 .cra_alignmask = OMAP_ALIGN_MASK, 1541 .cra_module = THIS_MODULE, 1542 .cra_init = omap_sham_cra_md5_init, 1543 .cra_exit = omap_sham_cra_exit, 1544 } 1545 } 1546 }; 1547 1548 /* OMAP4 has some algs in addition to what OMAP2 has */ 1549 static struct ahash_alg algs_sha224_sha256[] = { 1550 { 1551 .init = omap_sham_init, 1552 .update = omap_sham_update, 1553 .final = omap_sham_final, 1554 .finup = omap_sham_finup, 1555 .digest = omap_sham_digest, 1556 .halg.digestsize = SHA224_DIGEST_SIZE, 1557 .halg.base = { 1558 .cra_name = "sha224", 1559 .cra_driver_name = "omap-sha224", 1560 .cra_priority = 400, 1561 .cra_flags = CRYPTO_ALG_ASYNC | 1562 CRYPTO_ALG_NEED_FALLBACK, 1563 .cra_blocksize = SHA224_BLOCK_SIZE, 1564 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1565 .cra_alignmask = OMAP_ALIGN_MASK, 1566 .cra_module = THIS_MODULE, 1567 .cra_init = omap_sham_cra_init, 1568 .cra_exit = omap_sham_cra_exit, 1569 } 1570 }, 1571 { 1572 .init = omap_sham_init, 1573 .update = omap_sham_update, 1574 .final = omap_sham_final, 1575 .finup = omap_sham_finup, 1576 .digest = omap_sham_digest, 1577 .halg.digestsize = SHA256_DIGEST_SIZE, 1578 .halg.base = { 1579 .cra_name = "sha256", 1580 .cra_driver_name = "omap-sha256", 1581 .cra_priority = 400, 1582 .cra_flags = CRYPTO_ALG_ASYNC | 1583 CRYPTO_ALG_NEED_FALLBACK, 1584 .cra_blocksize = SHA256_BLOCK_SIZE, 1585 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1586 .cra_alignmask = OMAP_ALIGN_MASK, 1587 .cra_module = THIS_MODULE, 1588 .cra_init = omap_sham_cra_init, 1589 .cra_exit = omap_sham_cra_exit, 1590 } 1591 }, 1592 { 1593 .init = omap_sham_init, 1594 .update = omap_sham_update, 1595 .final = omap_sham_final, 1596 .finup = omap_sham_finup, 1597 .digest = omap_sham_digest, 1598 .setkey = omap_sham_setkey, 1599 .halg.digestsize = SHA224_DIGEST_SIZE, 1600 .halg.base = { 1601 .cra_name = "hmac(sha224)", 1602 .cra_driver_name = "omap-hmac-sha224", 1603 .cra_priority = 400, 1604 .cra_flags = CRYPTO_ALG_ASYNC | 1605 CRYPTO_ALG_NEED_FALLBACK, 1606 .cra_blocksize = SHA224_BLOCK_SIZE, 1607 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1608 sizeof(struct omap_sham_hmac_ctx), 1609 .cra_alignmask = OMAP_ALIGN_MASK, 1610 .cra_module = THIS_MODULE, 1611 .cra_init = omap_sham_cra_sha224_init, 1612 .cra_exit = omap_sham_cra_exit, 1613 } 1614 }, 1615 { 1616 .init = omap_sham_init, 1617 .update = omap_sham_update, 1618 .final = omap_sham_final, 1619 .finup = omap_sham_finup, 1620 .digest = omap_sham_digest, 1621 .setkey = omap_sham_setkey, 1622 .halg.digestsize = SHA256_DIGEST_SIZE, 1623 .halg.base = { 1624 .cra_name = "hmac(sha256)", 1625 .cra_driver_name = "omap-hmac-sha256", 1626 .cra_priority = 400, 1627 .cra_flags = CRYPTO_ALG_ASYNC | 1628 CRYPTO_ALG_NEED_FALLBACK, 1629 .cra_blocksize = SHA256_BLOCK_SIZE, 1630 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1631 sizeof(struct omap_sham_hmac_ctx), 1632 .cra_alignmask = OMAP_ALIGN_MASK, 1633 .cra_module = THIS_MODULE, 1634 .cra_init = omap_sham_cra_sha256_init, 1635 .cra_exit = omap_sham_cra_exit, 1636 } 1637 }, 1638 }; 1639 1640 static struct ahash_alg algs_sha384_sha512[] = { 1641 { 1642 .init = omap_sham_init, 1643 .update = omap_sham_update, 1644 .final = omap_sham_final, 1645 .finup = omap_sham_finup, 1646 .digest = omap_sham_digest, 1647 .halg.digestsize = SHA384_DIGEST_SIZE, 1648 .halg.base = { 1649 .cra_name = "sha384", 1650 .cra_driver_name = "omap-sha384", 1651 .cra_priority = 400, 1652 .cra_flags = CRYPTO_ALG_ASYNC | 1653 CRYPTO_ALG_NEED_FALLBACK, 1654 .cra_blocksize = SHA384_BLOCK_SIZE, 1655 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1656 .cra_alignmask = OMAP_ALIGN_MASK, 1657 .cra_module = THIS_MODULE, 1658 .cra_init = omap_sham_cra_init, 1659 .cra_exit = omap_sham_cra_exit, 1660 } 1661 }, 1662 { 1663 .init = omap_sham_init, 1664 .update = omap_sham_update, 1665 .final = omap_sham_final, 1666 .finup = omap_sham_finup, 1667 .digest = omap_sham_digest, 1668 .halg.digestsize = SHA512_DIGEST_SIZE, 1669 .halg.base = { 1670 .cra_name = "sha512", 1671 .cra_driver_name = "omap-sha512", 1672 .cra_priority = 400, 1673 .cra_flags = CRYPTO_ALG_ASYNC | 1674 CRYPTO_ALG_NEED_FALLBACK, 1675 .cra_blocksize = SHA512_BLOCK_SIZE, 1676 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1677 .cra_alignmask = OMAP_ALIGN_MASK, 1678 .cra_module = THIS_MODULE, 1679 .cra_init = omap_sham_cra_init, 1680 .cra_exit = omap_sham_cra_exit, 1681 } 1682 }, 1683 { 1684 .init = omap_sham_init, 1685 .update = omap_sham_update, 1686 .final = omap_sham_final, 1687 .finup = omap_sham_finup, 1688 .digest = omap_sham_digest, 1689 .setkey = omap_sham_setkey, 1690 .halg.digestsize = SHA384_DIGEST_SIZE, 1691 .halg.base = { 1692 .cra_name = "hmac(sha384)", 1693 .cra_driver_name = "omap-hmac-sha384", 1694 .cra_priority = 400, 1695 .cra_flags = CRYPTO_ALG_ASYNC | 1696 CRYPTO_ALG_NEED_FALLBACK, 1697 .cra_blocksize = SHA384_BLOCK_SIZE, 1698 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1699 sizeof(struct omap_sham_hmac_ctx), 1700 .cra_alignmask = OMAP_ALIGN_MASK, 1701 .cra_module = THIS_MODULE, 1702 .cra_init = omap_sham_cra_sha384_init, 1703 .cra_exit = omap_sham_cra_exit, 1704 } 1705 }, 1706 { 1707 .init = omap_sham_init, 1708 .update = omap_sham_update, 1709 .final = omap_sham_final, 1710 .finup = omap_sham_finup, 1711 .digest = omap_sham_digest, 1712 .setkey = omap_sham_setkey, 1713 .halg.digestsize = SHA512_DIGEST_SIZE, 1714 .halg.base = { 1715 .cra_name = "hmac(sha512)", 1716 .cra_driver_name = "omap-hmac-sha512", 1717 .cra_priority = 400, 1718 .cra_flags = CRYPTO_ALG_ASYNC | 1719 CRYPTO_ALG_NEED_FALLBACK, 1720 .cra_blocksize = SHA512_BLOCK_SIZE, 1721 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1722 sizeof(struct omap_sham_hmac_ctx), 1723 .cra_alignmask = OMAP_ALIGN_MASK, 1724 .cra_module = THIS_MODULE, 1725 .cra_init = omap_sham_cra_sha512_init, 1726 .cra_exit = omap_sham_cra_exit, 1727 } 1728 }, 1729 }; 1730 1731 static void omap_sham_done_task(unsigned long data) 1732 { 1733 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1734 int err = 0; 1735 1736 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1737 omap_sham_handle_queue(dd, NULL); 1738 return; 1739 } 1740 1741 if (test_bit(FLAGS_CPU, &dd->flags)) { 1742 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) 1743 goto finish; 1744 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1745 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1746 omap_sham_update_dma_stop(dd); 1747 if (dd->err) { 1748 err = dd->err; 1749 goto finish; 1750 } 1751 } 1752 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1753 /* hash or semi-hash ready */ 1754 clear_bit(FLAGS_DMA_READY, &dd->flags); 1755 goto finish; 1756 } 1757 } 1758 1759 return; 1760 1761 finish: 1762 dev_dbg(dd->dev, "update done: err: %d\n", err); 1763 /* finish curent request */ 1764 omap_sham_finish_req(dd->req, err); 1765 1766 /* If we are not busy, process next req */ 1767 if (!test_bit(FLAGS_BUSY, &dd->flags)) 1768 omap_sham_handle_queue(dd, NULL); 1769 } 1770 1771 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1772 { 1773 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1774 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1775 } else { 1776 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1777 tasklet_schedule(&dd->done_task); 1778 } 1779 1780 return IRQ_HANDLED; 1781 } 1782 1783 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1784 { 1785 struct omap_sham_dev *dd = dev_id; 1786 1787 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1788 /* final -> allow device to go to power-saving mode */ 1789 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1790 1791 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1792 SHA_REG_CTRL_OUTPUT_READY); 1793 omap_sham_read(dd, SHA_REG_CTRL); 1794 1795 return omap_sham_irq_common(dd); 1796 } 1797 1798 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1799 { 1800 struct omap_sham_dev *dd = dev_id; 1801 1802 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1803 1804 return omap_sham_irq_common(dd); 1805 } 1806 1807 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1808 { 1809 .algs_list = algs_sha1_md5, 1810 .size = ARRAY_SIZE(algs_sha1_md5), 1811 }, 1812 }; 1813 1814 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1815 .algs_info = omap_sham_algs_info_omap2, 1816 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1817 .flags = BIT(FLAGS_BE32_SHA1), 1818 .digest_size = SHA1_DIGEST_SIZE, 1819 .copy_hash = omap_sham_copy_hash_omap2, 1820 .write_ctrl = omap_sham_write_ctrl_omap2, 1821 .trigger = omap_sham_trigger_omap2, 1822 .poll_irq = omap_sham_poll_irq_omap2, 1823 .intr_hdlr = omap_sham_irq_omap2, 1824 .idigest_ofs = 0x00, 1825 .din_ofs = 0x1c, 1826 .digcnt_ofs = 0x14, 1827 .rev_ofs = 0x5c, 1828 .mask_ofs = 0x60, 1829 .sysstatus_ofs = 0x64, 1830 .major_mask = 0xf0, 1831 .major_shift = 4, 1832 .minor_mask = 0x0f, 1833 .minor_shift = 0, 1834 }; 1835 1836 #ifdef CONFIG_OF 1837 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1838 { 1839 .algs_list = algs_sha1_md5, 1840 .size = ARRAY_SIZE(algs_sha1_md5), 1841 }, 1842 { 1843 .algs_list = algs_sha224_sha256, 1844 .size = ARRAY_SIZE(algs_sha224_sha256), 1845 }, 1846 }; 1847 1848 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1849 .algs_info = omap_sham_algs_info_omap4, 1850 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1851 .flags = BIT(FLAGS_AUTO_XOR), 1852 .digest_size = SHA256_DIGEST_SIZE, 1853 .copy_hash = omap_sham_copy_hash_omap4, 1854 .write_ctrl = omap_sham_write_ctrl_omap4, 1855 .trigger = omap_sham_trigger_omap4, 1856 .poll_irq = omap_sham_poll_irq_omap4, 1857 .intr_hdlr = omap_sham_irq_omap4, 1858 .idigest_ofs = 0x020, 1859 .odigest_ofs = 0x0, 1860 .din_ofs = 0x080, 1861 .digcnt_ofs = 0x040, 1862 .rev_ofs = 0x100, 1863 .mask_ofs = 0x110, 1864 .sysstatus_ofs = 0x114, 1865 .mode_ofs = 0x44, 1866 .length_ofs = 0x48, 1867 .major_mask = 0x0700, 1868 .major_shift = 8, 1869 .minor_mask = 0x003f, 1870 .minor_shift = 0, 1871 }; 1872 1873 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1874 { 1875 .algs_list = algs_sha1_md5, 1876 .size = ARRAY_SIZE(algs_sha1_md5), 1877 }, 1878 { 1879 .algs_list = algs_sha224_sha256, 1880 .size = ARRAY_SIZE(algs_sha224_sha256), 1881 }, 1882 { 1883 .algs_list = algs_sha384_sha512, 1884 .size = ARRAY_SIZE(algs_sha384_sha512), 1885 }, 1886 }; 1887 1888 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1889 .algs_info = omap_sham_algs_info_omap5, 1890 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1891 .flags = BIT(FLAGS_AUTO_XOR), 1892 .digest_size = SHA512_DIGEST_SIZE, 1893 .copy_hash = omap_sham_copy_hash_omap4, 1894 .write_ctrl = omap_sham_write_ctrl_omap4, 1895 .trigger = omap_sham_trigger_omap4, 1896 .poll_irq = omap_sham_poll_irq_omap4, 1897 .intr_hdlr = omap_sham_irq_omap4, 1898 .idigest_ofs = 0x240, 1899 .odigest_ofs = 0x200, 1900 .din_ofs = 0x080, 1901 .digcnt_ofs = 0x280, 1902 .rev_ofs = 0x100, 1903 .mask_ofs = 0x110, 1904 .sysstatus_ofs = 0x114, 1905 .mode_ofs = 0x284, 1906 .length_ofs = 0x288, 1907 .major_mask = 0x0700, 1908 .major_shift = 8, 1909 .minor_mask = 0x003f, 1910 .minor_shift = 0, 1911 }; 1912 1913 static const struct of_device_id omap_sham_of_match[] = { 1914 { 1915 .compatible = "ti,omap2-sham", 1916 .data = &omap_sham_pdata_omap2, 1917 }, 1918 { 1919 .compatible = "ti,omap3-sham", 1920 .data = &omap_sham_pdata_omap2, 1921 }, 1922 { 1923 .compatible = "ti,omap4-sham", 1924 .data = &omap_sham_pdata_omap4, 1925 }, 1926 { 1927 .compatible = "ti,omap5-sham", 1928 .data = &omap_sham_pdata_omap5, 1929 }, 1930 {}, 1931 }; 1932 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1933 1934 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1935 struct device *dev, struct resource *res) 1936 { 1937 struct device_node *node = dev->of_node; 1938 int err = 0; 1939 1940 dd->pdata = of_device_get_match_data(dev); 1941 if (!dd->pdata) { 1942 dev_err(dev, "no compatible OF match\n"); 1943 err = -EINVAL; 1944 goto err; 1945 } 1946 1947 err = of_address_to_resource(node, 0, res); 1948 if (err < 0) { 1949 dev_err(dev, "can't translate OF node address\n"); 1950 err = -EINVAL; 1951 goto err; 1952 } 1953 1954 dd->irq = irq_of_parse_and_map(node, 0); 1955 if (!dd->irq) { 1956 dev_err(dev, "can't translate OF irq value\n"); 1957 err = -EINVAL; 1958 goto err; 1959 } 1960 1961 err: 1962 return err; 1963 } 1964 #else 1965 static const struct of_device_id omap_sham_of_match[] = { 1966 {}, 1967 }; 1968 1969 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1970 struct device *dev, struct resource *res) 1971 { 1972 return -EINVAL; 1973 } 1974 #endif 1975 1976 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 1977 struct platform_device *pdev, struct resource *res) 1978 { 1979 struct device *dev = &pdev->dev; 1980 struct resource *r; 1981 int err = 0; 1982 1983 /* Get the base address */ 1984 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1985 if (!r) { 1986 dev_err(dev, "no MEM resource info\n"); 1987 err = -ENODEV; 1988 goto err; 1989 } 1990 memcpy(res, r, sizeof(*res)); 1991 1992 /* Get the IRQ */ 1993 dd->irq = platform_get_irq(pdev, 0); 1994 if (dd->irq < 0) { 1995 dev_err(dev, "no IRQ resource info\n"); 1996 err = dd->irq; 1997 goto err; 1998 } 1999 2000 /* Only OMAP2/3 can be non-DT */ 2001 dd->pdata = &omap_sham_pdata_omap2; 2002 2003 err: 2004 return err; 2005 } 2006 2007 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 2008 char *buf) 2009 { 2010 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2011 2012 return sprintf(buf, "%d\n", dd->fallback_sz); 2013 } 2014 2015 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 2016 const char *buf, size_t size) 2017 { 2018 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2019 ssize_t status; 2020 long value; 2021 2022 status = kstrtol(buf, 0, &value); 2023 if (status) 2024 return status; 2025 2026 /* HW accelerator only works with buffers > 9 */ 2027 if (value < 9) { 2028 dev_err(dev, "minimum fallback size 9\n"); 2029 return -EINVAL; 2030 } 2031 2032 dd->fallback_sz = value; 2033 2034 return size; 2035 } 2036 2037 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 2038 char *buf) 2039 { 2040 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2041 2042 return sprintf(buf, "%d\n", dd->queue.max_qlen); 2043 } 2044 2045 static ssize_t queue_len_store(struct device *dev, 2046 struct device_attribute *attr, const char *buf, 2047 size_t size) 2048 { 2049 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2050 ssize_t status; 2051 long value; 2052 unsigned long flags; 2053 2054 status = kstrtol(buf, 0, &value); 2055 if (status) 2056 return status; 2057 2058 if (value < 1) 2059 return -EINVAL; 2060 2061 /* 2062 * Changing the queue size in fly is safe, if size becomes smaller 2063 * than current size, it will just not accept new entries until 2064 * it has shrank enough. 2065 */ 2066 spin_lock_irqsave(&dd->lock, flags); 2067 dd->queue.max_qlen = value; 2068 spin_unlock_irqrestore(&dd->lock, flags); 2069 2070 return size; 2071 } 2072 2073 static DEVICE_ATTR_RW(queue_len); 2074 static DEVICE_ATTR_RW(fallback); 2075 2076 static struct attribute *omap_sham_attrs[] = { 2077 &dev_attr_queue_len.attr, 2078 &dev_attr_fallback.attr, 2079 NULL, 2080 }; 2081 2082 static struct attribute_group omap_sham_attr_group = { 2083 .attrs = omap_sham_attrs, 2084 }; 2085 2086 static int omap_sham_probe(struct platform_device *pdev) 2087 { 2088 struct omap_sham_dev *dd; 2089 struct device *dev = &pdev->dev; 2090 struct resource res; 2091 dma_cap_mask_t mask; 2092 int err, i, j; 2093 u32 rev; 2094 2095 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 2096 if (dd == NULL) { 2097 dev_err(dev, "unable to alloc data struct.\n"); 2098 err = -ENOMEM; 2099 goto data_err; 2100 } 2101 dd->dev = dev; 2102 platform_set_drvdata(pdev, dd); 2103 2104 INIT_LIST_HEAD(&dd->list); 2105 spin_lock_init(&dd->lock); 2106 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 2107 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 2108 2109 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 2110 omap_sham_get_res_pdev(dd, pdev, &res); 2111 if (err) 2112 goto data_err; 2113 2114 dd->io_base = devm_ioremap_resource(dev, &res); 2115 if (IS_ERR(dd->io_base)) { 2116 err = PTR_ERR(dd->io_base); 2117 goto data_err; 2118 } 2119 dd->phys_base = res.start; 2120 2121 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 2122 IRQF_TRIGGER_NONE, dev_name(dev), dd); 2123 if (err) { 2124 dev_err(dev, "unable to request irq %d, err = %d\n", 2125 dd->irq, err); 2126 goto data_err; 2127 } 2128 2129 dma_cap_zero(mask); 2130 dma_cap_set(DMA_SLAVE, mask); 2131 2132 dd->dma_lch = dma_request_chan(dev, "rx"); 2133 if (IS_ERR(dd->dma_lch)) { 2134 err = PTR_ERR(dd->dma_lch); 2135 if (err == -EPROBE_DEFER) 2136 goto data_err; 2137 2138 dd->polling_mode = 1; 2139 dev_dbg(dev, "using polling mode instead of dma\n"); 2140 } 2141 2142 dd->flags |= dd->pdata->flags; 2143 2144 pm_runtime_use_autosuspend(dev); 2145 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 2146 2147 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; 2148 2149 pm_runtime_enable(dev); 2150 pm_runtime_irq_safe(dev); 2151 2152 err = pm_runtime_get_sync(dev); 2153 if (err < 0) { 2154 dev_err(dev, "failed to get sync: %d\n", err); 2155 goto err_pm; 2156 } 2157 2158 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 2159 pm_runtime_put_sync(&pdev->dev); 2160 2161 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 2162 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 2163 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 2164 2165 spin_lock(&sham.lock); 2166 list_add_tail(&dd->list, &sham.dev_list); 2167 spin_unlock(&sham.lock); 2168 2169 for (i = 0; i < dd->pdata->algs_info_size; i++) { 2170 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2171 struct ahash_alg *alg; 2172 2173 alg = &dd->pdata->algs_info[i].algs_list[j]; 2174 alg->export = omap_sham_export; 2175 alg->import = omap_sham_import; 2176 alg->halg.statesize = sizeof(struct omap_sham_reqctx) + 2177 BUFLEN; 2178 err = crypto_register_ahash(alg); 2179 if (err) 2180 goto err_algs; 2181 2182 dd->pdata->algs_info[i].registered++; 2183 } 2184 } 2185 2186 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); 2187 if (err) { 2188 dev_err(dev, "could not create sysfs device attrs\n"); 2189 goto err_algs; 2190 } 2191 2192 return 0; 2193 2194 err_algs: 2195 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2196 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2197 crypto_unregister_ahash( 2198 &dd->pdata->algs_info[i].algs_list[j]); 2199 err_pm: 2200 pm_runtime_disable(dev); 2201 if (!dd->polling_mode) 2202 dma_release_channel(dd->dma_lch); 2203 data_err: 2204 dev_err(dev, "initialization failed.\n"); 2205 2206 return err; 2207 } 2208 2209 static int omap_sham_remove(struct platform_device *pdev) 2210 { 2211 struct omap_sham_dev *dd; 2212 int i, j; 2213 2214 dd = platform_get_drvdata(pdev); 2215 if (!dd) 2216 return -ENODEV; 2217 spin_lock(&sham.lock); 2218 list_del(&dd->list); 2219 spin_unlock(&sham.lock); 2220 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2221 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2222 crypto_unregister_ahash( 2223 &dd->pdata->algs_info[i].algs_list[j]); 2224 tasklet_kill(&dd->done_task); 2225 pm_runtime_disable(&pdev->dev); 2226 2227 if (!dd->polling_mode) 2228 dma_release_channel(dd->dma_lch); 2229 2230 return 0; 2231 } 2232 2233 #ifdef CONFIG_PM_SLEEP 2234 static int omap_sham_suspend(struct device *dev) 2235 { 2236 pm_runtime_put_sync(dev); 2237 return 0; 2238 } 2239 2240 static int omap_sham_resume(struct device *dev) 2241 { 2242 int err = pm_runtime_get_sync(dev); 2243 if (err < 0) { 2244 dev_err(dev, "failed to get sync: %d\n", err); 2245 return err; 2246 } 2247 return 0; 2248 } 2249 #endif 2250 2251 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2252 2253 static struct platform_driver omap_sham_driver = { 2254 .probe = omap_sham_probe, 2255 .remove = omap_sham_remove, 2256 .driver = { 2257 .name = "omap-sham", 2258 .pm = &omap_sham_pm_ops, 2259 .of_match_table = omap_sham_of_match, 2260 }, 2261 }; 2262 2263 module_platform_driver(omap_sham_driver); 2264 2265 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2266 MODULE_LICENSE("GPL v2"); 2267 MODULE_AUTHOR("Dmitry Kasatkin"); 2268 MODULE_ALIAS("platform:omap-sham"); 2269