1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 */ 11 12 #define pr_fmt(fmt) "%20s: " fmt, __func__ 13 #define prn(num) pr_debug(#num "=%d\n", num) 14 #define prx(num) pr_debug(#num "=%x\n", num) 15 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/errno.h> 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/scatterlist.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_address.h> 29 #include <linux/io.h> 30 #include <linux/crypto.h> 31 #include <linux/interrupt.h> 32 #include <crypto/scatterwalk.h> 33 #include <crypto/aes.h> 34 #include <crypto/gcm.h> 35 #include <crypto/engine.h> 36 #include <crypto/internal/skcipher.h> 37 #include <crypto/internal/aead.h> 38 39 #include "omap-crypto.h" 40 #include "omap-aes.h" 41 42 /* keep registered devices data here */ 43 static LIST_HEAD(dev_list); 44 static DEFINE_SPINLOCK(list_lock); 45 46 static int aes_fallback_sz = 200; 47 48 #ifdef DEBUG 49 #define omap_aes_read(dd, offset) \ 50 ({ \ 51 int _read_ret; \ 52 _read_ret = __raw_readl(dd->io_base + offset); \ 53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 54 offset, _read_ret); \ 55 _read_ret; \ 56 }) 57 #else 58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 59 { 60 return __raw_readl(dd->io_base + offset); 61 } 62 #endif 63 64 #ifdef DEBUG 65 #define omap_aes_write(dd, offset, value) \ 66 do { \ 67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 68 offset, value); \ 69 __raw_writel(value, dd->io_base + offset); \ 70 } while (0) 71 #else 72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 73 u32 value) 74 { 75 __raw_writel(value, dd->io_base + offset); 76 } 77 #endif 78 79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 80 u32 value, u32 mask) 81 { 82 u32 val; 83 84 val = omap_aes_read(dd, offset); 85 val &= ~mask; 86 val |= value; 87 omap_aes_write(dd, offset, val); 88 } 89 90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 91 u32 *value, int count) 92 { 93 for (; count--; value++, offset += 4) 94 omap_aes_write(dd, offset, *value); 95 } 96 97 static int omap_aes_hw_init(struct omap_aes_dev *dd) 98 { 99 int err; 100 101 if (!(dd->flags & FLAGS_INIT)) { 102 dd->flags |= FLAGS_INIT; 103 dd->err = 0; 104 } 105 106 err = pm_runtime_get_sync(dd->dev); 107 if (err < 0) { 108 dev_err(dd->dev, "failed to get sync: %d\n", err); 109 return err; 110 } 111 112 return 0; 113 } 114 115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 116 { 117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 120 } 121 122 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 123 { 124 struct omap_aes_reqctx *rctx; 125 unsigned int key32; 126 int i, err; 127 u32 val; 128 129 err = omap_aes_hw_init(dd); 130 if (err) 131 return err; 132 133 key32 = dd->ctx->keylen / sizeof(u32); 134 135 /* RESET the key as previous HASH keys should not get affected*/ 136 if (dd->flags & FLAGS_GCM) 137 for (i = 0; i < 0x40; i = i + 4) 138 omap_aes_write(dd, i, 0x0); 139 140 for (i = 0; i < key32; i++) { 141 omap_aes_write(dd, AES_REG_KEY(dd, i), 142 __le32_to_cpu(dd->ctx->key[i])); 143 } 144 145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) 146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4); 147 148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 149 rctx = aead_request_ctx(dd->aead_req); 150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 151 } 152 153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 154 if (dd->flags & FLAGS_CBC) 155 val |= AES_REG_CTRL_CBC; 156 157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 159 160 if (dd->flags & FLAGS_GCM) 161 val |= AES_REG_CTRL_GCM; 162 163 if (dd->flags & FLAGS_ENCRYPT) 164 val |= AES_REG_CTRL_DIRECTION; 165 166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 167 168 return 0; 169 } 170 171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 172 { 173 u32 mask, val; 174 175 val = dd->pdata->dma_start; 176 177 if (dd->dma_lch_out != NULL) 178 val |= dd->pdata->dma_enable_out; 179 if (dd->dma_lch_in != NULL) 180 val |= dd->pdata->dma_enable_in; 181 182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 183 dd->pdata->dma_start; 184 185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 186 187 } 188 189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 190 { 191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 193 if (dd->flags & FLAGS_GCM) 194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 195 196 omap_aes_dma_trigger_omap2(dd, length); 197 } 198 199 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 200 { 201 u32 mask; 202 203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 204 dd->pdata->dma_start; 205 206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 207 } 208 209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 210 { 211 struct omap_aes_dev *dd; 212 213 spin_lock_bh(&list_lock); 214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 215 list_move_tail(&dd->list, &dev_list); 216 rctx->dd = dd; 217 spin_unlock_bh(&list_lock); 218 219 return dd; 220 } 221 222 static void omap_aes_dma_out_callback(void *data) 223 { 224 struct omap_aes_dev *dd = data; 225 226 /* dma_lch_out - completed */ 227 tasklet_schedule(&dd->done_task); 228 } 229 230 static int omap_aes_dma_init(struct omap_aes_dev *dd) 231 { 232 int err; 233 234 dd->dma_lch_out = NULL; 235 dd->dma_lch_in = NULL; 236 237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 238 if (IS_ERR(dd->dma_lch_in)) { 239 dev_err(dd->dev, "Unable to request in DMA channel\n"); 240 return PTR_ERR(dd->dma_lch_in); 241 } 242 243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 244 if (IS_ERR(dd->dma_lch_out)) { 245 dev_err(dd->dev, "Unable to request out DMA channel\n"); 246 err = PTR_ERR(dd->dma_lch_out); 247 goto err_dma_out; 248 } 249 250 return 0; 251 252 err_dma_out: 253 dma_release_channel(dd->dma_lch_in); 254 255 return err; 256 } 257 258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 259 { 260 if (dd->pio_only) 261 return; 262 263 dma_release_channel(dd->dma_lch_out); 264 dma_release_channel(dd->dma_lch_in); 265 } 266 267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 268 struct scatterlist *in_sg, 269 struct scatterlist *out_sg, 270 int in_sg_len, int out_sg_len) 271 { 272 struct dma_async_tx_descriptor *tx_in, *tx_out; 273 struct dma_slave_config cfg; 274 int ret; 275 276 if (dd->pio_only) { 277 scatterwalk_start(&dd->in_walk, dd->in_sg); 278 scatterwalk_start(&dd->out_walk, dd->out_sg); 279 280 /* Enable DATAIN interrupt and let it take 281 care of the rest */ 282 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 283 return 0; 284 } 285 286 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 287 288 memset(&cfg, 0, sizeof(cfg)); 289 290 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 291 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 292 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 293 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 294 cfg.src_maxburst = DST_MAXBURST; 295 cfg.dst_maxburst = DST_MAXBURST; 296 297 /* IN */ 298 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 299 if (ret) { 300 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 301 ret); 302 return ret; 303 } 304 305 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 306 DMA_MEM_TO_DEV, 307 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 308 if (!tx_in) { 309 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 310 return -EINVAL; 311 } 312 313 /* No callback necessary */ 314 tx_in->callback_param = dd; 315 316 /* OUT */ 317 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 318 if (ret) { 319 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 320 ret); 321 return ret; 322 } 323 324 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 325 DMA_DEV_TO_MEM, 326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 327 if (!tx_out) { 328 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 329 return -EINVAL; 330 } 331 332 if (dd->flags & FLAGS_GCM) 333 tx_out->callback = omap_aes_gcm_dma_out_callback; 334 else 335 tx_out->callback = omap_aes_dma_out_callback; 336 tx_out->callback_param = dd; 337 338 dmaengine_submit(tx_in); 339 dmaengine_submit(tx_out); 340 341 dma_async_issue_pending(dd->dma_lch_in); 342 dma_async_issue_pending(dd->dma_lch_out); 343 344 /* start DMA */ 345 dd->pdata->trigger(dd, dd->total); 346 347 return 0; 348 } 349 350 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 351 { 352 int err; 353 354 pr_debug("total: %d\n", dd->total); 355 356 if (!dd->pio_only) { 357 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 358 DMA_TO_DEVICE); 359 if (!err) { 360 dev_err(dd->dev, "dma_map_sg() error\n"); 361 return -EINVAL; 362 } 363 364 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 365 DMA_FROM_DEVICE); 366 if (!err) { 367 dev_err(dd->dev, "dma_map_sg() error\n"); 368 return -EINVAL; 369 } 370 } 371 372 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 373 dd->out_sg_len); 374 if (err && !dd->pio_only) { 375 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 376 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 377 DMA_FROM_DEVICE); 378 } 379 380 return err; 381 } 382 383 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 384 { 385 struct skcipher_request *req = dd->req; 386 387 pr_debug("err: %d\n", err); 388 389 crypto_finalize_skcipher_request(dd->engine, req, err); 390 391 pm_runtime_mark_last_busy(dd->dev); 392 pm_runtime_put_autosuspend(dd->dev); 393 } 394 395 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 396 { 397 pr_debug("total: %d\n", dd->total); 398 399 omap_aes_dma_stop(dd); 400 401 402 return 0; 403 } 404 405 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 406 struct skcipher_request *req) 407 { 408 if (req) 409 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 410 411 return 0; 412 } 413 414 static int omap_aes_prepare_req(struct crypto_engine *engine, 415 void *areq) 416 { 417 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 418 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 419 crypto_skcipher_reqtfm(req)); 420 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 421 struct omap_aes_dev *dd = rctx->dd; 422 int ret; 423 u16 flags; 424 425 if (!dd) 426 return -ENODEV; 427 428 /* assign new request to device */ 429 dd->req = req; 430 dd->total = req->cryptlen; 431 dd->total_save = req->cryptlen; 432 dd->in_sg = req->src; 433 dd->out_sg = req->dst; 434 dd->orig_out = req->dst; 435 436 flags = OMAP_CRYPTO_COPY_DATA; 437 if (req->src == req->dst) 438 flags |= OMAP_CRYPTO_FORCE_COPY; 439 440 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 441 dd->in_sgl, flags, 442 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 443 if (ret) 444 return ret; 445 446 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 447 &dd->out_sgl, 0, 448 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 449 if (ret) 450 return ret; 451 452 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 453 if (dd->in_sg_len < 0) 454 return dd->in_sg_len; 455 456 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 457 if (dd->out_sg_len < 0) 458 return dd->out_sg_len; 459 460 rctx->mode &= FLAGS_MODE_MASK; 461 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 462 463 dd->ctx = ctx; 464 rctx->dd = dd; 465 466 return omap_aes_write_ctrl(dd); 467 } 468 469 static int omap_aes_crypt_req(struct crypto_engine *engine, 470 void *areq) 471 { 472 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 473 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 474 struct omap_aes_dev *dd = rctx->dd; 475 476 if (!dd) 477 return -ENODEV; 478 479 return omap_aes_crypt_dma_start(dd); 480 } 481 482 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) 483 { 484 int i; 485 486 for (i = 0; i < 4; i++) 487 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); 488 } 489 490 static void omap_aes_done_task(unsigned long data) 491 { 492 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 493 494 pr_debug("enter done_task\n"); 495 496 if (!dd->pio_only) { 497 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 498 DMA_FROM_DEVICE); 499 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 500 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 501 DMA_FROM_DEVICE); 502 omap_aes_crypt_dma_stop(dd); 503 } 504 505 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save, 506 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 507 508 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save, 509 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 510 511 /* Update IV output */ 512 if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) 513 omap_aes_copy_ivout(dd, dd->req->iv); 514 515 omap_aes_finish_req(dd, 0); 516 517 pr_debug("exit\n"); 518 } 519 520 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) 521 { 522 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 523 crypto_skcipher_reqtfm(req)); 524 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 525 struct omap_aes_dev *dd; 526 int ret; 527 528 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR)) 529 return -EINVAL; 530 531 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 532 !!(mode & FLAGS_ENCRYPT), 533 !!(mode & FLAGS_CBC)); 534 535 if (req->cryptlen < aes_fallback_sz) { 536 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); 537 538 skcipher_request_set_sync_tfm(subreq, ctx->fallback); 539 skcipher_request_set_callback(subreq, req->base.flags, NULL, 540 NULL); 541 skcipher_request_set_crypt(subreq, req->src, req->dst, 542 req->cryptlen, req->iv); 543 544 if (mode & FLAGS_ENCRYPT) 545 ret = crypto_skcipher_encrypt(subreq); 546 else 547 ret = crypto_skcipher_decrypt(subreq); 548 549 skcipher_request_zero(subreq); 550 return ret; 551 } 552 dd = omap_aes_find_dev(rctx); 553 if (!dd) 554 return -ENODEV; 555 556 rctx->mode = mode; 557 558 return omap_aes_handle_queue(dd, req); 559 } 560 561 /* ********************** ALG API ************************************ */ 562 563 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 564 unsigned int keylen) 565 { 566 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 567 int ret; 568 569 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 570 keylen != AES_KEYSIZE_256) 571 return -EINVAL; 572 573 pr_debug("enter, keylen: %d\n", keylen); 574 575 memcpy(ctx->key, key, keylen); 576 ctx->keylen = keylen; 577 578 crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 579 crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 580 CRYPTO_TFM_REQ_MASK); 581 582 ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen); 583 if (!ret) 584 return 0; 585 586 return 0; 587 } 588 589 static int omap_aes_ecb_encrypt(struct skcipher_request *req) 590 { 591 return omap_aes_crypt(req, FLAGS_ENCRYPT); 592 } 593 594 static int omap_aes_ecb_decrypt(struct skcipher_request *req) 595 { 596 return omap_aes_crypt(req, 0); 597 } 598 599 static int omap_aes_cbc_encrypt(struct skcipher_request *req) 600 { 601 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 602 } 603 604 static int omap_aes_cbc_decrypt(struct skcipher_request *req) 605 { 606 return omap_aes_crypt(req, FLAGS_CBC); 607 } 608 609 static int omap_aes_ctr_encrypt(struct skcipher_request *req) 610 { 611 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 612 } 613 614 static int omap_aes_ctr_decrypt(struct skcipher_request *req) 615 { 616 return omap_aes_crypt(req, FLAGS_CTR); 617 } 618 619 static int omap_aes_prepare_req(struct crypto_engine *engine, 620 void *req); 621 static int omap_aes_crypt_req(struct crypto_engine *engine, 622 void *req); 623 624 static int omap_aes_init_tfm(struct crypto_skcipher *tfm) 625 { 626 const char *name = crypto_tfm_alg_name(&tfm->base); 627 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 628 struct crypto_sync_skcipher *blk; 629 630 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 631 if (IS_ERR(blk)) 632 return PTR_ERR(blk); 633 634 ctx->fallback = blk; 635 636 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx)); 637 638 ctx->enginectx.op.prepare_request = omap_aes_prepare_req; 639 ctx->enginectx.op.unprepare_request = NULL; 640 ctx->enginectx.op.do_one_request = omap_aes_crypt_req; 641 642 return 0; 643 } 644 645 static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) 646 { 647 struct omap_aes_dev *dd = NULL; 648 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 649 int err; 650 651 /* Find AES device, currently picks the first device */ 652 spin_lock_bh(&list_lock); 653 list_for_each_entry(dd, &dev_list, list) { 654 break; 655 } 656 spin_unlock_bh(&list_lock); 657 658 err = pm_runtime_get_sync(dd->dev); 659 if (err < 0) { 660 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", 661 __func__, err); 662 return err; 663 } 664 665 tfm->reqsize = sizeof(struct omap_aes_reqctx); 666 ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); 667 if (IS_ERR(ctx->ctr)) { 668 pr_warn("could not load aes driver for encrypting IV\n"); 669 return PTR_ERR(ctx->ctr); 670 } 671 672 return 0; 673 } 674 675 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) 676 { 677 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 678 679 if (ctx->fallback) 680 crypto_free_sync_skcipher(ctx->fallback); 681 682 ctx->fallback = NULL; 683 } 684 685 static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) 686 { 687 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 688 689 if (ctx->fallback) 690 crypto_free_sync_skcipher(ctx->fallback); 691 692 ctx->fallback = NULL; 693 694 if (ctx->ctr) 695 crypto_free_skcipher(ctx->ctr); 696 } 697 698 /* ********************** ALGS ************************************ */ 699 700 static struct skcipher_alg algs_ecb_cbc[] = { 701 { 702 .base.cra_name = "ecb(aes)", 703 .base.cra_driver_name = "ecb-aes-omap", 704 .base.cra_priority = 300, 705 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 706 CRYPTO_ALG_ASYNC | 707 CRYPTO_ALG_NEED_FALLBACK, 708 .base.cra_blocksize = AES_BLOCK_SIZE, 709 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 710 .base.cra_module = THIS_MODULE, 711 712 .min_keysize = AES_MIN_KEY_SIZE, 713 .max_keysize = AES_MAX_KEY_SIZE, 714 .setkey = omap_aes_setkey, 715 .encrypt = omap_aes_ecb_encrypt, 716 .decrypt = omap_aes_ecb_decrypt, 717 .init = omap_aes_init_tfm, 718 .exit = omap_aes_exit_tfm, 719 }, 720 { 721 .base.cra_name = "cbc(aes)", 722 .base.cra_driver_name = "cbc-aes-omap", 723 .base.cra_priority = 300, 724 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 725 CRYPTO_ALG_ASYNC | 726 CRYPTO_ALG_NEED_FALLBACK, 727 .base.cra_blocksize = AES_BLOCK_SIZE, 728 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 729 .base.cra_module = THIS_MODULE, 730 731 .min_keysize = AES_MIN_KEY_SIZE, 732 .max_keysize = AES_MAX_KEY_SIZE, 733 .ivsize = AES_BLOCK_SIZE, 734 .setkey = omap_aes_setkey, 735 .encrypt = omap_aes_cbc_encrypt, 736 .decrypt = omap_aes_cbc_decrypt, 737 .init = omap_aes_init_tfm, 738 .exit = omap_aes_exit_tfm, 739 } 740 }; 741 742 static struct skcipher_alg algs_ctr[] = { 743 { 744 .base.cra_name = "ctr(aes)", 745 .base.cra_driver_name = "ctr-aes-omap", 746 .base.cra_priority = 300, 747 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 748 CRYPTO_ALG_ASYNC | 749 CRYPTO_ALG_NEED_FALLBACK, 750 .base.cra_blocksize = AES_BLOCK_SIZE, 751 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 752 .base.cra_module = THIS_MODULE, 753 754 .min_keysize = AES_MIN_KEY_SIZE, 755 .max_keysize = AES_MAX_KEY_SIZE, 756 .ivsize = AES_BLOCK_SIZE, 757 .setkey = omap_aes_setkey, 758 .encrypt = omap_aes_ctr_encrypt, 759 .decrypt = omap_aes_ctr_decrypt, 760 .init = omap_aes_init_tfm, 761 .exit = omap_aes_exit_tfm, 762 } 763 }; 764 765 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 766 { 767 .algs_list = algs_ecb_cbc, 768 .size = ARRAY_SIZE(algs_ecb_cbc), 769 }, 770 }; 771 772 static struct aead_alg algs_aead_gcm[] = { 773 { 774 .base = { 775 .cra_name = "gcm(aes)", 776 .cra_driver_name = "gcm-aes-omap", 777 .cra_priority = 300, 778 .cra_flags = CRYPTO_ALG_ASYNC | 779 CRYPTO_ALG_KERN_DRIVER_ONLY, 780 .cra_blocksize = 1, 781 .cra_ctxsize = sizeof(struct omap_aes_ctx), 782 .cra_alignmask = 0xf, 783 .cra_module = THIS_MODULE, 784 }, 785 .init = omap_aes_gcm_cra_init, 786 .exit = omap_aes_gcm_cra_exit, 787 .ivsize = GCM_AES_IV_SIZE, 788 .maxauthsize = AES_BLOCK_SIZE, 789 .setkey = omap_aes_gcm_setkey, 790 .encrypt = omap_aes_gcm_encrypt, 791 .decrypt = omap_aes_gcm_decrypt, 792 }, 793 { 794 .base = { 795 .cra_name = "rfc4106(gcm(aes))", 796 .cra_driver_name = "rfc4106-gcm-aes-omap", 797 .cra_priority = 300, 798 .cra_flags = CRYPTO_ALG_ASYNC | 799 CRYPTO_ALG_KERN_DRIVER_ONLY, 800 .cra_blocksize = 1, 801 .cra_ctxsize = sizeof(struct omap_aes_ctx), 802 .cra_alignmask = 0xf, 803 .cra_module = THIS_MODULE, 804 }, 805 .init = omap_aes_gcm_cra_init, 806 .exit = omap_aes_gcm_cra_exit, 807 .maxauthsize = AES_BLOCK_SIZE, 808 .ivsize = GCM_RFC4106_IV_SIZE, 809 .setkey = omap_aes_4106gcm_setkey, 810 .encrypt = omap_aes_4106gcm_encrypt, 811 .decrypt = omap_aes_4106gcm_decrypt, 812 }, 813 }; 814 815 static struct omap_aes_aead_algs omap_aes_aead_info = { 816 .algs_list = algs_aead_gcm, 817 .size = ARRAY_SIZE(algs_aead_gcm), 818 }; 819 820 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 821 .algs_info = omap_aes_algs_info_ecb_cbc, 822 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 823 .trigger = omap_aes_dma_trigger_omap2, 824 .key_ofs = 0x1c, 825 .iv_ofs = 0x20, 826 .ctrl_ofs = 0x30, 827 .data_ofs = 0x34, 828 .rev_ofs = 0x44, 829 .mask_ofs = 0x48, 830 .dma_enable_in = BIT(2), 831 .dma_enable_out = BIT(3), 832 .dma_start = BIT(5), 833 .major_mask = 0xf0, 834 .major_shift = 4, 835 .minor_mask = 0x0f, 836 .minor_shift = 0, 837 }; 838 839 #ifdef CONFIG_OF 840 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 841 { 842 .algs_list = algs_ecb_cbc, 843 .size = ARRAY_SIZE(algs_ecb_cbc), 844 }, 845 { 846 .algs_list = algs_ctr, 847 .size = ARRAY_SIZE(algs_ctr), 848 }, 849 }; 850 851 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 852 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 853 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 854 .trigger = omap_aes_dma_trigger_omap2, 855 .key_ofs = 0x1c, 856 .iv_ofs = 0x20, 857 .ctrl_ofs = 0x30, 858 .data_ofs = 0x34, 859 .rev_ofs = 0x44, 860 .mask_ofs = 0x48, 861 .dma_enable_in = BIT(2), 862 .dma_enable_out = BIT(3), 863 .dma_start = BIT(5), 864 .major_mask = 0xf0, 865 .major_shift = 4, 866 .minor_mask = 0x0f, 867 .minor_shift = 0, 868 }; 869 870 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 871 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 872 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 873 .aead_algs_info = &omap_aes_aead_info, 874 .trigger = omap_aes_dma_trigger_omap4, 875 .key_ofs = 0x3c, 876 .iv_ofs = 0x40, 877 .ctrl_ofs = 0x50, 878 .data_ofs = 0x60, 879 .rev_ofs = 0x80, 880 .mask_ofs = 0x84, 881 .irq_status_ofs = 0x8c, 882 .irq_enable_ofs = 0x90, 883 .dma_enable_in = BIT(5), 884 .dma_enable_out = BIT(6), 885 .major_mask = 0x0700, 886 .major_shift = 8, 887 .minor_mask = 0x003f, 888 .minor_shift = 0, 889 }; 890 891 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 892 { 893 struct omap_aes_dev *dd = dev_id; 894 u32 status, i; 895 u32 *src, *dst; 896 897 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 898 if (status & AES_REG_IRQ_DATA_IN) { 899 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 900 901 BUG_ON(!dd->in_sg); 902 903 BUG_ON(_calc_walked(in) > dd->in_sg->length); 904 905 src = sg_virt(dd->in_sg) + _calc_walked(in); 906 907 for (i = 0; i < AES_BLOCK_WORDS; i++) { 908 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 909 910 scatterwalk_advance(&dd->in_walk, 4); 911 if (dd->in_sg->length == _calc_walked(in)) { 912 dd->in_sg = sg_next(dd->in_sg); 913 if (dd->in_sg) { 914 scatterwalk_start(&dd->in_walk, 915 dd->in_sg); 916 src = sg_virt(dd->in_sg) + 917 _calc_walked(in); 918 } 919 } else { 920 src++; 921 } 922 } 923 924 /* Clear IRQ status */ 925 status &= ~AES_REG_IRQ_DATA_IN; 926 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 927 928 /* Enable DATA_OUT interrupt */ 929 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 930 931 } else if (status & AES_REG_IRQ_DATA_OUT) { 932 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 933 934 BUG_ON(!dd->out_sg); 935 936 BUG_ON(_calc_walked(out) > dd->out_sg->length); 937 938 dst = sg_virt(dd->out_sg) + _calc_walked(out); 939 940 for (i = 0; i < AES_BLOCK_WORDS; i++) { 941 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 942 scatterwalk_advance(&dd->out_walk, 4); 943 if (dd->out_sg->length == _calc_walked(out)) { 944 dd->out_sg = sg_next(dd->out_sg); 945 if (dd->out_sg) { 946 scatterwalk_start(&dd->out_walk, 947 dd->out_sg); 948 dst = sg_virt(dd->out_sg) + 949 _calc_walked(out); 950 } 951 } else { 952 dst++; 953 } 954 } 955 956 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 957 958 /* Clear IRQ status */ 959 status &= ~AES_REG_IRQ_DATA_OUT; 960 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 961 962 if (!dd->total) 963 /* All bytes read! */ 964 tasklet_schedule(&dd->done_task); 965 else 966 /* Enable DATA_IN interrupt for next block */ 967 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 968 } 969 970 return IRQ_HANDLED; 971 } 972 973 static const struct of_device_id omap_aes_of_match[] = { 974 { 975 .compatible = "ti,omap2-aes", 976 .data = &omap_aes_pdata_omap2, 977 }, 978 { 979 .compatible = "ti,omap3-aes", 980 .data = &omap_aes_pdata_omap3, 981 }, 982 { 983 .compatible = "ti,omap4-aes", 984 .data = &omap_aes_pdata_omap4, 985 }, 986 {}, 987 }; 988 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 989 990 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 991 struct device *dev, struct resource *res) 992 { 993 struct device_node *node = dev->of_node; 994 int err = 0; 995 996 dd->pdata = of_device_get_match_data(dev); 997 if (!dd->pdata) { 998 dev_err(dev, "no compatible OF match\n"); 999 err = -EINVAL; 1000 goto err; 1001 } 1002 1003 err = of_address_to_resource(node, 0, res); 1004 if (err < 0) { 1005 dev_err(dev, "can't translate OF node address\n"); 1006 err = -EINVAL; 1007 goto err; 1008 } 1009 1010 err: 1011 return err; 1012 } 1013 #else 1014 static const struct of_device_id omap_aes_of_match[] = { 1015 {}, 1016 }; 1017 1018 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1019 struct device *dev, struct resource *res) 1020 { 1021 return -EINVAL; 1022 } 1023 #endif 1024 1025 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 1026 struct platform_device *pdev, struct resource *res) 1027 { 1028 struct device *dev = &pdev->dev; 1029 struct resource *r; 1030 int err = 0; 1031 1032 /* Get the base address */ 1033 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1034 if (!r) { 1035 dev_err(dev, "no MEM resource info\n"); 1036 err = -ENODEV; 1037 goto err; 1038 } 1039 memcpy(res, r, sizeof(*res)); 1040 1041 /* Only OMAP2/3 can be non-DT */ 1042 dd->pdata = &omap_aes_pdata_omap2; 1043 1044 err: 1045 return err; 1046 } 1047 1048 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1049 char *buf) 1050 { 1051 return sprintf(buf, "%d\n", aes_fallback_sz); 1052 } 1053 1054 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1055 const char *buf, size_t size) 1056 { 1057 ssize_t status; 1058 long value; 1059 1060 status = kstrtol(buf, 0, &value); 1061 if (status) 1062 return status; 1063 1064 /* HW accelerator only works with buffers > 9 */ 1065 if (value < 9) { 1066 dev_err(dev, "minimum fallback size 9\n"); 1067 return -EINVAL; 1068 } 1069 1070 aes_fallback_sz = value; 1071 1072 return size; 1073 } 1074 1075 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1076 char *buf) 1077 { 1078 struct omap_aes_dev *dd = dev_get_drvdata(dev); 1079 1080 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); 1081 } 1082 1083 static ssize_t queue_len_store(struct device *dev, 1084 struct device_attribute *attr, const char *buf, 1085 size_t size) 1086 { 1087 struct omap_aes_dev *dd; 1088 ssize_t status; 1089 long value; 1090 unsigned long flags; 1091 1092 status = kstrtol(buf, 0, &value); 1093 if (status) 1094 return status; 1095 1096 if (value < 1) 1097 return -EINVAL; 1098 1099 /* 1100 * Changing the queue size in fly is safe, if size becomes smaller 1101 * than current size, it will just not accept new entries until 1102 * it has shrank enough. 1103 */ 1104 spin_lock_bh(&list_lock); 1105 list_for_each_entry(dd, &dev_list, list) { 1106 spin_lock_irqsave(&dd->lock, flags); 1107 dd->engine->queue.max_qlen = value; 1108 dd->aead_queue.base.max_qlen = value; 1109 spin_unlock_irqrestore(&dd->lock, flags); 1110 } 1111 spin_unlock_bh(&list_lock); 1112 1113 return size; 1114 } 1115 1116 static DEVICE_ATTR_RW(queue_len); 1117 static DEVICE_ATTR_RW(fallback); 1118 1119 static struct attribute *omap_aes_attrs[] = { 1120 &dev_attr_queue_len.attr, 1121 &dev_attr_fallback.attr, 1122 NULL, 1123 }; 1124 1125 static struct attribute_group omap_aes_attr_group = { 1126 .attrs = omap_aes_attrs, 1127 }; 1128 1129 static int omap_aes_probe(struct platform_device *pdev) 1130 { 1131 struct device *dev = &pdev->dev; 1132 struct omap_aes_dev *dd; 1133 struct skcipher_alg *algp; 1134 struct aead_alg *aalg; 1135 struct resource res; 1136 int err = -ENOMEM, i, j, irq = -1; 1137 u32 reg; 1138 1139 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1140 if (dd == NULL) { 1141 dev_err(dev, "unable to alloc data struct.\n"); 1142 goto err_data; 1143 } 1144 dd->dev = dev; 1145 platform_set_drvdata(pdev, dd); 1146 1147 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1148 1149 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1150 omap_aes_get_res_pdev(dd, pdev, &res); 1151 if (err) 1152 goto err_res; 1153 1154 dd->io_base = devm_ioremap_resource(dev, &res); 1155 if (IS_ERR(dd->io_base)) { 1156 err = PTR_ERR(dd->io_base); 1157 goto err_res; 1158 } 1159 dd->phys_base = res.start; 1160 1161 pm_runtime_use_autosuspend(dev); 1162 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1163 1164 pm_runtime_enable(dev); 1165 err = pm_runtime_get_sync(dev); 1166 if (err < 0) { 1167 dev_err(dev, "%s: failed to get_sync(%d)\n", 1168 __func__, err); 1169 goto err_res; 1170 } 1171 1172 omap_aes_dma_stop(dd); 1173 1174 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1175 1176 pm_runtime_put_sync(dev); 1177 1178 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1179 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1180 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1181 1182 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1183 1184 err = omap_aes_dma_init(dd); 1185 if (err == -EPROBE_DEFER) { 1186 goto err_irq; 1187 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1188 dd->pio_only = 1; 1189 1190 irq = platform_get_irq(pdev, 0); 1191 if (irq < 0) { 1192 err = irq; 1193 goto err_irq; 1194 } 1195 1196 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1197 dev_name(dev), dd); 1198 if (err) { 1199 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1200 goto err_irq; 1201 } 1202 } 1203 1204 spin_lock_init(&dd->lock); 1205 1206 INIT_LIST_HEAD(&dd->list); 1207 spin_lock(&list_lock); 1208 list_add_tail(&dd->list, &dev_list); 1209 spin_unlock(&list_lock); 1210 1211 /* Initialize crypto engine */ 1212 dd->engine = crypto_engine_alloc_init(dev, 1); 1213 if (!dd->engine) { 1214 err = -ENOMEM; 1215 goto err_engine; 1216 } 1217 1218 err = crypto_engine_start(dd->engine); 1219 if (err) 1220 goto err_engine; 1221 1222 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1223 if (!dd->pdata->algs_info[i].registered) { 1224 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1225 algp = &dd->pdata->algs_info[i].algs_list[j]; 1226 1227 pr_debug("reg alg: %s\n", algp->base.cra_name); 1228 1229 err = crypto_register_skcipher(algp); 1230 if (err) 1231 goto err_algs; 1232 1233 dd->pdata->algs_info[i].registered++; 1234 } 1235 } 1236 } 1237 1238 if (dd->pdata->aead_algs_info && 1239 !dd->pdata->aead_algs_info->registered) { 1240 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1241 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1242 1243 pr_debug("reg alg: %s\n", aalg->base.cra_name); 1244 1245 err = crypto_register_aead(aalg); 1246 if (err) 1247 goto err_aead_algs; 1248 1249 dd->pdata->aead_algs_info->registered++; 1250 } 1251 } 1252 1253 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); 1254 if (err) { 1255 dev_err(dev, "could not create sysfs device attrs\n"); 1256 goto err_aead_algs; 1257 } 1258 1259 return 0; 1260 err_aead_algs: 1261 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1262 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1263 crypto_unregister_aead(aalg); 1264 } 1265 err_algs: 1266 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1267 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1268 crypto_unregister_skcipher( 1269 &dd->pdata->algs_info[i].algs_list[j]); 1270 1271 err_engine: 1272 if (dd->engine) 1273 crypto_engine_exit(dd->engine); 1274 1275 omap_aes_dma_cleanup(dd); 1276 err_irq: 1277 tasklet_kill(&dd->done_task); 1278 pm_runtime_disable(dev); 1279 err_res: 1280 dd = NULL; 1281 err_data: 1282 dev_err(dev, "initialization failed.\n"); 1283 return err; 1284 } 1285 1286 static int omap_aes_remove(struct platform_device *pdev) 1287 { 1288 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1289 struct aead_alg *aalg; 1290 int i, j; 1291 1292 if (!dd) 1293 return -ENODEV; 1294 1295 spin_lock(&list_lock); 1296 list_del(&dd->list); 1297 spin_unlock(&list_lock); 1298 1299 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1300 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1301 crypto_unregister_skcipher( 1302 &dd->pdata->algs_info[i].algs_list[j]); 1303 1304 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { 1305 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1306 crypto_unregister_aead(aalg); 1307 } 1308 1309 crypto_engine_exit(dd->engine); 1310 1311 tasklet_kill(&dd->done_task); 1312 omap_aes_dma_cleanup(dd); 1313 pm_runtime_disable(dd->dev); 1314 1315 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group); 1316 1317 return 0; 1318 } 1319 1320 #ifdef CONFIG_PM_SLEEP 1321 static int omap_aes_suspend(struct device *dev) 1322 { 1323 pm_runtime_put_sync(dev); 1324 return 0; 1325 } 1326 1327 static int omap_aes_resume(struct device *dev) 1328 { 1329 pm_runtime_get_sync(dev); 1330 return 0; 1331 } 1332 #endif 1333 1334 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1335 1336 static struct platform_driver omap_aes_driver = { 1337 .probe = omap_aes_probe, 1338 .remove = omap_aes_remove, 1339 .driver = { 1340 .name = "omap-aes", 1341 .pm = &omap_aes_pm_ops, 1342 .of_match_table = omap_aes_of_match, 1343 }, 1344 }; 1345 1346 module_platform_driver(omap_aes_driver); 1347 1348 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1349 MODULE_LICENSE("GPL v2"); 1350 MODULE_AUTHOR("Dmitry Kasatkin"); 1351 1352