1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 */ 11 12 #define pr_fmt(fmt) "%20s: " fmt, __func__ 13 #define prn(num) pr_debug(#num "=%d\n", num) 14 #define prx(num) pr_debug(#num "=%x\n", num) 15 16 #include <crypto/aes.h> 17 #include <crypto/gcm.h> 18 #include <crypto/internal/aead.h> 19 #include <crypto/internal/engine.h> 20 #include <crypto/internal/skcipher.h> 21 #include <crypto/scatterwalk.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/err.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/scatterlist.h> 36 37 #include "omap-crypto.h" 38 #include "omap-aes.h" 39 40 /* keep registered devices data here */ 41 static LIST_HEAD(dev_list); 42 static DEFINE_SPINLOCK(list_lock); 43 44 static int aes_fallback_sz = 200; 45 46 #ifdef DEBUG 47 #define omap_aes_read(dd, offset) \ 48 ({ \ 49 int _read_ret; \ 50 _read_ret = __raw_readl(dd->io_base + offset); \ 51 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 52 offset, _read_ret); \ 53 _read_ret; \ 54 }) 55 #else 56 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 57 { 58 return __raw_readl(dd->io_base + offset); 59 } 60 #endif 61 62 #ifdef DEBUG 63 #define omap_aes_write(dd, offset, value) \ 64 do { \ 65 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 66 offset, value); \ 67 __raw_writel(value, dd->io_base + offset); \ 68 } while (0) 69 #else 70 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 71 u32 value) 72 { 73 __raw_writel(value, dd->io_base + offset); 74 } 75 #endif 76 77 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 78 u32 value, u32 mask) 79 { 80 u32 val; 81 82 val = omap_aes_read(dd, offset); 83 val &= ~mask; 84 val |= value; 85 omap_aes_write(dd, offset, val); 86 } 87 88 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 89 u32 *value, int count) 90 { 91 for (; count--; value++, offset += 4) 92 omap_aes_write(dd, offset, *value); 93 } 94 95 static int omap_aes_hw_init(struct omap_aes_dev *dd) 96 { 97 int err; 98 99 if (!(dd->flags & FLAGS_INIT)) { 100 dd->flags |= FLAGS_INIT; 101 dd->err = 0; 102 } 103 104 err = pm_runtime_resume_and_get(dd->dev); 105 if (err < 0) { 106 dev_err(dd->dev, "failed to get sync: %d\n", err); 107 return err; 108 } 109 110 return 0; 111 } 112 113 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 114 { 115 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 116 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 118 } 119 120 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 121 { 122 struct omap_aes_reqctx *rctx; 123 unsigned int key32; 124 int i, err; 125 u32 val; 126 127 err = omap_aes_hw_init(dd); 128 if (err) 129 return err; 130 131 key32 = dd->ctx->keylen / sizeof(u32); 132 133 /* RESET the key as previous HASH keys should not get affected*/ 134 if (dd->flags & FLAGS_GCM) 135 for (i = 0; i < 0x40; i = i + 4) 136 omap_aes_write(dd, i, 0x0); 137 138 for (i = 0; i < key32; i++) { 139 omap_aes_write(dd, AES_REG_KEY(dd, i), 140 (__force u32)cpu_to_le32(dd->ctx->key[i])); 141 } 142 143 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) 144 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4); 145 146 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 147 rctx = aead_request_ctx(dd->aead_req); 148 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 149 } 150 151 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 152 if (dd->flags & FLAGS_CBC) 153 val |= AES_REG_CTRL_CBC; 154 155 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 156 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 157 158 if (dd->flags & FLAGS_GCM) 159 val |= AES_REG_CTRL_GCM; 160 161 if (dd->flags & FLAGS_ENCRYPT) 162 val |= AES_REG_CTRL_DIRECTION; 163 164 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 165 166 return 0; 167 } 168 169 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 170 { 171 u32 mask, val; 172 173 val = dd->pdata->dma_start; 174 175 if (dd->dma_lch_out != NULL) 176 val |= dd->pdata->dma_enable_out; 177 if (dd->dma_lch_in != NULL) 178 val |= dd->pdata->dma_enable_in; 179 180 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 181 dd->pdata->dma_start; 182 183 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 184 185 } 186 187 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 188 { 189 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 190 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 191 if (dd->flags & FLAGS_GCM) 192 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 193 194 omap_aes_dma_trigger_omap2(dd, length); 195 } 196 197 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 198 { 199 u32 mask; 200 201 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 202 dd->pdata->dma_start; 203 204 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 205 } 206 207 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 208 { 209 struct omap_aes_dev *dd; 210 211 spin_lock_bh(&list_lock); 212 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 213 list_move_tail(&dd->list, &dev_list); 214 rctx->dd = dd; 215 spin_unlock_bh(&list_lock); 216 217 return dd; 218 } 219 220 static void omap_aes_dma_out_callback(void *data) 221 { 222 struct omap_aes_dev *dd = data; 223 224 /* dma_lch_out - completed */ 225 tasklet_schedule(&dd->done_task); 226 } 227 228 static int omap_aes_dma_init(struct omap_aes_dev *dd) 229 { 230 int err; 231 232 dd->dma_lch_out = NULL; 233 dd->dma_lch_in = NULL; 234 235 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 236 if (IS_ERR(dd->dma_lch_in)) { 237 dev_err(dd->dev, "Unable to request in DMA channel\n"); 238 return PTR_ERR(dd->dma_lch_in); 239 } 240 241 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 242 if (IS_ERR(dd->dma_lch_out)) { 243 dev_err(dd->dev, "Unable to request out DMA channel\n"); 244 err = PTR_ERR(dd->dma_lch_out); 245 goto err_dma_out; 246 } 247 248 return 0; 249 250 err_dma_out: 251 dma_release_channel(dd->dma_lch_in); 252 253 return err; 254 } 255 256 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 257 { 258 if (dd->pio_only) 259 return; 260 261 dma_release_channel(dd->dma_lch_out); 262 dma_release_channel(dd->dma_lch_in); 263 } 264 265 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 266 struct scatterlist *in_sg, 267 struct scatterlist *out_sg, 268 int in_sg_len, int out_sg_len) 269 { 270 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc; 271 struct dma_slave_config cfg; 272 int ret; 273 274 if (dd->pio_only) { 275 scatterwalk_start(&dd->in_walk, dd->in_sg); 276 if (out_sg_len) 277 scatterwalk_start(&dd->out_walk, dd->out_sg); 278 279 /* Enable DATAIN interrupt and let it take 280 care of the rest */ 281 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 282 return 0; 283 } 284 285 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 286 287 memset(&cfg, 0, sizeof(cfg)); 288 289 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 290 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 291 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 292 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 293 cfg.src_maxburst = DST_MAXBURST; 294 cfg.dst_maxburst = DST_MAXBURST; 295 296 /* IN */ 297 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 298 if (ret) { 299 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 300 ret); 301 return ret; 302 } 303 304 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 305 DMA_MEM_TO_DEV, 306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 307 if (!tx_in) { 308 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 309 return -EINVAL; 310 } 311 312 /* No callback necessary */ 313 tx_in->callback_param = dd; 314 tx_in->callback = NULL; 315 316 /* OUT */ 317 if (out_sg_len) { 318 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 319 if (ret) { 320 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 321 ret); 322 return ret; 323 } 324 325 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 326 out_sg_len, 327 DMA_DEV_TO_MEM, 328 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 329 if (!tx_out) { 330 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 331 return -EINVAL; 332 } 333 334 cb_desc = tx_out; 335 } else { 336 cb_desc = tx_in; 337 } 338 339 if (dd->flags & FLAGS_GCM) 340 cb_desc->callback = omap_aes_gcm_dma_out_callback; 341 else 342 cb_desc->callback = omap_aes_dma_out_callback; 343 cb_desc->callback_param = dd; 344 345 346 dmaengine_submit(tx_in); 347 if (tx_out) 348 dmaengine_submit(tx_out); 349 350 dma_async_issue_pending(dd->dma_lch_in); 351 if (out_sg_len) 352 dma_async_issue_pending(dd->dma_lch_out); 353 354 /* start DMA */ 355 dd->pdata->trigger(dd, dd->total); 356 357 return 0; 358 } 359 360 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 361 { 362 int err; 363 364 pr_debug("total: %zu\n", dd->total); 365 366 if (!dd->pio_only) { 367 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 368 DMA_TO_DEVICE); 369 if (!err) { 370 dev_err(dd->dev, "dma_map_sg() error\n"); 371 return -EINVAL; 372 } 373 374 if (dd->out_sg_len) { 375 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 376 DMA_FROM_DEVICE); 377 if (!err) { 378 dev_err(dd->dev, "dma_map_sg() error\n"); 379 return -EINVAL; 380 } 381 } 382 } 383 384 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 385 dd->out_sg_len); 386 if (err && !dd->pio_only) { 387 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 388 if (dd->out_sg_len) 389 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 390 DMA_FROM_DEVICE); 391 } 392 393 return err; 394 } 395 396 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 397 { 398 struct skcipher_request *req = dd->req; 399 400 pr_debug("err: %d\n", err); 401 402 crypto_finalize_skcipher_request(dd->engine, req, err); 403 404 pm_runtime_mark_last_busy(dd->dev); 405 pm_runtime_put_autosuspend(dd->dev); 406 } 407 408 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 409 { 410 pr_debug("total: %zu\n", dd->total); 411 412 omap_aes_dma_stop(dd); 413 414 415 return 0; 416 } 417 418 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 419 struct skcipher_request *req) 420 { 421 if (req) 422 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 423 424 return 0; 425 } 426 427 static int omap_aes_prepare_req(struct skcipher_request *req, 428 struct omap_aes_dev *dd) 429 { 430 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 431 crypto_skcipher_reqtfm(req)); 432 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 433 int ret; 434 u16 flags; 435 436 /* assign new request to device */ 437 dd->req = req; 438 dd->total = req->cryptlen; 439 dd->total_save = req->cryptlen; 440 dd->in_sg = req->src; 441 dd->out_sg = req->dst; 442 dd->orig_out = req->dst; 443 444 flags = OMAP_CRYPTO_COPY_DATA; 445 if (req->src == req->dst) 446 flags |= OMAP_CRYPTO_FORCE_COPY; 447 448 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 449 dd->in_sgl, flags, 450 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 451 if (ret) 452 return ret; 453 454 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 455 &dd->out_sgl, 0, 456 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 457 if (ret) 458 return ret; 459 460 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 461 if (dd->in_sg_len < 0) 462 return dd->in_sg_len; 463 464 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 465 if (dd->out_sg_len < 0) 466 return dd->out_sg_len; 467 468 rctx->mode &= FLAGS_MODE_MASK; 469 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 470 471 dd->ctx = ctx; 472 rctx->dd = dd; 473 474 return omap_aes_write_ctrl(dd); 475 } 476 477 static int omap_aes_crypt_req(struct crypto_engine *engine, 478 void *areq) 479 { 480 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 481 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 482 struct omap_aes_dev *dd = rctx->dd; 483 484 if (!dd) 485 return -ENODEV; 486 487 return omap_aes_prepare_req(req, dd) ?: 488 omap_aes_crypt_dma_start(dd); 489 } 490 491 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) 492 { 493 int i; 494 495 for (i = 0; i < 4; i++) 496 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); 497 } 498 499 static void omap_aes_done_task(unsigned long data) 500 { 501 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 502 503 pr_debug("enter done_task\n"); 504 505 if (!dd->pio_only) { 506 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 507 DMA_FROM_DEVICE); 508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 510 DMA_FROM_DEVICE); 511 omap_aes_crypt_dma_stop(dd); 512 } 513 514 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save, 515 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 516 517 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save, 518 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 519 520 /* Update IV output */ 521 if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) 522 omap_aes_copy_ivout(dd, dd->req->iv); 523 524 omap_aes_finish_req(dd, 0); 525 526 pr_debug("exit\n"); 527 } 528 529 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) 530 { 531 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 532 crypto_skcipher_reqtfm(req)); 533 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 534 struct omap_aes_dev *dd; 535 int ret; 536 537 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR)) 538 return -EINVAL; 539 540 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 541 !!(mode & FLAGS_ENCRYPT), 542 !!(mode & FLAGS_CBC)); 543 544 if (req->cryptlen < aes_fallback_sz) { 545 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); 546 skcipher_request_set_callback(&rctx->fallback_req, 547 req->base.flags, 548 req->base.complete, 549 req->base.data); 550 skcipher_request_set_crypt(&rctx->fallback_req, req->src, 551 req->dst, req->cryptlen, req->iv); 552 553 if (mode & FLAGS_ENCRYPT) 554 ret = crypto_skcipher_encrypt(&rctx->fallback_req); 555 else 556 ret = crypto_skcipher_decrypt(&rctx->fallback_req); 557 return ret; 558 } 559 dd = omap_aes_find_dev(rctx); 560 if (!dd) 561 return -ENODEV; 562 563 rctx->mode = mode; 564 565 return omap_aes_handle_queue(dd, req); 566 } 567 568 /* ********************** ALG API ************************************ */ 569 570 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 571 unsigned int keylen) 572 { 573 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 574 int ret; 575 576 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 577 keylen != AES_KEYSIZE_256) 578 return -EINVAL; 579 580 pr_debug("enter, keylen: %d\n", keylen); 581 582 memcpy(ctx->key, key, keylen); 583 ctx->keylen = keylen; 584 585 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 586 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 587 CRYPTO_TFM_REQ_MASK); 588 589 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); 590 if (!ret) 591 return 0; 592 593 return 0; 594 } 595 596 static int omap_aes_ecb_encrypt(struct skcipher_request *req) 597 { 598 return omap_aes_crypt(req, FLAGS_ENCRYPT); 599 } 600 601 static int omap_aes_ecb_decrypt(struct skcipher_request *req) 602 { 603 return omap_aes_crypt(req, 0); 604 } 605 606 static int omap_aes_cbc_encrypt(struct skcipher_request *req) 607 { 608 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 609 } 610 611 static int omap_aes_cbc_decrypt(struct skcipher_request *req) 612 { 613 return omap_aes_crypt(req, FLAGS_CBC); 614 } 615 616 static int omap_aes_ctr_encrypt(struct skcipher_request *req) 617 { 618 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 619 } 620 621 static int omap_aes_ctr_decrypt(struct skcipher_request *req) 622 { 623 return omap_aes_crypt(req, FLAGS_CTR); 624 } 625 626 static int omap_aes_init_tfm(struct crypto_skcipher *tfm) 627 { 628 const char *name = crypto_tfm_alg_name(&tfm->base); 629 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 630 struct crypto_skcipher *blk; 631 632 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 633 if (IS_ERR(blk)) 634 return PTR_ERR(blk); 635 636 ctx->fallback = blk; 637 638 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) + 639 crypto_skcipher_reqsize(blk)); 640 641 ctx->enginectx.op.do_one_request = omap_aes_crypt_req; 642 643 return 0; 644 } 645 646 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) 647 { 648 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 649 650 if (ctx->fallback) 651 crypto_free_skcipher(ctx->fallback); 652 653 ctx->fallback = NULL; 654 } 655 656 /* ********************** ALGS ************************************ */ 657 658 static struct skcipher_alg algs_ecb_cbc[] = { 659 { 660 .base.cra_name = "ecb(aes)", 661 .base.cra_driver_name = "ecb-aes-omap", 662 .base.cra_priority = 300, 663 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 664 CRYPTO_ALG_ASYNC | 665 CRYPTO_ALG_NEED_FALLBACK, 666 .base.cra_blocksize = AES_BLOCK_SIZE, 667 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 668 .base.cra_module = THIS_MODULE, 669 670 .min_keysize = AES_MIN_KEY_SIZE, 671 .max_keysize = AES_MAX_KEY_SIZE, 672 .setkey = omap_aes_setkey, 673 .encrypt = omap_aes_ecb_encrypt, 674 .decrypt = omap_aes_ecb_decrypt, 675 .init = omap_aes_init_tfm, 676 .exit = omap_aes_exit_tfm, 677 }, 678 { 679 .base.cra_name = "cbc(aes)", 680 .base.cra_driver_name = "cbc-aes-omap", 681 .base.cra_priority = 300, 682 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 683 CRYPTO_ALG_ASYNC | 684 CRYPTO_ALG_NEED_FALLBACK, 685 .base.cra_blocksize = AES_BLOCK_SIZE, 686 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 687 .base.cra_module = THIS_MODULE, 688 689 .min_keysize = AES_MIN_KEY_SIZE, 690 .max_keysize = AES_MAX_KEY_SIZE, 691 .ivsize = AES_BLOCK_SIZE, 692 .setkey = omap_aes_setkey, 693 .encrypt = omap_aes_cbc_encrypt, 694 .decrypt = omap_aes_cbc_decrypt, 695 .init = omap_aes_init_tfm, 696 .exit = omap_aes_exit_tfm, 697 } 698 }; 699 700 static struct skcipher_alg algs_ctr[] = { 701 { 702 .base.cra_name = "ctr(aes)", 703 .base.cra_driver_name = "ctr-aes-omap", 704 .base.cra_priority = 300, 705 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 706 CRYPTO_ALG_ASYNC | 707 CRYPTO_ALG_NEED_FALLBACK, 708 .base.cra_blocksize = 1, 709 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 710 .base.cra_module = THIS_MODULE, 711 712 .min_keysize = AES_MIN_KEY_SIZE, 713 .max_keysize = AES_MAX_KEY_SIZE, 714 .ivsize = AES_BLOCK_SIZE, 715 .setkey = omap_aes_setkey, 716 .encrypt = omap_aes_ctr_encrypt, 717 .decrypt = omap_aes_ctr_decrypt, 718 .init = omap_aes_init_tfm, 719 .exit = omap_aes_exit_tfm, 720 } 721 }; 722 723 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 724 { 725 .algs_list = algs_ecb_cbc, 726 .size = ARRAY_SIZE(algs_ecb_cbc), 727 }, 728 }; 729 730 static struct aead_alg algs_aead_gcm[] = { 731 { 732 .base = { 733 .cra_name = "gcm(aes)", 734 .cra_driver_name = "gcm-aes-omap", 735 .cra_priority = 300, 736 .cra_flags = CRYPTO_ALG_ASYNC | 737 CRYPTO_ALG_KERN_DRIVER_ONLY, 738 .cra_blocksize = 1, 739 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 740 .cra_alignmask = 0xf, 741 .cra_module = THIS_MODULE, 742 }, 743 .init = omap_aes_gcm_cra_init, 744 .ivsize = GCM_AES_IV_SIZE, 745 .maxauthsize = AES_BLOCK_SIZE, 746 .setkey = omap_aes_gcm_setkey, 747 .setauthsize = omap_aes_gcm_setauthsize, 748 .encrypt = omap_aes_gcm_encrypt, 749 .decrypt = omap_aes_gcm_decrypt, 750 }, 751 { 752 .base = { 753 .cra_name = "rfc4106(gcm(aes))", 754 .cra_driver_name = "rfc4106-gcm-aes-omap", 755 .cra_priority = 300, 756 .cra_flags = CRYPTO_ALG_ASYNC | 757 CRYPTO_ALG_KERN_DRIVER_ONLY, 758 .cra_blocksize = 1, 759 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 760 .cra_alignmask = 0xf, 761 .cra_module = THIS_MODULE, 762 }, 763 .init = omap_aes_gcm_cra_init, 764 .maxauthsize = AES_BLOCK_SIZE, 765 .ivsize = GCM_RFC4106_IV_SIZE, 766 .setkey = omap_aes_4106gcm_setkey, 767 .setauthsize = omap_aes_4106gcm_setauthsize, 768 .encrypt = omap_aes_4106gcm_encrypt, 769 .decrypt = omap_aes_4106gcm_decrypt, 770 }, 771 }; 772 773 static struct omap_aes_aead_algs omap_aes_aead_info = { 774 .algs_list = algs_aead_gcm, 775 .size = ARRAY_SIZE(algs_aead_gcm), 776 }; 777 778 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 779 .algs_info = omap_aes_algs_info_ecb_cbc, 780 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 781 .trigger = omap_aes_dma_trigger_omap2, 782 .key_ofs = 0x1c, 783 .iv_ofs = 0x20, 784 .ctrl_ofs = 0x30, 785 .data_ofs = 0x34, 786 .rev_ofs = 0x44, 787 .mask_ofs = 0x48, 788 .dma_enable_in = BIT(2), 789 .dma_enable_out = BIT(3), 790 .dma_start = BIT(5), 791 .major_mask = 0xf0, 792 .major_shift = 4, 793 .minor_mask = 0x0f, 794 .minor_shift = 0, 795 }; 796 797 #ifdef CONFIG_OF 798 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 799 { 800 .algs_list = algs_ecb_cbc, 801 .size = ARRAY_SIZE(algs_ecb_cbc), 802 }, 803 { 804 .algs_list = algs_ctr, 805 .size = ARRAY_SIZE(algs_ctr), 806 }, 807 }; 808 809 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 810 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 811 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 812 .trigger = omap_aes_dma_trigger_omap2, 813 .key_ofs = 0x1c, 814 .iv_ofs = 0x20, 815 .ctrl_ofs = 0x30, 816 .data_ofs = 0x34, 817 .rev_ofs = 0x44, 818 .mask_ofs = 0x48, 819 .dma_enable_in = BIT(2), 820 .dma_enable_out = BIT(3), 821 .dma_start = BIT(5), 822 .major_mask = 0xf0, 823 .major_shift = 4, 824 .minor_mask = 0x0f, 825 .minor_shift = 0, 826 }; 827 828 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 829 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 830 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 831 .aead_algs_info = &omap_aes_aead_info, 832 .trigger = omap_aes_dma_trigger_omap4, 833 .key_ofs = 0x3c, 834 .iv_ofs = 0x40, 835 .ctrl_ofs = 0x50, 836 .data_ofs = 0x60, 837 .rev_ofs = 0x80, 838 .mask_ofs = 0x84, 839 .irq_status_ofs = 0x8c, 840 .irq_enable_ofs = 0x90, 841 .dma_enable_in = BIT(5), 842 .dma_enable_out = BIT(6), 843 .major_mask = 0x0700, 844 .major_shift = 8, 845 .minor_mask = 0x003f, 846 .minor_shift = 0, 847 }; 848 849 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 850 { 851 struct omap_aes_dev *dd = dev_id; 852 u32 status, i; 853 u32 *src, *dst; 854 855 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 856 if (status & AES_REG_IRQ_DATA_IN) { 857 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 858 859 BUG_ON(!dd->in_sg); 860 861 BUG_ON(_calc_walked(in) > dd->in_sg->length); 862 863 src = sg_virt(dd->in_sg) + _calc_walked(in); 864 865 for (i = 0; i < AES_BLOCK_WORDS; i++) { 866 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 867 868 scatterwalk_advance(&dd->in_walk, 4); 869 if (dd->in_sg->length == _calc_walked(in)) { 870 dd->in_sg = sg_next(dd->in_sg); 871 if (dd->in_sg) { 872 scatterwalk_start(&dd->in_walk, 873 dd->in_sg); 874 src = sg_virt(dd->in_sg) + 875 _calc_walked(in); 876 } 877 } else { 878 src++; 879 } 880 } 881 882 /* Clear IRQ status */ 883 status &= ~AES_REG_IRQ_DATA_IN; 884 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 885 886 /* Enable DATA_OUT interrupt */ 887 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 888 889 } else if (status & AES_REG_IRQ_DATA_OUT) { 890 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 891 892 BUG_ON(!dd->out_sg); 893 894 BUG_ON(_calc_walked(out) > dd->out_sg->length); 895 896 dst = sg_virt(dd->out_sg) + _calc_walked(out); 897 898 for (i = 0; i < AES_BLOCK_WORDS; i++) { 899 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 900 scatterwalk_advance(&dd->out_walk, 4); 901 if (dd->out_sg->length == _calc_walked(out)) { 902 dd->out_sg = sg_next(dd->out_sg); 903 if (dd->out_sg) { 904 scatterwalk_start(&dd->out_walk, 905 dd->out_sg); 906 dst = sg_virt(dd->out_sg) + 907 _calc_walked(out); 908 } 909 } else { 910 dst++; 911 } 912 } 913 914 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 915 916 /* Clear IRQ status */ 917 status &= ~AES_REG_IRQ_DATA_OUT; 918 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 919 920 if (!dd->total) 921 /* All bytes read! */ 922 tasklet_schedule(&dd->done_task); 923 else 924 /* Enable DATA_IN interrupt for next block */ 925 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 926 } 927 928 return IRQ_HANDLED; 929 } 930 931 static const struct of_device_id omap_aes_of_match[] = { 932 { 933 .compatible = "ti,omap2-aes", 934 .data = &omap_aes_pdata_omap2, 935 }, 936 { 937 .compatible = "ti,omap3-aes", 938 .data = &omap_aes_pdata_omap3, 939 }, 940 { 941 .compatible = "ti,omap4-aes", 942 .data = &omap_aes_pdata_omap4, 943 }, 944 {}, 945 }; 946 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 947 948 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 949 struct device *dev, struct resource *res) 950 { 951 struct device_node *node = dev->of_node; 952 int err = 0; 953 954 dd->pdata = of_device_get_match_data(dev); 955 if (!dd->pdata) { 956 dev_err(dev, "no compatible OF match\n"); 957 err = -EINVAL; 958 goto err; 959 } 960 961 err = of_address_to_resource(node, 0, res); 962 if (err < 0) { 963 dev_err(dev, "can't translate OF node address\n"); 964 err = -EINVAL; 965 goto err; 966 } 967 968 err: 969 return err; 970 } 971 #else 972 static const struct of_device_id omap_aes_of_match[] = { 973 {}, 974 }; 975 976 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 977 struct device *dev, struct resource *res) 978 { 979 return -EINVAL; 980 } 981 #endif 982 983 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 984 struct platform_device *pdev, struct resource *res) 985 { 986 struct device *dev = &pdev->dev; 987 struct resource *r; 988 int err = 0; 989 990 /* Get the base address */ 991 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 992 if (!r) { 993 dev_err(dev, "no MEM resource info\n"); 994 err = -ENODEV; 995 goto err; 996 } 997 memcpy(res, r, sizeof(*res)); 998 999 /* Only OMAP2/3 can be non-DT */ 1000 dd->pdata = &omap_aes_pdata_omap2; 1001 1002 err: 1003 return err; 1004 } 1005 1006 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1007 char *buf) 1008 { 1009 return sprintf(buf, "%d\n", aes_fallback_sz); 1010 } 1011 1012 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1013 const char *buf, size_t size) 1014 { 1015 ssize_t status; 1016 long value; 1017 1018 status = kstrtol(buf, 0, &value); 1019 if (status) 1020 return status; 1021 1022 /* HW accelerator only works with buffers > 9 */ 1023 if (value < 9) { 1024 dev_err(dev, "minimum fallback size 9\n"); 1025 return -EINVAL; 1026 } 1027 1028 aes_fallback_sz = value; 1029 1030 return size; 1031 } 1032 1033 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1034 char *buf) 1035 { 1036 struct omap_aes_dev *dd = dev_get_drvdata(dev); 1037 1038 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); 1039 } 1040 1041 static ssize_t queue_len_store(struct device *dev, 1042 struct device_attribute *attr, const char *buf, 1043 size_t size) 1044 { 1045 struct omap_aes_dev *dd; 1046 ssize_t status; 1047 long value; 1048 unsigned long flags; 1049 1050 status = kstrtol(buf, 0, &value); 1051 if (status) 1052 return status; 1053 1054 if (value < 1) 1055 return -EINVAL; 1056 1057 /* 1058 * Changing the queue size in fly is safe, if size becomes smaller 1059 * than current size, it will just not accept new entries until 1060 * it has shrank enough. 1061 */ 1062 spin_lock_bh(&list_lock); 1063 list_for_each_entry(dd, &dev_list, list) { 1064 spin_lock_irqsave(&dd->lock, flags); 1065 dd->engine->queue.max_qlen = value; 1066 dd->aead_queue.base.max_qlen = value; 1067 spin_unlock_irqrestore(&dd->lock, flags); 1068 } 1069 spin_unlock_bh(&list_lock); 1070 1071 return size; 1072 } 1073 1074 static DEVICE_ATTR_RW(queue_len); 1075 static DEVICE_ATTR_RW(fallback); 1076 1077 static struct attribute *omap_aes_attrs[] = { 1078 &dev_attr_queue_len.attr, 1079 &dev_attr_fallback.attr, 1080 NULL, 1081 }; 1082 1083 static const struct attribute_group omap_aes_attr_group = { 1084 .attrs = omap_aes_attrs, 1085 }; 1086 1087 static int omap_aes_probe(struct platform_device *pdev) 1088 { 1089 struct device *dev = &pdev->dev; 1090 struct omap_aes_dev *dd; 1091 struct skcipher_alg *algp; 1092 struct aead_alg *aalg; 1093 struct resource res; 1094 int err = -ENOMEM, i, j, irq = -1; 1095 u32 reg; 1096 1097 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1098 if (dd == NULL) { 1099 dev_err(dev, "unable to alloc data struct.\n"); 1100 goto err_data; 1101 } 1102 dd->dev = dev; 1103 platform_set_drvdata(pdev, dd); 1104 1105 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1106 1107 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1108 omap_aes_get_res_pdev(dd, pdev, &res); 1109 if (err) 1110 goto err_res; 1111 1112 dd->io_base = devm_ioremap_resource(dev, &res); 1113 if (IS_ERR(dd->io_base)) { 1114 err = PTR_ERR(dd->io_base); 1115 goto err_res; 1116 } 1117 dd->phys_base = res.start; 1118 1119 pm_runtime_use_autosuspend(dev); 1120 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1121 1122 pm_runtime_enable(dev); 1123 err = pm_runtime_resume_and_get(dev); 1124 if (err < 0) { 1125 dev_err(dev, "%s: failed to get_sync(%d)\n", 1126 __func__, err); 1127 goto err_pm_disable; 1128 } 1129 1130 omap_aes_dma_stop(dd); 1131 1132 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1133 1134 pm_runtime_put_sync(dev); 1135 1136 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1137 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1138 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1139 1140 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1141 1142 err = omap_aes_dma_init(dd); 1143 if (err == -EPROBE_DEFER) { 1144 goto err_irq; 1145 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1146 dd->pio_only = 1; 1147 1148 irq = platform_get_irq(pdev, 0); 1149 if (irq < 0) { 1150 err = irq; 1151 goto err_irq; 1152 } 1153 1154 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1155 dev_name(dev), dd); 1156 if (err) { 1157 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1158 goto err_irq; 1159 } 1160 } 1161 1162 spin_lock_init(&dd->lock); 1163 1164 INIT_LIST_HEAD(&dd->list); 1165 spin_lock_bh(&list_lock); 1166 list_add_tail(&dd->list, &dev_list); 1167 spin_unlock_bh(&list_lock); 1168 1169 /* Initialize crypto engine */ 1170 dd->engine = crypto_engine_alloc_init(dev, 1); 1171 if (!dd->engine) { 1172 err = -ENOMEM; 1173 goto err_engine; 1174 } 1175 1176 err = crypto_engine_start(dd->engine); 1177 if (err) 1178 goto err_engine; 1179 1180 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1181 if (!dd->pdata->algs_info[i].registered) { 1182 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1183 algp = &dd->pdata->algs_info[i].algs_list[j]; 1184 1185 pr_debug("reg alg: %s\n", algp->base.cra_name); 1186 1187 err = crypto_register_skcipher(algp); 1188 if (err) 1189 goto err_algs; 1190 1191 dd->pdata->algs_info[i].registered++; 1192 } 1193 } 1194 } 1195 1196 if (dd->pdata->aead_algs_info && 1197 !dd->pdata->aead_algs_info->registered) { 1198 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1199 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1200 1201 pr_debug("reg alg: %s\n", aalg->base.cra_name); 1202 1203 err = crypto_register_aead(aalg); 1204 if (err) 1205 goto err_aead_algs; 1206 1207 dd->pdata->aead_algs_info->registered++; 1208 } 1209 } 1210 1211 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); 1212 if (err) { 1213 dev_err(dev, "could not create sysfs device attrs\n"); 1214 goto err_aead_algs; 1215 } 1216 1217 return 0; 1218 err_aead_algs: 1219 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1220 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1221 crypto_unregister_aead(aalg); 1222 } 1223 err_algs: 1224 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1225 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1226 crypto_unregister_skcipher( 1227 &dd->pdata->algs_info[i].algs_list[j]); 1228 1229 err_engine: 1230 if (dd->engine) 1231 crypto_engine_exit(dd->engine); 1232 1233 omap_aes_dma_cleanup(dd); 1234 err_irq: 1235 tasklet_kill(&dd->done_task); 1236 err_pm_disable: 1237 pm_runtime_disable(dev); 1238 err_res: 1239 dd = NULL; 1240 err_data: 1241 dev_err(dev, "initialization failed.\n"); 1242 return err; 1243 } 1244 1245 static int omap_aes_remove(struct platform_device *pdev) 1246 { 1247 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1248 struct aead_alg *aalg; 1249 int i, j; 1250 1251 spin_lock_bh(&list_lock); 1252 list_del(&dd->list); 1253 spin_unlock_bh(&list_lock); 1254 1255 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1256 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { 1257 crypto_unregister_skcipher( 1258 &dd->pdata->algs_info[i].algs_list[j]); 1259 dd->pdata->algs_info[i].registered--; 1260 } 1261 1262 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1263 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1264 crypto_unregister_aead(aalg); 1265 dd->pdata->aead_algs_info->registered--; 1266 } 1267 1268 crypto_engine_exit(dd->engine); 1269 1270 tasklet_kill(&dd->done_task); 1271 omap_aes_dma_cleanup(dd); 1272 pm_runtime_disable(dd->dev); 1273 1274 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group); 1275 1276 return 0; 1277 } 1278 1279 #ifdef CONFIG_PM_SLEEP 1280 static int omap_aes_suspend(struct device *dev) 1281 { 1282 pm_runtime_put_sync(dev); 1283 return 0; 1284 } 1285 1286 static int omap_aes_resume(struct device *dev) 1287 { 1288 pm_runtime_get_sync(dev); 1289 return 0; 1290 } 1291 #endif 1292 1293 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1294 1295 static struct platform_driver omap_aes_driver = { 1296 .probe = omap_aes_probe, 1297 .remove = omap_aes_remove, 1298 .driver = { 1299 .name = "omap-aes", 1300 .pm = &omap_aes_pm_ops, 1301 .of_match_table = omap_aes_of_match, 1302 }, 1303 }; 1304 1305 module_platform_driver(omap_aes_driver); 1306 1307 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1308 MODULE_LICENSE("GPL v2"); 1309 MODULE_AUTHOR("Dmitry Kasatkin"); 1310 1311