1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 */ 11 12 #define pr_fmt(fmt) "%20s: " fmt, __func__ 13 #define prn(num) pr_debug(#num "=%d\n", num) 14 #define prx(num) pr_debug(#num "=%x\n", num) 15 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/errno.h> 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/scatterlist.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_address.h> 29 #include <linux/io.h> 30 #include <linux/crypto.h> 31 #include <linux/interrupt.h> 32 #include <crypto/scatterwalk.h> 33 #include <crypto/aes.h> 34 #include <crypto/gcm.h> 35 #include <crypto/engine.h> 36 #include <crypto/internal/skcipher.h> 37 #include <crypto/internal/aead.h> 38 39 #include "omap-crypto.h" 40 #include "omap-aes.h" 41 42 /* keep registered devices data here */ 43 static LIST_HEAD(dev_list); 44 static DEFINE_SPINLOCK(list_lock); 45 46 static int aes_fallback_sz = 200; 47 48 #ifdef DEBUG 49 #define omap_aes_read(dd, offset) \ 50 ({ \ 51 int _read_ret; \ 52 _read_ret = __raw_readl(dd->io_base + offset); \ 53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 54 offset, _read_ret); \ 55 _read_ret; \ 56 }) 57 #else 58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 59 { 60 return __raw_readl(dd->io_base + offset); 61 } 62 #endif 63 64 #ifdef DEBUG 65 #define omap_aes_write(dd, offset, value) \ 66 do { \ 67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 68 offset, value); \ 69 __raw_writel(value, dd->io_base + offset); \ 70 } while (0) 71 #else 72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 73 u32 value) 74 { 75 __raw_writel(value, dd->io_base + offset); 76 } 77 #endif 78 79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 80 u32 value, u32 mask) 81 { 82 u32 val; 83 84 val = omap_aes_read(dd, offset); 85 val &= ~mask; 86 val |= value; 87 omap_aes_write(dd, offset, val); 88 } 89 90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 91 u32 *value, int count) 92 { 93 for (; count--; value++, offset += 4) 94 omap_aes_write(dd, offset, *value); 95 } 96 97 static int omap_aes_hw_init(struct omap_aes_dev *dd) 98 { 99 int err; 100 101 if (!(dd->flags & FLAGS_INIT)) { 102 dd->flags |= FLAGS_INIT; 103 dd->err = 0; 104 } 105 106 err = pm_runtime_get_sync(dd->dev); 107 if (err < 0) { 108 dev_err(dd->dev, "failed to get sync: %d\n", err); 109 return err; 110 } 111 112 return 0; 113 } 114 115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 116 { 117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 120 } 121 122 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 123 { 124 struct omap_aes_reqctx *rctx; 125 unsigned int key32; 126 int i, err; 127 u32 val; 128 129 err = omap_aes_hw_init(dd); 130 if (err) 131 return err; 132 133 key32 = dd->ctx->keylen / sizeof(u32); 134 135 /* RESET the key as previous HASH keys should not get affected*/ 136 if (dd->flags & FLAGS_GCM) 137 for (i = 0; i < 0x40; i = i + 4) 138 omap_aes_write(dd, i, 0x0); 139 140 for (i = 0; i < key32; i++) { 141 omap_aes_write(dd, AES_REG_KEY(dd, i), 142 __le32_to_cpu(dd->ctx->key[i])); 143 } 144 145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) 146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4); 147 148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 149 rctx = aead_request_ctx(dd->aead_req); 150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 151 } 152 153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 154 if (dd->flags & FLAGS_CBC) 155 val |= AES_REG_CTRL_CBC; 156 157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 159 160 if (dd->flags & FLAGS_GCM) 161 val |= AES_REG_CTRL_GCM; 162 163 if (dd->flags & FLAGS_ENCRYPT) 164 val |= AES_REG_CTRL_DIRECTION; 165 166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 167 168 return 0; 169 } 170 171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 172 { 173 u32 mask, val; 174 175 val = dd->pdata->dma_start; 176 177 if (dd->dma_lch_out != NULL) 178 val |= dd->pdata->dma_enable_out; 179 if (dd->dma_lch_in != NULL) 180 val |= dd->pdata->dma_enable_in; 181 182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 183 dd->pdata->dma_start; 184 185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 186 187 } 188 189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 190 { 191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 193 if (dd->flags & FLAGS_GCM) 194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 195 196 omap_aes_dma_trigger_omap2(dd, length); 197 } 198 199 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 200 { 201 u32 mask; 202 203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 204 dd->pdata->dma_start; 205 206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 207 } 208 209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 210 { 211 struct omap_aes_dev *dd; 212 213 spin_lock_bh(&list_lock); 214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 215 list_move_tail(&dd->list, &dev_list); 216 rctx->dd = dd; 217 spin_unlock_bh(&list_lock); 218 219 return dd; 220 } 221 222 static void omap_aes_dma_out_callback(void *data) 223 { 224 struct omap_aes_dev *dd = data; 225 226 /* dma_lch_out - completed */ 227 tasklet_schedule(&dd->done_task); 228 } 229 230 static int omap_aes_dma_init(struct omap_aes_dev *dd) 231 { 232 int err; 233 234 dd->dma_lch_out = NULL; 235 dd->dma_lch_in = NULL; 236 237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 238 if (IS_ERR(dd->dma_lch_in)) { 239 dev_err(dd->dev, "Unable to request in DMA channel\n"); 240 return PTR_ERR(dd->dma_lch_in); 241 } 242 243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 244 if (IS_ERR(dd->dma_lch_out)) { 245 dev_err(dd->dev, "Unable to request out DMA channel\n"); 246 err = PTR_ERR(dd->dma_lch_out); 247 goto err_dma_out; 248 } 249 250 return 0; 251 252 err_dma_out: 253 dma_release_channel(dd->dma_lch_in); 254 255 return err; 256 } 257 258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 259 { 260 if (dd->pio_only) 261 return; 262 263 dma_release_channel(dd->dma_lch_out); 264 dma_release_channel(dd->dma_lch_in); 265 } 266 267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 268 struct scatterlist *in_sg, 269 struct scatterlist *out_sg, 270 int in_sg_len, int out_sg_len) 271 { 272 struct dma_async_tx_descriptor *tx_in, *tx_out; 273 struct dma_slave_config cfg; 274 int ret; 275 276 if (dd->pio_only) { 277 scatterwalk_start(&dd->in_walk, dd->in_sg); 278 scatterwalk_start(&dd->out_walk, dd->out_sg); 279 280 /* Enable DATAIN interrupt and let it take 281 care of the rest */ 282 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 283 return 0; 284 } 285 286 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 287 288 memset(&cfg, 0, sizeof(cfg)); 289 290 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 291 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 292 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 293 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 294 cfg.src_maxburst = DST_MAXBURST; 295 cfg.dst_maxburst = DST_MAXBURST; 296 297 /* IN */ 298 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 299 if (ret) { 300 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 301 ret); 302 return ret; 303 } 304 305 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 306 DMA_MEM_TO_DEV, 307 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 308 if (!tx_in) { 309 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 310 return -EINVAL; 311 } 312 313 /* No callback necessary */ 314 tx_in->callback_param = dd; 315 316 /* OUT */ 317 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 318 if (ret) { 319 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 320 ret); 321 return ret; 322 } 323 324 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 325 DMA_DEV_TO_MEM, 326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 327 if (!tx_out) { 328 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 329 return -EINVAL; 330 } 331 332 if (dd->flags & FLAGS_GCM) 333 tx_out->callback = omap_aes_gcm_dma_out_callback; 334 else 335 tx_out->callback = omap_aes_dma_out_callback; 336 tx_out->callback_param = dd; 337 338 dmaengine_submit(tx_in); 339 dmaengine_submit(tx_out); 340 341 dma_async_issue_pending(dd->dma_lch_in); 342 dma_async_issue_pending(dd->dma_lch_out); 343 344 /* start DMA */ 345 dd->pdata->trigger(dd, dd->total); 346 347 return 0; 348 } 349 350 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 351 { 352 int err; 353 354 pr_debug("total: %d\n", dd->total); 355 356 if (!dd->pio_only) { 357 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 358 DMA_TO_DEVICE); 359 if (!err) { 360 dev_err(dd->dev, "dma_map_sg() error\n"); 361 return -EINVAL; 362 } 363 364 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 365 DMA_FROM_DEVICE); 366 if (!err) { 367 dev_err(dd->dev, "dma_map_sg() error\n"); 368 return -EINVAL; 369 } 370 } 371 372 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 373 dd->out_sg_len); 374 if (err && !dd->pio_only) { 375 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 376 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 377 DMA_FROM_DEVICE); 378 } 379 380 return err; 381 } 382 383 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 384 { 385 struct skcipher_request *req = dd->req; 386 387 pr_debug("err: %d\n", err); 388 389 crypto_finalize_skcipher_request(dd->engine, req, err); 390 391 pm_runtime_mark_last_busy(dd->dev); 392 pm_runtime_put_autosuspend(dd->dev); 393 } 394 395 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 396 { 397 pr_debug("total: %d\n", dd->total); 398 399 omap_aes_dma_stop(dd); 400 401 402 return 0; 403 } 404 405 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 406 struct skcipher_request *req) 407 { 408 if (req) 409 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 410 411 return 0; 412 } 413 414 static int omap_aes_prepare_req(struct crypto_engine *engine, 415 void *areq) 416 { 417 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 418 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 419 crypto_skcipher_reqtfm(req)); 420 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 421 struct omap_aes_dev *dd = rctx->dd; 422 int ret; 423 u16 flags; 424 425 if (!dd) 426 return -ENODEV; 427 428 /* assign new request to device */ 429 dd->req = req; 430 dd->total = req->cryptlen; 431 dd->total_save = req->cryptlen; 432 dd->in_sg = req->src; 433 dd->out_sg = req->dst; 434 dd->orig_out = req->dst; 435 436 flags = OMAP_CRYPTO_COPY_DATA; 437 if (req->src == req->dst) 438 flags |= OMAP_CRYPTO_FORCE_COPY; 439 440 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 441 dd->in_sgl, flags, 442 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 443 if (ret) 444 return ret; 445 446 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 447 &dd->out_sgl, 0, 448 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 449 if (ret) 450 return ret; 451 452 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 453 if (dd->in_sg_len < 0) 454 return dd->in_sg_len; 455 456 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 457 if (dd->out_sg_len < 0) 458 return dd->out_sg_len; 459 460 rctx->mode &= FLAGS_MODE_MASK; 461 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 462 463 dd->ctx = ctx; 464 rctx->dd = dd; 465 466 return omap_aes_write_ctrl(dd); 467 } 468 469 static int omap_aes_crypt_req(struct crypto_engine *engine, 470 void *areq) 471 { 472 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 473 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 474 struct omap_aes_dev *dd = rctx->dd; 475 476 if (!dd) 477 return -ENODEV; 478 479 return omap_aes_crypt_dma_start(dd); 480 } 481 482 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) 483 { 484 int i; 485 486 for (i = 0; i < 4; i++) 487 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); 488 } 489 490 static void omap_aes_done_task(unsigned long data) 491 { 492 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 493 494 pr_debug("enter done_task\n"); 495 496 if (!dd->pio_only) { 497 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 498 DMA_FROM_DEVICE); 499 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 500 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 501 DMA_FROM_DEVICE); 502 omap_aes_crypt_dma_stop(dd); 503 } 504 505 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save, 506 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 507 508 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save, 509 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 510 511 /* Update IV output */ 512 if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) 513 omap_aes_copy_ivout(dd, dd->req->iv); 514 515 omap_aes_finish_req(dd, 0); 516 517 pr_debug("exit\n"); 518 } 519 520 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) 521 { 522 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 523 crypto_skcipher_reqtfm(req)); 524 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 525 struct omap_aes_dev *dd; 526 int ret; 527 528 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 529 !!(mode & FLAGS_ENCRYPT), 530 !!(mode & FLAGS_CBC)); 531 532 if (req->cryptlen < aes_fallback_sz) { 533 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); 534 535 skcipher_request_set_sync_tfm(subreq, ctx->fallback); 536 skcipher_request_set_callback(subreq, req->base.flags, NULL, 537 NULL); 538 skcipher_request_set_crypt(subreq, req->src, req->dst, 539 req->cryptlen, req->iv); 540 541 if (mode & FLAGS_ENCRYPT) 542 ret = crypto_skcipher_encrypt(subreq); 543 else 544 ret = crypto_skcipher_decrypt(subreq); 545 546 skcipher_request_zero(subreq); 547 return ret; 548 } 549 dd = omap_aes_find_dev(rctx); 550 if (!dd) 551 return -ENODEV; 552 553 rctx->mode = mode; 554 555 return omap_aes_handle_queue(dd, req); 556 } 557 558 /* ********************** ALG API ************************************ */ 559 560 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 561 unsigned int keylen) 562 { 563 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 564 int ret; 565 566 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 567 keylen != AES_KEYSIZE_256) 568 return -EINVAL; 569 570 pr_debug("enter, keylen: %d\n", keylen); 571 572 memcpy(ctx->key, key, keylen); 573 ctx->keylen = keylen; 574 575 crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 576 crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 577 CRYPTO_TFM_REQ_MASK); 578 579 ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen); 580 if (!ret) 581 return 0; 582 583 return 0; 584 } 585 586 static int omap_aes_ecb_encrypt(struct skcipher_request *req) 587 { 588 return omap_aes_crypt(req, FLAGS_ENCRYPT); 589 } 590 591 static int omap_aes_ecb_decrypt(struct skcipher_request *req) 592 { 593 return omap_aes_crypt(req, 0); 594 } 595 596 static int omap_aes_cbc_encrypt(struct skcipher_request *req) 597 { 598 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 599 } 600 601 static int omap_aes_cbc_decrypt(struct skcipher_request *req) 602 { 603 return omap_aes_crypt(req, FLAGS_CBC); 604 } 605 606 static int omap_aes_ctr_encrypt(struct skcipher_request *req) 607 { 608 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 609 } 610 611 static int omap_aes_ctr_decrypt(struct skcipher_request *req) 612 { 613 return omap_aes_crypt(req, FLAGS_CTR); 614 } 615 616 static int omap_aes_prepare_req(struct crypto_engine *engine, 617 void *req); 618 static int omap_aes_crypt_req(struct crypto_engine *engine, 619 void *req); 620 621 static int omap_aes_init_tfm(struct crypto_skcipher *tfm) 622 { 623 const char *name = crypto_tfm_alg_name(&tfm->base); 624 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 625 struct crypto_sync_skcipher *blk; 626 627 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 628 if (IS_ERR(blk)) 629 return PTR_ERR(blk); 630 631 ctx->fallback = blk; 632 633 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx)); 634 635 ctx->enginectx.op.prepare_request = omap_aes_prepare_req; 636 ctx->enginectx.op.unprepare_request = NULL; 637 ctx->enginectx.op.do_one_request = omap_aes_crypt_req; 638 639 return 0; 640 } 641 642 static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) 643 { 644 struct omap_aes_dev *dd = NULL; 645 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 646 int err; 647 648 /* Find AES device, currently picks the first device */ 649 spin_lock_bh(&list_lock); 650 list_for_each_entry(dd, &dev_list, list) { 651 break; 652 } 653 spin_unlock_bh(&list_lock); 654 655 err = pm_runtime_get_sync(dd->dev); 656 if (err < 0) { 657 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", 658 __func__, err); 659 return err; 660 } 661 662 tfm->reqsize = sizeof(struct omap_aes_reqctx); 663 ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); 664 if (IS_ERR(ctx->ctr)) { 665 pr_warn("could not load aes driver for encrypting IV\n"); 666 return PTR_ERR(ctx->ctr); 667 } 668 669 return 0; 670 } 671 672 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) 673 { 674 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 675 676 if (ctx->fallback) 677 crypto_free_sync_skcipher(ctx->fallback); 678 679 ctx->fallback = NULL; 680 } 681 682 static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) 683 { 684 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 685 686 if (ctx->fallback) 687 crypto_free_sync_skcipher(ctx->fallback); 688 689 ctx->fallback = NULL; 690 691 if (ctx->ctr) 692 crypto_free_skcipher(ctx->ctr); 693 } 694 695 /* ********************** ALGS ************************************ */ 696 697 static struct skcipher_alg algs_ecb_cbc[] = { 698 { 699 .base.cra_name = "ecb(aes)", 700 .base.cra_driver_name = "ecb-aes-omap", 701 .base.cra_priority = 300, 702 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 703 CRYPTO_ALG_ASYNC | 704 CRYPTO_ALG_NEED_FALLBACK, 705 .base.cra_blocksize = AES_BLOCK_SIZE, 706 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 707 .base.cra_module = THIS_MODULE, 708 709 .min_keysize = AES_MIN_KEY_SIZE, 710 .max_keysize = AES_MAX_KEY_SIZE, 711 .setkey = omap_aes_setkey, 712 .encrypt = omap_aes_ecb_encrypt, 713 .decrypt = omap_aes_ecb_decrypt, 714 .init = omap_aes_init_tfm, 715 .exit = omap_aes_exit_tfm, 716 }, 717 { 718 .base.cra_name = "cbc(aes)", 719 .base.cra_driver_name = "cbc-aes-omap", 720 .base.cra_priority = 300, 721 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 722 CRYPTO_ALG_ASYNC | 723 CRYPTO_ALG_NEED_FALLBACK, 724 .base.cra_blocksize = AES_BLOCK_SIZE, 725 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 726 .base.cra_module = THIS_MODULE, 727 728 .min_keysize = AES_MIN_KEY_SIZE, 729 .max_keysize = AES_MAX_KEY_SIZE, 730 .ivsize = AES_BLOCK_SIZE, 731 .setkey = omap_aes_setkey, 732 .encrypt = omap_aes_cbc_encrypt, 733 .decrypt = omap_aes_cbc_decrypt, 734 .init = omap_aes_init_tfm, 735 .exit = omap_aes_exit_tfm, 736 } 737 }; 738 739 static struct skcipher_alg algs_ctr[] = { 740 { 741 .base.cra_name = "ctr(aes)", 742 .base.cra_driver_name = "ctr-aes-omap", 743 .base.cra_priority = 300, 744 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 745 CRYPTO_ALG_ASYNC | 746 CRYPTO_ALG_NEED_FALLBACK, 747 .base.cra_blocksize = AES_BLOCK_SIZE, 748 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 749 .base.cra_module = THIS_MODULE, 750 751 .min_keysize = AES_MIN_KEY_SIZE, 752 .max_keysize = AES_MAX_KEY_SIZE, 753 .ivsize = AES_BLOCK_SIZE, 754 .setkey = omap_aes_setkey, 755 .encrypt = omap_aes_ctr_encrypt, 756 .decrypt = omap_aes_ctr_decrypt, 757 .init = omap_aes_init_tfm, 758 .exit = omap_aes_exit_tfm, 759 } 760 }; 761 762 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 763 { 764 .algs_list = algs_ecb_cbc, 765 .size = ARRAY_SIZE(algs_ecb_cbc), 766 }, 767 }; 768 769 static struct aead_alg algs_aead_gcm[] = { 770 { 771 .base = { 772 .cra_name = "gcm(aes)", 773 .cra_driver_name = "gcm-aes-omap", 774 .cra_priority = 300, 775 .cra_flags = CRYPTO_ALG_ASYNC | 776 CRYPTO_ALG_KERN_DRIVER_ONLY, 777 .cra_blocksize = 1, 778 .cra_ctxsize = sizeof(struct omap_aes_ctx), 779 .cra_alignmask = 0xf, 780 .cra_module = THIS_MODULE, 781 }, 782 .init = omap_aes_gcm_cra_init, 783 .exit = omap_aes_gcm_cra_exit, 784 .ivsize = GCM_AES_IV_SIZE, 785 .maxauthsize = AES_BLOCK_SIZE, 786 .setkey = omap_aes_gcm_setkey, 787 .encrypt = omap_aes_gcm_encrypt, 788 .decrypt = omap_aes_gcm_decrypt, 789 }, 790 { 791 .base = { 792 .cra_name = "rfc4106(gcm(aes))", 793 .cra_driver_name = "rfc4106-gcm-aes-omap", 794 .cra_priority = 300, 795 .cra_flags = CRYPTO_ALG_ASYNC | 796 CRYPTO_ALG_KERN_DRIVER_ONLY, 797 .cra_blocksize = 1, 798 .cra_ctxsize = sizeof(struct omap_aes_ctx), 799 .cra_alignmask = 0xf, 800 .cra_module = THIS_MODULE, 801 }, 802 .init = omap_aes_gcm_cra_init, 803 .exit = omap_aes_gcm_cra_exit, 804 .maxauthsize = AES_BLOCK_SIZE, 805 .ivsize = GCM_RFC4106_IV_SIZE, 806 .setkey = omap_aes_4106gcm_setkey, 807 .encrypt = omap_aes_4106gcm_encrypt, 808 .decrypt = omap_aes_4106gcm_decrypt, 809 }, 810 }; 811 812 static struct omap_aes_aead_algs omap_aes_aead_info = { 813 .algs_list = algs_aead_gcm, 814 .size = ARRAY_SIZE(algs_aead_gcm), 815 }; 816 817 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 818 .algs_info = omap_aes_algs_info_ecb_cbc, 819 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 820 .trigger = omap_aes_dma_trigger_omap2, 821 .key_ofs = 0x1c, 822 .iv_ofs = 0x20, 823 .ctrl_ofs = 0x30, 824 .data_ofs = 0x34, 825 .rev_ofs = 0x44, 826 .mask_ofs = 0x48, 827 .dma_enable_in = BIT(2), 828 .dma_enable_out = BIT(3), 829 .dma_start = BIT(5), 830 .major_mask = 0xf0, 831 .major_shift = 4, 832 .minor_mask = 0x0f, 833 .minor_shift = 0, 834 }; 835 836 #ifdef CONFIG_OF 837 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 838 { 839 .algs_list = algs_ecb_cbc, 840 .size = ARRAY_SIZE(algs_ecb_cbc), 841 }, 842 { 843 .algs_list = algs_ctr, 844 .size = ARRAY_SIZE(algs_ctr), 845 }, 846 }; 847 848 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 849 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 850 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 851 .trigger = omap_aes_dma_trigger_omap2, 852 .key_ofs = 0x1c, 853 .iv_ofs = 0x20, 854 .ctrl_ofs = 0x30, 855 .data_ofs = 0x34, 856 .rev_ofs = 0x44, 857 .mask_ofs = 0x48, 858 .dma_enable_in = BIT(2), 859 .dma_enable_out = BIT(3), 860 .dma_start = BIT(5), 861 .major_mask = 0xf0, 862 .major_shift = 4, 863 .minor_mask = 0x0f, 864 .minor_shift = 0, 865 }; 866 867 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 868 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 869 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 870 .aead_algs_info = &omap_aes_aead_info, 871 .trigger = omap_aes_dma_trigger_omap4, 872 .key_ofs = 0x3c, 873 .iv_ofs = 0x40, 874 .ctrl_ofs = 0x50, 875 .data_ofs = 0x60, 876 .rev_ofs = 0x80, 877 .mask_ofs = 0x84, 878 .irq_status_ofs = 0x8c, 879 .irq_enable_ofs = 0x90, 880 .dma_enable_in = BIT(5), 881 .dma_enable_out = BIT(6), 882 .major_mask = 0x0700, 883 .major_shift = 8, 884 .minor_mask = 0x003f, 885 .minor_shift = 0, 886 }; 887 888 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 889 { 890 struct omap_aes_dev *dd = dev_id; 891 u32 status, i; 892 u32 *src, *dst; 893 894 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 895 if (status & AES_REG_IRQ_DATA_IN) { 896 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 897 898 BUG_ON(!dd->in_sg); 899 900 BUG_ON(_calc_walked(in) > dd->in_sg->length); 901 902 src = sg_virt(dd->in_sg) + _calc_walked(in); 903 904 for (i = 0; i < AES_BLOCK_WORDS; i++) { 905 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 906 907 scatterwalk_advance(&dd->in_walk, 4); 908 if (dd->in_sg->length == _calc_walked(in)) { 909 dd->in_sg = sg_next(dd->in_sg); 910 if (dd->in_sg) { 911 scatterwalk_start(&dd->in_walk, 912 dd->in_sg); 913 src = sg_virt(dd->in_sg) + 914 _calc_walked(in); 915 } 916 } else { 917 src++; 918 } 919 } 920 921 /* Clear IRQ status */ 922 status &= ~AES_REG_IRQ_DATA_IN; 923 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 924 925 /* Enable DATA_OUT interrupt */ 926 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 927 928 } else if (status & AES_REG_IRQ_DATA_OUT) { 929 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 930 931 BUG_ON(!dd->out_sg); 932 933 BUG_ON(_calc_walked(out) > dd->out_sg->length); 934 935 dst = sg_virt(dd->out_sg) + _calc_walked(out); 936 937 for (i = 0; i < AES_BLOCK_WORDS; i++) { 938 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 939 scatterwalk_advance(&dd->out_walk, 4); 940 if (dd->out_sg->length == _calc_walked(out)) { 941 dd->out_sg = sg_next(dd->out_sg); 942 if (dd->out_sg) { 943 scatterwalk_start(&dd->out_walk, 944 dd->out_sg); 945 dst = sg_virt(dd->out_sg) + 946 _calc_walked(out); 947 } 948 } else { 949 dst++; 950 } 951 } 952 953 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 954 955 /* Clear IRQ status */ 956 status &= ~AES_REG_IRQ_DATA_OUT; 957 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 958 959 if (!dd->total) 960 /* All bytes read! */ 961 tasklet_schedule(&dd->done_task); 962 else 963 /* Enable DATA_IN interrupt for next block */ 964 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 965 } 966 967 return IRQ_HANDLED; 968 } 969 970 static const struct of_device_id omap_aes_of_match[] = { 971 { 972 .compatible = "ti,omap2-aes", 973 .data = &omap_aes_pdata_omap2, 974 }, 975 { 976 .compatible = "ti,omap3-aes", 977 .data = &omap_aes_pdata_omap3, 978 }, 979 { 980 .compatible = "ti,omap4-aes", 981 .data = &omap_aes_pdata_omap4, 982 }, 983 {}, 984 }; 985 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 986 987 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 988 struct device *dev, struct resource *res) 989 { 990 struct device_node *node = dev->of_node; 991 int err = 0; 992 993 dd->pdata = of_device_get_match_data(dev); 994 if (!dd->pdata) { 995 dev_err(dev, "no compatible OF match\n"); 996 err = -EINVAL; 997 goto err; 998 } 999 1000 err = of_address_to_resource(node, 0, res); 1001 if (err < 0) { 1002 dev_err(dev, "can't translate OF node address\n"); 1003 err = -EINVAL; 1004 goto err; 1005 } 1006 1007 err: 1008 return err; 1009 } 1010 #else 1011 static const struct of_device_id omap_aes_of_match[] = { 1012 {}, 1013 }; 1014 1015 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1016 struct device *dev, struct resource *res) 1017 { 1018 return -EINVAL; 1019 } 1020 #endif 1021 1022 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 1023 struct platform_device *pdev, struct resource *res) 1024 { 1025 struct device *dev = &pdev->dev; 1026 struct resource *r; 1027 int err = 0; 1028 1029 /* Get the base address */ 1030 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1031 if (!r) { 1032 dev_err(dev, "no MEM resource info\n"); 1033 err = -ENODEV; 1034 goto err; 1035 } 1036 memcpy(res, r, sizeof(*res)); 1037 1038 /* Only OMAP2/3 can be non-DT */ 1039 dd->pdata = &omap_aes_pdata_omap2; 1040 1041 err: 1042 return err; 1043 } 1044 1045 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1046 char *buf) 1047 { 1048 return sprintf(buf, "%d\n", aes_fallback_sz); 1049 } 1050 1051 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1052 const char *buf, size_t size) 1053 { 1054 ssize_t status; 1055 long value; 1056 1057 status = kstrtol(buf, 0, &value); 1058 if (status) 1059 return status; 1060 1061 /* HW accelerator only works with buffers > 9 */ 1062 if (value < 9) { 1063 dev_err(dev, "minimum fallback size 9\n"); 1064 return -EINVAL; 1065 } 1066 1067 aes_fallback_sz = value; 1068 1069 return size; 1070 } 1071 1072 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1073 char *buf) 1074 { 1075 struct omap_aes_dev *dd = dev_get_drvdata(dev); 1076 1077 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); 1078 } 1079 1080 static ssize_t queue_len_store(struct device *dev, 1081 struct device_attribute *attr, const char *buf, 1082 size_t size) 1083 { 1084 struct omap_aes_dev *dd; 1085 ssize_t status; 1086 long value; 1087 unsigned long flags; 1088 1089 status = kstrtol(buf, 0, &value); 1090 if (status) 1091 return status; 1092 1093 if (value < 1) 1094 return -EINVAL; 1095 1096 /* 1097 * Changing the queue size in fly is safe, if size becomes smaller 1098 * than current size, it will just not accept new entries until 1099 * it has shrank enough. 1100 */ 1101 spin_lock_bh(&list_lock); 1102 list_for_each_entry(dd, &dev_list, list) { 1103 spin_lock_irqsave(&dd->lock, flags); 1104 dd->engine->queue.max_qlen = value; 1105 dd->aead_queue.base.max_qlen = value; 1106 spin_unlock_irqrestore(&dd->lock, flags); 1107 } 1108 spin_unlock_bh(&list_lock); 1109 1110 return size; 1111 } 1112 1113 static DEVICE_ATTR_RW(queue_len); 1114 static DEVICE_ATTR_RW(fallback); 1115 1116 static struct attribute *omap_aes_attrs[] = { 1117 &dev_attr_queue_len.attr, 1118 &dev_attr_fallback.attr, 1119 NULL, 1120 }; 1121 1122 static struct attribute_group omap_aes_attr_group = { 1123 .attrs = omap_aes_attrs, 1124 }; 1125 1126 static int omap_aes_probe(struct platform_device *pdev) 1127 { 1128 struct device *dev = &pdev->dev; 1129 struct omap_aes_dev *dd; 1130 struct skcipher_alg *algp; 1131 struct aead_alg *aalg; 1132 struct resource res; 1133 int err = -ENOMEM, i, j, irq = -1; 1134 u32 reg; 1135 1136 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1137 if (dd == NULL) { 1138 dev_err(dev, "unable to alloc data struct.\n"); 1139 goto err_data; 1140 } 1141 dd->dev = dev; 1142 platform_set_drvdata(pdev, dd); 1143 1144 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1145 1146 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1147 omap_aes_get_res_pdev(dd, pdev, &res); 1148 if (err) 1149 goto err_res; 1150 1151 dd->io_base = devm_ioremap_resource(dev, &res); 1152 if (IS_ERR(dd->io_base)) { 1153 err = PTR_ERR(dd->io_base); 1154 goto err_res; 1155 } 1156 dd->phys_base = res.start; 1157 1158 pm_runtime_use_autosuspend(dev); 1159 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1160 1161 pm_runtime_enable(dev); 1162 err = pm_runtime_get_sync(dev); 1163 if (err < 0) { 1164 dev_err(dev, "%s: failed to get_sync(%d)\n", 1165 __func__, err); 1166 goto err_res; 1167 } 1168 1169 omap_aes_dma_stop(dd); 1170 1171 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1172 1173 pm_runtime_put_sync(dev); 1174 1175 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1176 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1177 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1178 1179 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1180 1181 err = omap_aes_dma_init(dd); 1182 if (err == -EPROBE_DEFER) { 1183 goto err_irq; 1184 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1185 dd->pio_only = 1; 1186 1187 irq = platform_get_irq(pdev, 0); 1188 if (irq < 0) { 1189 err = irq; 1190 goto err_irq; 1191 } 1192 1193 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1194 dev_name(dev), dd); 1195 if (err) { 1196 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1197 goto err_irq; 1198 } 1199 } 1200 1201 spin_lock_init(&dd->lock); 1202 1203 INIT_LIST_HEAD(&dd->list); 1204 spin_lock(&list_lock); 1205 list_add_tail(&dd->list, &dev_list); 1206 spin_unlock(&list_lock); 1207 1208 /* Initialize crypto engine */ 1209 dd->engine = crypto_engine_alloc_init(dev, 1); 1210 if (!dd->engine) { 1211 err = -ENOMEM; 1212 goto err_engine; 1213 } 1214 1215 err = crypto_engine_start(dd->engine); 1216 if (err) 1217 goto err_engine; 1218 1219 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1220 if (!dd->pdata->algs_info[i].registered) { 1221 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1222 algp = &dd->pdata->algs_info[i].algs_list[j]; 1223 1224 pr_debug("reg alg: %s\n", algp->base.cra_name); 1225 1226 err = crypto_register_skcipher(algp); 1227 if (err) 1228 goto err_algs; 1229 1230 dd->pdata->algs_info[i].registered++; 1231 } 1232 } 1233 } 1234 1235 if (dd->pdata->aead_algs_info && 1236 !dd->pdata->aead_algs_info->registered) { 1237 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1238 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1239 1240 pr_debug("reg alg: %s\n", aalg->base.cra_name); 1241 1242 err = crypto_register_aead(aalg); 1243 if (err) 1244 goto err_aead_algs; 1245 1246 dd->pdata->aead_algs_info->registered++; 1247 } 1248 } 1249 1250 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); 1251 if (err) { 1252 dev_err(dev, "could not create sysfs device attrs\n"); 1253 goto err_aead_algs; 1254 } 1255 1256 return 0; 1257 err_aead_algs: 1258 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1259 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1260 crypto_unregister_aead(aalg); 1261 } 1262 err_algs: 1263 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1264 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1265 crypto_unregister_skcipher( 1266 &dd->pdata->algs_info[i].algs_list[j]); 1267 1268 err_engine: 1269 if (dd->engine) 1270 crypto_engine_exit(dd->engine); 1271 1272 omap_aes_dma_cleanup(dd); 1273 err_irq: 1274 tasklet_kill(&dd->done_task); 1275 pm_runtime_disable(dev); 1276 err_res: 1277 dd = NULL; 1278 err_data: 1279 dev_err(dev, "initialization failed.\n"); 1280 return err; 1281 } 1282 1283 static int omap_aes_remove(struct platform_device *pdev) 1284 { 1285 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1286 struct aead_alg *aalg; 1287 int i, j; 1288 1289 if (!dd) 1290 return -ENODEV; 1291 1292 spin_lock(&list_lock); 1293 list_del(&dd->list); 1294 spin_unlock(&list_lock); 1295 1296 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1297 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1298 crypto_unregister_skcipher( 1299 &dd->pdata->algs_info[i].algs_list[j]); 1300 1301 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { 1302 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1303 crypto_unregister_aead(aalg); 1304 } 1305 1306 crypto_engine_exit(dd->engine); 1307 1308 tasklet_kill(&dd->done_task); 1309 omap_aes_dma_cleanup(dd); 1310 pm_runtime_disable(dd->dev); 1311 1312 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group); 1313 1314 return 0; 1315 } 1316 1317 #ifdef CONFIG_PM_SLEEP 1318 static int omap_aes_suspend(struct device *dev) 1319 { 1320 pm_runtime_put_sync(dev); 1321 return 0; 1322 } 1323 1324 static int omap_aes_resume(struct device *dev) 1325 { 1326 pm_runtime_get_sync(dev); 1327 return 0; 1328 } 1329 #endif 1330 1331 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1332 1333 static struct platform_driver omap_aes_driver = { 1334 .probe = omap_aes_probe, 1335 .remove = omap_aes_remove, 1336 .driver = { 1337 .name = "omap-aes", 1338 .pm = &omap_aes_pm_ops, 1339 .of_match_table = omap_aes_of_match, 1340 }, 1341 }; 1342 1343 module_platform_driver(omap_aes_driver); 1344 1345 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1346 MODULE_LICENSE("GPL v2"); 1347 MODULE_AUTHOR("Dmitry Kasatkin"); 1348 1349