1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP AES HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 */ 15 16 #define pr_fmt(fmt) "%20s: " fmt, __func__ 17 #define prn(num) pr_debug(#num "=%d\n", num) 18 #define prx(num) pr_debug(#num "=%x\n", num) 19 20 #include <linux/err.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/kernel.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/io.h> 34 #include <linux/crypto.h> 35 #include <linux/interrupt.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/aes.h> 38 #include <crypto/engine.h> 39 #include <crypto/internal/skcipher.h> 40 41 #include "omap-crypto.h" 42 #include "omap-aes.h" 43 44 /* keep registered devices data here */ 45 static LIST_HEAD(dev_list); 46 static DEFINE_SPINLOCK(list_lock); 47 48 #ifdef DEBUG 49 #define omap_aes_read(dd, offset) \ 50 ({ \ 51 int _read_ret; \ 52 _read_ret = __raw_readl(dd->io_base + offset); \ 53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 54 offset, _read_ret); \ 55 _read_ret; \ 56 }) 57 #else 58 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 59 { 60 return __raw_readl(dd->io_base + offset); 61 } 62 #endif 63 64 #ifdef DEBUG 65 #define omap_aes_write(dd, offset, value) \ 66 do { \ 67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 68 offset, value); \ 69 __raw_writel(value, dd->io_base + offset); \ 70 } while (0) 71 #else 72 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 73 u32 value) 74 { 75 __raw_writel(value, dd->io_base + offset); 76 } 77 #endif 78 79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 80 u32 value, u32 mask) 81 { 82 u32 val; 83 84 val = omap_aes_read(dd, offset); 85 val &= ~mask; 86 val |= value; 87 omap_aes_write(dd, offset, val); 88 } 89 90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 91 u32 *value, int count) 92 { 93 for (; count--; value++, offset += 4) 94 omap_aes_write(dd, offset, *value); 95 } 96 97 static int omap_aes_hw_init(struct omap_aes_dev *dd) 98 { 99 int err; 100 101 if (!(dd->flags & FLAGS_INIT)) { 102 dd->flags |= FLAGS_INIT; 103 dd->err = 0; 104 } 105 106 err = pm_runtime_get_sync(dd->dev); 107 if (err < 0) { 108 dev_err(dd->dev, "failed to get sync: %d\n", err); 109 return err; 110 } 111 112 return 0; 113 } 114 115 static int omap_aes_write_ctrl(struct omap_aes_dev *dd) 116 { 117 unsigned int key32; 118 int i, err; 119 u32 val; 120 121 err = omap_aes_hw_init(dd); 122 if (err) 123 return err; 124 125 key32 = dd->ctx->keylen / sizeof(u32); 126 127 /* it seems a key should always be set even if it has not changed */ 128 for (i = 0; i < key32; i++) { 129 omap_aes_write(dd, AES_REG_KEY(dd, i), 130 __le32_to_cpu(dd->ctx->key[i])); 131 } 132 133 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) 134 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); 135 136 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 137 if (dd->flags & FLAGS_CBC) 138 val |= AES_REG_CTRL_CBC; 139 if (dd->flags & FLAGS_CTR) 140 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 141 142 if (dd->flags & FLAGS_ENCRYPT) 143 val |= AES_REG_CTRL_DIRECTION; 144 145 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 146 147 return 0; 148 } 149 150 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 151 { 152 u32 mask, val; 153 154 val = dd->pdata->dma_start; 155 156 if (dd->dma_lch_out != NULL) 157 val |= dd->pdata->dma_enable_out; 158 if (dd->dma_lch_in != NULL) 159 val |= dd->pdata->dma_enable_in; 160 161 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 162 dd->pdata->dma_start; 163 164 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 165 166 } 167 168 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 169 { 170 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 171 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 172 173 omap_aes_dma_trigger_omap2(dd, length); 174 } 175 176 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 177 { 178 u32 mask; 179 180 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 181 dd->pdata->dma_start; 182 183 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 184 } 185 186 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 187 { 188 struct omap_aes_dev *dd; 189 190 spin_lock_bh(&list_lock); 191 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 192 list_move_tail(&dd->list, &dev_list); 193 rctx->dd = dd; 194 spin_unlock_bh(&list_lock); 195 196 return dd; 197 } 198 199 static void omap_aes_dma_out_callback(void *data) 200 { 201 struct omap_aes_dev *dd = data; 202 203 /* dma_lch_out - completed */ 204 tasklet_schedule(&dd->done_task); 205 } 206 207 static int omap_aes_dma_init(struct omap_aes_dev *dd) 208 { 209 int err; 210 211 dd->dma_lch_out = NULL; 212 dd->dma_lch_in = NULL; 213 214 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 215 if (IS_ERR(dd->dma_lch_in)) { 216 dev_err(dd->dev, "Unable to request in DMA channel\n"); 217 return PTR_ERR(dd->dma_lch_in); 218 } 219 220 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 221 if (IS_ERR(dd->dma_lch_out)) { 222 dev_err(dd->dev, "Unable to request out DMA channel\n"); 223 err = PTR_ERR(dd->dma_lch_out); 224 goto err_dma_out; 225 } 226 227 return 0; 228 229 err_dma_out: 230 dma_release_channel(dd->dma_lch_in); 231 232 return err; 233 } 234 235 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 236 { 237 if (dd->pio_only) 238 return; 239 240 dma_release_channel(dd->dma_lch_out); 241 dma_release_channel(dd->dma_lch_in); 242 } 243 244 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 245 struct scatterlist *in_sg, 246 struct scatterlist *out_sg, 247 int in_sg_len, int out_sg_len) 248 { 249 struct dma_async_tx_descriptor *tx_in, *tx_out; 250 struct dma_slave_config cfg; 251 int ret; 252 253 if (dd->pio_only) { 254 scatterwalk_start(&dd->in_walk, dd->in_sg); 255 scatterwalk_start(&dd->out_walk, dd->out_sg); 256 257 /* Enable DATAIN interrupt and let it take 258 care of the rest */ 259 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 260 return 0; 261 } 262 263 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 264 265 memset(&cfg, 0, sizeof(cfg)); 266 267 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 268 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 269 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 270 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 271 cfg.src_maxburst = DST_MAXBURST; 272 cfg.dst_maxburst = DST_MAXBURST; 273 274 /* IN */ 275 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 276 if (ret) { 277 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 278 ret); 279 return ret; 280 } 281 282 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 283 DMA_MEM_TO_DEV, 284 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 285 if (!tx_in) { 286 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 287 return -EINVAL; 288 } 289 290 /* No callback necessary */ 291 tx_in->callback_param = dd; 292 293 /* OUT */ 294 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 295 if (ret) { 296 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 297 ret); 298 return ret; 299 } 300 301 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 302 DMA_DEV_TO_MEM, 303 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 304 if (!tx_out) { 305 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 306 return -EINVAL; 307 } 308 309 tx_out->callback = omap_aes_dma_out_callback; 310 tx_out->callback_param = dd; 311 312 dmaengine_submit(tx_in); 313 dmaengine_submit(tx_out); 314 315 dma_async_issue_pending(dd->dma_lch_in); 316 dma_async_issue_pending(dd->dma_lch_out); 317 318 /* start DMA */ 319 dd->pdata->trigger(dd, dd->total); 320 321 return 0; 322 } 323 324 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 325 { 326 int err; 327 328 pr_debug("total: %d\n", dd->total); 329 330 if (!dd->pio_only) { 331 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 332 DMA_TO_DEVICE); 333 if (!err) { 334 dev_err(dd->dev, "dma_map_sg() error\n"); 335 return -EINVAL; 336 } 337 338 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 339 DMA_FROM_DEVICE); 340 if (!err) { 341 dev_err(dd->dev, "dma_map_sg() error\n"); 342 return -EINVAL; 343 } 344 } 345 346 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 347 dd->out_sg_len); 348 if (err && !dd->pio_only) { 349 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 350 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 351 DMA_FROM_DEVICE); 352 } 353 354 return err; 355 } 356 357 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 358 { 359 struct ablkcipher_request *req = dd->req; 360 361 pr_debug("err: %d\n", err); 362 363 crypto_finalize_cipher_request(dd->engine, req, err); 364 365 pm_runtime_mark_last_busy(dd->dev); 366 pm_runtime_put_autosuspend(dd->dev); 367 } 368 369 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 370 { 371 pr_debug("total: %d\n", dd->total); 372 373 omap_aes_dma_stop(dd); 374 375 376 return 0; 377 } 378 379 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 380 struct ablkcipher_request *req) 381 { 382 if (req) 383 return crypto_transfer_cipher_request_to_engine(dd->engine, req); 384 385 return 0; 386 } 387 388 static int omap_aes_prepare_req(struct crypto_engine *engine, 389 struct ablkcipher_request *req) 390 { 391 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 392 crypto_ablkcipher_reqtfm(req)); 393 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 394 struct omap_aes_dev *dd = rctx->dd; 395 int ret; 396 u16 flags; 397 398 if (!dd) 399 return -ENODEV; 400 401 /* assign new request to device */ 402 dd->req = req; 403 dd->total = req->nbytes; 404 dd->total_save = req->nbytes; 405 dd->in_sg = req->src; 406 dd->out_sg = req->dst; 407 dd->orig_out = req->dst; 408 409 flags = OMAP_CRYPTO_COPY_DATA; 410 if (req->src == req->dst) 411 flags |= OMAP_CRYPTO_FORCE_COPY; 412 413 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 414 &dd->in_sgl, flags, 415 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 416 if (ret) 417 return ret; 418 419 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 420 &dd->out_sgl, 0, 421 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 422 if (ret) 423 return ret; 424 425 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 426 if (dd->in_sg_len < 0) 427 return dd->in_sg_len; 428 429 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 430 if (dd->out_sg_len < 0) 431 return dd->out_sg_len; 432 433 rctx->mode &= FLAGS_MODE_MASK; 434 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 435 436 dd->ctx = ctx; 437 rctx->dd = dd; 438 439 return omap_aes_write_ctrl(dd); 440 } 441 442 static int omap_aes_crypt_req(struct crypto_engine *engine, 443 struct ablkcipher_request *req) 444 { 445 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 446 struct omap_aes_dev *dd = rctx->dd; 447 448 if (!dd) 449 return -ENODEV; 450 451 return omap_aes_crypt_dma_start(dd); 452 } 453 454 static void omap_aes_done_task(unsigned long data) 455 { 456 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 457 458 pr_debug("enter done_task\n"); 459 460 if (!dd->pio_only) { 461 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 462 DMA_FROM_DEVICE); 463 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 464 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 465 DMA_FROM_DEVICE); 466 omap_aes_crypt_dma_stop(dd); 467 } 468 469 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save, 470 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 471 472 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, 473 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 474 475 omap_aes_finish_req(dd, 0); 476 477 pr_debug("exit\n"); 478 } 479 480 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) 481 { 482 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 483 crypto_ablkcipher_reqtfm(req)); 484 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 485 struct omap_aes_dev *dd; 486 int ret; 487 488 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 489 !!(mode & FLAGS_ENCRYPT), 490 !!(mode & FLAGS_CBC)); 491 492 if (req->nbytes < 200) { 493 SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); 494 495 skcipher_request_set_tfm(subreq, ctx->fallback); 496 skcipher_request_set_callback(subreq, req->base.flags, NULL, 497 NULL); 498 skcipher_request_set_crypt(subreq, req->src, req->dst, 499 req->nbytes, req->info); 500 501 if (mode & FLAGS_ENCRYPT) 502 ret = crypto_skcipher_encrypt(subreq); 503 else 504 ret = crypto_skcipher_decrypt(subreq); 505 506 skcipher_request_zero(subreq); 507 return ret; 508 } 509 dd = omap_aes_find_dev(rctx); 510 if (!dd) 511 return -ENODEV; 512 513 rctx->mode = mode; 514 515 return omap_aes_handle_queue(dd, req); 516 } 517 518 /* ********************** ALG API ************************************ */ 519 520 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 521 unsigned int keylen) 522 { 523 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 524 int ret; 525 526 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 527 keylen != AES_KEYSIZE_256) 528 return -EINVAL; 529 530 pr_debug("enter, keylen: %d\n", keylen); 531 532 memcpy(ctx->key, key, keylen); 533 ctx->keylen = keylen; 534 535 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 536 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 537 CRYPTO_TFM_REQ_MASK); 538 539 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); 540 if (!ret) 541 return 0; 542 543 return 0; 544 } 545 546 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) 547 { 548 return omap_aes_crypt(req, FLAGS_ENCRYPT); 549 } 550 551 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) 552 { 553 return omap_aes_crypt(req, 0); 554 } 555 556 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) 557 { 558 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 559 } 560 561 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) 562 { 563 return omap_aes_crypt(req, FLAGS_CBC); 564 } 565 566 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) 567 { 568 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 569 } 570 571 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) 572 { 573 return omap_aes_crypt(req, FLAGS_CTR); 574 } 575 576 static int omap_aes_cra_init(struct crypto_tfm *tfm) 577 { 578 const char *name = crypto_tfm_alg_name(tfm); 579 const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; 580 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 581 struct crypto_skcipher *blk; 582 583 blk = crypto_alloc_skcipher(name, 0, flags); 584 if (IS_ERR(blk)) 585 return PTR_ERR(blk); 586 587 ctx->fallback = blk; 588 589 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); 590 591 return 0; 592 } 593 594 static void omap_aes_cra_exit(struct crypto_tfm *tfm) 595 { 596 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 597 598 if (ctx->fallback) 599 crypto_free_skcipher(ctx->fallback); 600 601 ctx->fallback = NULL; 602 } 603 604 /* ********************** ALGS ************************************ */ 605 606 static struct crypto_alg algs_ecb_cbc[] = { 607 { 608 .cra_name = "ecb(aes)", 609 .cra_driver_name = "ecb-aes-omap", 610 .cra_priority = 300, 611 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 612 CRYPTO_ALG_KERN_DRIVER_ONLY | 613 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 614 .cra_blocksize = AES_BLOCK_SIZE, 615 .cra_ctxsize = sizeof(struct omap_aes_ctx), 616 .cra_alignmask = 0, 617 .cra_type = &crypto_ablkcipher_type, 618 .cra_module = THIS_MODULE, 619 .cra_init = omap_aes_cra_init, 620 .cra_exit = omap_aes_cra_exit, 621 .cra_u.ablkcipher = { 622 .min_keysize = AES_MIN_KEY_SIZE, 623 .max_keysize = AES_MAX_KEY_SIZE, 624 .setkey = omap_aes_setkey, 625 .encrypt = omap_aes_ecb_encrypt, 626 .decrypt = omap_aes_ecb_decrypt, 627 } 628 }, 629 { 630 .cra_name = "cbc(aes)", 631 .cra_driver_name = "cbc-aes-omap", 632 .cra_priority = 300, 633 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 634 CRYPTO_ALG_KERN_DRIVER_ONLY | 635 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 636 .cra_blocksize = AES_BLOCK_SIZE, 637 .cra_ctxsize = sizeof(struct omap_aes_ctx), 638 .cra_alignmask = 0, 639 .cra_type = &crypto_ablkcipher_type, 640 .cra_module = THIS_MODULE, 641 .cra_init = omap_aes_cra_init, 642 .cra_exit = omap_aes_cra_exit, 643 .cra_u.ablkcipher = { 644 .min_keysize = AES_MIN_KEY_SIZE, 645 .max_keysize = AES_MAX_KEY_SIZE, 646 .ivsize = AES_BLOCK_SIZE, 647 .setkey = omap_aes_setkey, 648 .encrypt = omap_aes_cbc_encrypt, 649 .decrypt = omap_aes_cbc_decrypt, 650 } 651 } 652 }; 653 654 static struct crypto_alg algs_ctr[] = { 655 { 656 .cra_name = "ctr(aes)", 657 .cra_driver_name = "ctr-aes-omap", 658 .cra_priority = 300, 659 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 660 CRYPTO_ALG_KERN_DRIVER_ONLY | 661 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 662 .cra_blocksize = AES_BLOCK_SIZE, 663 .cra_ctxsize = sizeof(struct omap_aes_ctx), 664 .cra_alignmask = 0, 665 .cra_type = &crypto_ablkcipher_type, 666 .cra_module = THIS_MODULE, 667 .cra_init = omap_aes_cra_init, 668 .cra_exit = omap_aes_cra_exit, 669 .cra_u.ablkcipher = { 670 .min_keysize = AES_MIN_KEY_SIZE, 671 .max_keysize = AES_MAX_KEY_SIZE, 672 .geniv = "eseqiv", 673 .ivsize = AES_BLOCK_SIZE, 674 .setkey = omap_aes_setkey, 675 .encrypt = omap_aes_ctr_encrypt, 676 .decrypt = omap_aes_ctr_decrypt, 677 } 678 } , 679 }; 680 681 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 682 { 683 .algs_list = algs_ecb_cbc, 684 .size = ARRAY_SIZE(algs_ecb_cbc), 685 }, 686 }; 687 688 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 689 .algs_info = omap_aes_algs_info_ecb_cbc, 690 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 691 .trigger = omap_aes_dma_trigger_omap2, 692 .key_ofs = 0x1c, 693 .iv_ofs = 0x20, 694 .ctrl_ofs = 0x30, 695 .data_ofs = 0x34, 696 .rev_ofs = 0x44, 697 .mask_ofs = 0x48, 698 .dma_enable_in = BIT(2), 699 .dma_enable_out = BIT(3), 700 .dma_start = BIT(5), 701 .major_mask = 0xf0, 702 .major_shift = 4, 703 .minor_mask = 0x0f, 704 .minor_shift = 0, 705 }; 706 707 #ifdef CONFIG_OF 708 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 709 { 710 .algs_list = algs_ecb_cbc, 711 .size = ARRAY_SIZE(algs_ecb_cbc), 712 }, 713 { 714 .algs_list = algs_ctr, 715 .size = ARRAY_SIZE(algs_ctr), 716 }, 717 }; 718 719 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 720 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 721 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 722 .trigger = omap_aes_dma_trigger_omap2, 723 .key_ofs = 0x1c, 724 .iv_ofs = 0x20, 725 .ctrl_ofs = 0x30, 726 .data_ofs = 0x34, 727 .rev_ofs = 0x44, 728 .mask_ofs = 0x48, 729 .dma_enable_in = BIT(2), 730 .dma_enable_out = BIT(3), 731 .dma_start = BIT(5), 732 .major_mask = 0xf0, 733 .major_shift = 4, 734 .minor_mask = 0x0f, 735 .minor_shift = 0, 736 }; 737 738 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 739 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 740 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 741 .trigger = omap_aes_dma_trigger_omap4, 742 .key_ofs = 0x3c, 743 .iv_ofs = 0x40, 744 .ctrl_ofs = 0x50, 745 .data_ofs = 0x60, 746 .rev_ofs = 0x80, 747 .mask_ofs = 0x84, 748 .irq_status_ofs = 0x8c, 749 .irq_enable_ofs = 0x90, 750 .dma_enable_in = BIT(5), 751 .dma_enable_out = BIT(6), 752 .major_mask = 0x0700, 753 .major_shift = 8, 754 .minor_mask = 0x003f, 755 .minor_shift = 0, 756 }; 757 758 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 759 { 760 struct omap_aes_dev *dd = dev_id; 761 u32 status, i; 762 u32 *src, *dst; 763 764 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 765 if (status & AES_REG_IRQ_DATA_IN) { 766 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 767 768 BUG_ON(!dd->in_sg); 769 770 BUG_ON(_calc_walked(in) > dd->in_sg->length); 771 772 src = sg_virt(dd->in_sg) + _calc_walked(in); 773 774 for (i = 0; i < AES_BLOCK_WORDS; i++) { 775 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 776 777 scatterwalk_advance(&dd->in_walk, 4); 778 if (dd->in_sg->length == _calc_walked(in)) { 779 dd->in_sg = sg_next(dd->in_sg); 780 if (dd->in_sg) { 781 scatterwalk_start(&dd->in_walk, 782 dd->in_sg); 783 src = sg_virt(dd->in_sg) + 784 _calc_walked(in); 785 } 786 } else { 787 src++; 788 } 789 } 790 791 /* Clear IRQ status */ 792 status &= ~AES_REG_IRQ_DATA_IN; 793 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 794 795 /* Enable DATA_OUT interrupt */ 796 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 797 798 } else if (status & AES_REG_IRQ_DATA_OUT) { 799 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 800 801 BUG_ON(!dd->out_sg); 802 803 BUG_ON(_calc_walked(out) > dd->out_sg->length); 804 805 dst = sg_virt(dd->out_sg) + _calc_walked(out); 806 807 for (i = 0; i < AES_BLOCK_WORDS; i++) { 808 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 809 scatterwalk_advance(&dd->out_walk, 4); 810 if (dd->out_sg->length == _calc_walked(out)) { 811 dd->out_sg = sg_next(dd->out_sg); 812 if (dd->out_sg) { 813 scatterwalk_start(&dd->out_walk, 814 dd->out_sg); 815 dst = sg_virt(dd->out_sg) + 816 _calc_walked(out); 817 } 818 } else { 819 dst++; 820 } 821 } 822 823 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 824 825 /* Clear IRQ status */ 826 status &= ~AES_REG_IRQ_DATA_OUT; 827 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 828 829 if (!dd->total) 830 /* All bytes read! */ 831 tasklet_schedule(&dd->done_task); 832 else 833 /* Enable DATA_IN interrupt for next block */ 834 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 835 } 836 837 return IRQ_HANDLED; 838 } 839 840 static const struct of_device_id omap_aes_of_match[] = { 841 { 842 .compatible = "ti,omap2-aes", 843 .data = &omap_aes_pdata_omap2, 844 }, 845 { 846 .compatible = "ti,omap3-aes", 847 .data = &omap_aes_pdata_omap3, 848 }, 849 { 850 .compatible = "ti,omap4-aes", 851 .data = &omap_aes_pdata_omap4, 852 }, 853 {}, 854 }; 855 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 856 857 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 858 struct device *dev, struct resource *res) 859 { 860 struct device_node *node = dev->of_node; 861 const struct of_device_id *match; 862 int err = 0; 863 864 match = of_match_device(of_match_ptr(omap_aes_of_match), dev); 865 if (!match) { 866 dev_err(dev, "no compatible OF match\n"); 867 err = -EINVAL; 868 goto err; 869 } 870 871 err = of_address_to_resource(node, 0, res); 872 if (err < 0) { 873 dev_err(dev, "can't translate OF node address\n"); 874 err = -EINVAL; 875 goto err; 876 } 877 878 dd->pdata = match->data; 879 880 err: 881 return err; 882 } 883 #else 884 static const struct of_device_id omap_aes_of_match[] = { 885 {}, 886 }; 887 888 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 889 struct device *dev, struct resource *res) 890 { 891 return -EINVAL; 892 } 893 #endif 894 895 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 896 struct platform_device *pdev, struct resource *res) 897 { 898 struct device *dev = &pdev->dev; 899 struct resource *r; 900 int err = 0; 901 902 /* Get the base address */ 903 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904 if (!r) { 905 dev_err(dev, "no MEM resource info\n"); 906 err = -ENODEV; 907 goto err; 908 } 909 memcpy(res, r, sizeof(*res)); 910 911 /* Only OMAP2/3 can be non-DT */ 912 dd->pdata = &omap_aes_pdata_omap2; 913 914 err: 915 return err; 916 } 917 918 static int omap_aes_probe(struct platform_device *pdev) 919 { 920 struct device *dev = &pdev->dev; 921 struct omap_aes_dev *dd; 922 struct crypto_alg *algp; 923 struct resource res; 924 int err = -ENOMEM, i, j, irq = -1; 925 u32 reg; 926 927 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 928 if (dd == NULL) { 929 dev_err(dev, "unable to alloc data struct.\n"); 930 goto err_data; 931 } 932 dd->dev = dev; 933 platform_set_drvdata(pdev, dd); 934 935 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 936 omap_aes_get_res_pdev(dd, pdev, &res); 937 if (err) 938 goto err_res; 939 940 dd->io_base = devm_ioremap_resource(dev, &res); 941 if (IS_ERR(dd->io_base)) { 942 err = PTR_ERR(dd->io_base); 943 goto err_res; 944 } 945 dd->phys_base = res.start; 946 947 pm_runtime_use_autosuspend(dev); 948 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 949 950 pm_runtime_enable(dev); 951 err = pm_runtime_get_sync(dev); 952 if (err < 0) { 953 dev_err(dev, "%s: failed to get_sync(%d)\n", 954 __func__, err); 955 goto err_res; 956 } 957 958 omap_aes_dma_stop(dd); 959 960 reg = omap_aes_read(dd, AES_REG_REV(dd)); 961 962 pm_runtime_put_sync(dev); 963 964 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 965 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 966 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 967 968 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 969 970 err = omap_aes_dma_init(dd); 971 if (err == -EPROBE_DEFER) { 972 goto err_irq; 973 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 974 dd->pio_only = 1; 975 976 irq = platform_get_irq(pdev, 0); 977 if (irq < 0) { 978 dev_err(dev, "can't get IRQ resource\n"); 979 goto err_irq; 980 } 981 982 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 983 dev_name(dev), dd); 984 if (err) { 985 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 986 goto err_irq; 987 } 988 } 989 990 991 INIT_LIST_HEAD(&dd->list); 992 spin_lock(&list_lock); 993 list_add_tail(&dd->list, &dev_list); 994 spin_unlock(&list_lock); 995 996 /* Initialize crypto engine */ 997 dd->engine = crypto_engine_alloc_init(dev, 1); 998 if (!dd->engine) { 999 err = -ENOMEM; 1000 goto err_engine; 1001 } 1002 1003 dd->engine->prepare_cipher_request = omap_aes_prepare_req; 1004 dd->engine->cipher_one_request = omap_aes_crypt_req; 1005 err = crypto_engine_start(dd->engine); 1006 if (err) 1007 goto err_engine; 1008 1009 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1010 if (!dd->pdata->algs_info[i].registered) { 1011 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1012 algp = &dd->pdata->algs_info[i].algs_list[j]; 1013 1014 pr_debug("reg alg: %s\n", algp->cra_name); 1015 INIT_LIST_HEAD(&algp->cra_list); 1016 1017 err = crypto_register_alg(algp); 1018 if (err) 1019 goto err_algs; 1020 1021 dd->pdata->algs_info[i].registered++; 1022 } 1023 } 1024 } 1025 1026 return 0; 1027 err_algs: 1028 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1029 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1030 crypto_unregister_alg( 1031 &dd->pdata->algs_info[i].algs_list[j]); 1032 1033 err_engine: 1034 if (dd->engine) 1035 crypto_engine_exit(dd->engine); 1036 1037 omap_aes_dma_cleanup(dd); 1038 err_irq: 1039 tasklet_kill(&dd->done_task); 1040 pm_runtime_disable(dev); 1041 err_res: 1042 dd = NULL; 1043 err_data: 1044 dev_err(dev, "initialization failed.\n"); 1045 return err; 1046 } 1047 1048 static int omap_aes_remove(struct platform_device *pdev) 1049 { 1050 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1051 int i, j; 1052 1053 if (!dd) 1054 return -ENODEV; 1055 1056 spin_lock(&list_lock); 1057 list_del(&dd->list); 1058 spin_unlock(&list_lock); 1059 1060 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1061 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1062 crypto_unregister_alg( 1063 &dd->pdata->algs_info[i].algs_list[j]); 1064 1065 crypto_engine_exit(dd->engine); 1066 tasklet_kill(&dd->done_task); 1067 omap_aes_dma_cleanup(dd); 1068 pm_runtime_disable(dd->dev); 1069 dd = NULL; 1070 1071 return 0; 1072 } 1073 1074 #ifdef CONFIG_PM_SLEEP 1075 static int omap_aes_suspend(struct device *dev) 1076 { 1077 pm_runtime_put_sync(dev); 1078 return 0; 1079 } 1080 1081 static int omap_aes_resume(struct device *dev) 1082 { 1083 pm_runtime_get_sync(dev); 1084 return 0; 1085 } 1086 #endif 1087 1088 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1089 1090 static struct platform_driver omap_aes_driver = { 1091 .probe = omap_aes_probe, 1092 .remove = omap_aes_remove, 1093 .driver = { 1094 .name = "omap-aes", 1095 .pm = &omap_aes_pm_ops, 1096 .of_match_table = omap_aes_of_match, 1097 }, 1098 }; 1099 1100 module_platform_driver(omap_aes_driver); 1101 1102 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1103 MODULE_LICENSE("GPL v2"); 1104 MODULE_AUTHOR("Dmitry Kasatkin"); 1105 1106