1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP AES HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 */ 15 16 #define pr_fmt(fmt) "%20s: " fmt, __func__ 17 #define prn(num) pr_debug(#num "=%d\n", num) 18 #define prx(num) pr_debug(#num "=%x\n", num) 19 20 #include <linux/err.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/kernel.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/io.h> 34 #include <linux/crypto.h> 35 #include <linux/interrupt.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/aes.h> 38 #include <crypto/gcm.h> 39 #include <crypto/engine.h> 40 #include <crypto/internal/skcipher.h> 41 #include <crypto/internal/aead.h> 42 43 #include "omap-crypto.h" 44 #include "omap-aes.h" 45 46 /* keep registered devices data here */ 47 static LIST_HEAD(dev_list); 48 static DEFINE_SPINLOCK(list_lock); 49 50 #ifdef DEBUG 51 #define omap_aes_read(dd, offset) \ 52 ({ \ 53 int _read_ret; \ 54 _read_ret = __raw_readl(dd->io_base + offset); \ 55 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 56 offset, _read_ret); \ 57 _read_ret; \ 58 }) 59 #else 60 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 61 { 62 return __raw_readl(dd->io_base + offset); 63 } 64 #endif 65 66 #ifdef DEBUG 67 #define omap_aes_write(dd, offset, value) \ 68 do { \ 69 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 70 offset, value); \ 71 __raw_writel(value, dd->io_base + offset); \ 72 } while (0) 73 #else 74 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 75 u32 value) 76 { 77 __raw_writel(value, dd->io_base + offset); 78 } 79 #endif 80 81 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 82 u32 value, u32 mask) 83 { 84 u32 val; 85 86 val = omap_aes_read(dd, offset); 87 val &= ~mask; 88 val |= value; 89 omap_aes_write(dd, offset, val); 90 } 91 92 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 93 u32 *value, int count) 94 { 95 for (; count--; value++, offset += 4) 96 omap_aes_write(dd, offset, *value); 97 } 98 99 static int omap_aes_hw_init(struct omap_aes_dev *dd) 100 { 101 int err; 102 103 if (!(dd->flags & FLAGS_INIT)) { 104 dd->flags |= FLAGS_INIT; 105 dd->err = 0; 106 } 107 108 err = pm_runtime_get_sync(dd->dev); 109 if (err < 0) { 110 dev_err(dd->dev, "failed to get sync: %d\n", err); 111 return err; 112 } 113 114 return 0; 115 } 116 117 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 118 { 119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 120 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 121 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 122 } 123 124 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 125 { 126 struct omap_aes_reqctx *rctx; 127 unsigned int key32; 128 int i, err; 129 u32 val; 130 131 err = omap_aes_hw_init(dd); 132 if (err) 133 return err; 134 135 key32 = dd->ctx->keylen / sizeof(u32); 136 137 /* RESET the key as previous HASH keys should not get affected*/ 138 if (dd->flags & FLAGS_GCM) 139 for (i = 0; i < 0x40; i = i + 4) 140 omap_aes_write(dd, i, 0x0); 141 142 for (i = 0; i < key32; i++) { 143 omap_aes_write(dd, AES_REG_KEY(dd, i), 144 __le32_to_cpu(dd->ctx->key[i])); 145 } 146 147 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) 148 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); 149 150 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 151 rctx = aead_request_ctx(dd->aead_req); 152 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 153 } 154 155 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 156 if (dd->flags & FLAGS_CBC) 157 val |= AES_REG_CTRL_CBC; 158 159 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 160 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 161 162 if (dd->flags & FLAGS_GCM) 163 val |= AES_REG_CTRL_GCM; 164 165 if (dd->flags & FLAGS_ENCRYPT) 166 val |= AES_REG_CTRL_DIRECTION; 167 168 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 169 170 return 0; 171 } 172 173 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 174 { 175 u32 mask, val; 176 177 val = dd->pdata->dma_start; 178 179 if (dd->dma_lch_out != NULL) 180 val |= dd->pdata->dma_enable_out; 181 if (dd->dma_lch_in != NULL) 182 val |= dd->pdata->dma_enable_in; 183 184 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 185 dd->pdata->dma_start; 186 187 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 188 189 } 190 191 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 192 { 193 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 194 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 195 if (dd->flags & FLAGS_GCM) 196 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 197 198 omap_aes_dma_trigger_omap2(dd, length); 199 } 200 201 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 202 { 203 u32 mask; 204 205 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 206 dd->pdata->dma_start; 207 208 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 209 } 210 211 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 212 { 213 struct omap_aes_dev *dd; 214 215 spin_lock_bh(&list_lock); 216 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 217 list_move_tail(&dd->list, &dev_list); 218 rctx->dd = dd; 219 spin_unlock_bh(&list_lock); 220 221 return dd; 222 } 223 224 static void omap_aes_dma_out_callback(void *data) 225 { 226 struct omap_aes_dev *dd = data; 227 228 /* dma_lch_out - completed */ 229 tasklet_schedule(&dd->done_task); 230 } 231 232 static int omap_aes_dma_init(struct omap_aes_dev *dd) 233 { 234 int err; 235 236 dd->dma_lch_out = NULL; 237 dd->dma_lch_in = NULL; 238 239 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 240 if (IS_ERR(dd->dma_lch_in)) { 241 dev_err(dd->dev, "Unable to request in DMA channel\n"); 242 return PTR_ERR(dd->dma_lch_in); 243 } 244 245 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 246 if (IS_ERR(dd->dma_lch_out)) { 247 dev_err(dd->dev, "Unable to request out DMA channel\n"); 248 err = PTR_ERR(dd->dma_lch_out); 249 goto err_dma_out; 250 } 251 252 return 0; 253 254 err_dma_out: 255 dma_release_channel(dd->dma_lch_in); 256 257 return err; 258 } 259 260 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 261 { 262 if (dd->pio_only) 263 return; 264 265 dma_release_channel(dd->dma_lch_out); 266 dma_release_channel(dd->dma_lch_in); 267 } 268 269 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 270 struct scatterlist *in_sg, 271 struct scatterlist *out_sg, 272 int in_sg_len, int out_sg_len) 273 { 274 struct dma_async_tx_descriptor *tx_in, *tx_out; 275 struct dma_slave_config cfg; 276 int ret; 277 278 if (dd->pio_only) { 279 scatterwalk_start(&dd->in_walk, dd->in_sg); 280 scatterwalk_start(&dd->out_walk, dd->out_sg); 281 282 /* Enable DATAIN interrupt and let it take 283 care of the rest */ 284 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 285 return 0; 286 } 287 288 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 289 290 memset(&cfg, 0, sizeof(cfg)); 291 292 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 293 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 294 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 295 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 296 cfg.src_maxburst = DST_MAXBURST; 297 cfg.dst_maxburst = DST_MAXBURST; 298 299 /* IN */ 300 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 301 if (ret) { 302 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 303 ret); 304 return ret; 305 } 306 307 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 308 DMA_MEM_TO_DEV, 309 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 310 if (!tx_in) { 311 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 312 return -EINVAL; 313 } 314 315 /* No callback necessary */ 316 tx_in->callback_param = dd; 317 318 /* OUT */ 319 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 320 if (ret) { 321 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 322 ret); 323 return ret; 324 } 325 326 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 327 DMA_DEV_TO_MEM, 328 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 329 if (!tx_out) { 330 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 331 return -EINVAL; 332 } 333 334 if (dd->flags & FLAGS_GCM) 335 tx_out->callback = omap_aes_gcm_dma_out_callback; 336 else 337 tx_out->callback = omap_aes_dma_out_callback; 338 tx_out->callback_param = dd; 339 340 dmaengine_submit(tx_in); 341 dmaengine_submit(tx_out); 342 343 dma_async_issue_pending(dd->dma_lch_in); 344 dma_async_issue_pending(dd->dma_lch_out); 345 346 /* start DMA */ 347 dd->pdata->trigger(dd, dd->total); 348 349 return 0; 350 } 351 352 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 353 { 354 int err; 355 356 pr_debug("total: %d\n", dd->total); 357 358 if (!dd->pio_only) { 359 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 360 DMA_TO_DEVICE); 361 if (!err) { 362 dev_err(dd->dev, "dma_map_sg() error\n"); 363 return -EINVAL; 364 } 365 366 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 367 DMA_FROM_DEVICE); 368 if (!err) { 369 dev_err(dd->dev, "dma_map_sg() error\n"); 370 return -EINVAL; 371 } 372 } 373 374 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 375 dd->out_sg_len); 376 if (err && !dd->pio_only) { 377 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 378 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 379 DMA_FROM_DEVICE); 380 } 381 382 return err; 383 } 384 385 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 386 { 387 struct ablkcipher_request *req = dd->req; 388 389 pr_debug("err: %d\n", err); 390 391 crypto_finalize_cipher_request(dd->engine, req, err); 392 393 pm_runtime_mark_last_busy(dd->dev); 394 pm_runtime_put_autosuspend(dd->dev); 395 } 396 397 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 398 { 399 pr_debug("total: %d\n", dd->total); 400 401 omap_aes_dma_stop(dd); 402 403 404 return 0; 405 } 406 407 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 408 struct ablkcipher_request *req) 409 { 410 if (req) 411 return crypto_transfer_cipher_request_to_engine(dd->engine, req); 412 413 return 0; 414 } 415 416 static int omap_aes_prepare_req(struct crypto_engine *engine, 417 struct ablkcipher_request *req) 418 { 419 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 420 crypto_ablkcipher_reqtfm(req)); 421 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 422 struct omap_aes_dev *dd = rctx->dd; 423 int ret; 424 u16 flags; 425 426 if (!dd) 427 return -ENODEV; 428 429 /* assign new request to device */ 430 dd->req = req; 431 dd->total = req->nbytes; 432 dd->total_save = req->nbytes; 433 dd->in_sg = req->src; 434 dd->out_sg = req->dst; 435 dd->orig_out = req->dst; 436 437 flags = OMAP_CRYPTO_COPY_DATA; 438 if (req->src == req->dst) 439 flags |= OMAP_CRYPTO_FORCE_COPY; 440 441 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 442 dd->in_sgl, flags, 443 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 444 if (ret) 445 return ret; 446 447 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 448 &dd->out_sgl, 0, 449 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 450 if (ret) 451 return ret; 452 453 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 454 if (dd->in_sg_len < 0) 455 return dd->in_sg_len; 456 457 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 458 if (dd->out_sg_len < 0) 459 return dd->out_sg_len; 460 461 rctx->mode &= FLAGS_MODE_MASK; 462 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 463 464 dd->ctx = ctx; 465 rctx->dd = dd; 466 467 return omap_aes_write_ctrl(dd); 468 } 469 470 static int omap_aes_crypt_req(struct crypto_engine *engine, 471 struct ablkcipher_request *req) 472 { 473 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 474 struct omap_aes_dev *dd = rctx->dd; 475 476 if (!dd) 477 return -ENODEV; 478 479 return omap_aes_crypt_dma_start(dd); 480 } 481 482 static void omap_aes_done_task(unsigned long data) 483 { 484 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 485 486 pr_debug("enter done_task\n"); 487 488 if (!dd->pio_only) { 489 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 490 DMA_FROM_DEVICE); 491 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 492 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 493 DMA_FROM_DEVICE); 494 omap_aes_crypt_dma_stop(dd); 495 } 496 497 omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save, 498 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 499 500 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, 501 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 502 503 omap_aes_finish_req(dd, 0); 504 505 pr_debug("exit\n"); 506 } 507 508 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) 509 { 510 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 511 crypto_ablkcipher_reqtfm(req)); 512 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 513 struct omap_aes_dev *dd; 514 int ret; 515 516 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 517 !!(mode & FLAGS_ENCRYPT), 518 !!(mode & FLAGS_CBC)); 519 520 if (req->nbytes < 200) { 521 SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); 522 523 skcipher_request_set_tfm(subreq, ctx->fallback); 524 skcipher_request_set_callback(subreq, req->base.flags, NULL, 525 NULL); 526 skcipher_request_set_crypt(subreq, req->src, req->dst, 527 req->nbytes, req->info); 528 529 if (mode & FLAGS_ENCRYPT) 530 ret = crypto_skcipher_encrypt(subreq); 531 else 532 ret = crypto_skcipher_decrypt(subreq); 533 534 skcipher_request_zero(subreq); 535 return ret; 536 } 537 dd = omap_aes_find_dev(rctx); 538 if (!dd) 539 return -ENODEV; 540 541 rctx->mode = mode; 542 543 return omap_aes_handle_queue(dd, req); 544 } 545 546 /* ********************** ALG API ************************************ */ 547 548 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 549 unsigned int keylen) 550 { 551 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 552 int ret; 553 554 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 555 keylen != AES_KEYSIZE_256) 556 return -EINVAL; 557 558 pr_debug("enter, keylen: %d\n", keylen); 559 560 memcpy(ctx->key, key, keylen); 561 ctx->keylen = keylen; 562 563 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 564 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 565 CRYPTO_TFM_REQ_MASK); 566 567 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); 568 if (!ret) 569 return 0; 570 571 return 0; 572 } 573 574 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) 575 { 576 return omap_aes_crypt(req, FLAGS_ENCRYPT); 577 } 578 579 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) 580 { 581 return omap_aes_crypt(req, 0); 582 } 583 584 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) 585 { 586 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 587 } 588 589 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) 590 { 591 return omap_aes_crypt(req, FLAGS_CBC); 592 } 593 594 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) 595 { 596 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 597 } 598 599 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) 600 { 601 return omap_aes_crypt(req, FLAGS_CTR); 602 } 603 604 static int omap_aes_cra_init(struct crypto_tfm *tfm) 605 { 606 const char *name = crypto_tfm_alg_name(tfm); 607 const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; 608 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 609 struct crypto_skcipher *blk; 610 611 blk = crypto_alloc_skcipher(name, 0, flags); 612 if (IS_ERR(blk)) 613 return PTR_ERR(blk); 614 615 ctx->fallback = blk; 616 617 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); 618 619 return 0; 620 } 621 622 static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) 623 { 624 struct omap_aes_dev *dd = NULL; 625 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 626 int err; 627 628 /* Find AES device, currently picks the first device */ 629 spin_lock_bh(&list_lock); 630 list_for_each_entry(dd, &dev_list, list) { 631 break; 632 } 633 spin_unlock_bh(&list_lock); 634 635 err = pm_runtime_get_sync(dd->dev); 636 if (err < 0) { 637 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", 638 __func__, err); 639 return err; 640 } 641 642 tfm->reqsize = sizeof(struct omap_aes_reqctx); 643 ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); 644 if (IS_ERR(ctx->ctr)) { 645 pr_warn("could not load aes driver for encrypting IV\n"); 646 return PTR_ERR(ctx->ctr); 647 } 648 649 return 0; 650 } 651 652 static void omap_aes_cra_exit(struct crypto_tfm *tfm) 653 { 654 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 655 656 if (ctx->fallback) 657 crypto_free_skcipher(ctx->fallback); 658 659 ctx->fallback = NULL; 660 } 661 662 static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) 663 { 664 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 665 666 omap_aes_cra_exit(crypto_aead_tfm(tfm)); 667 668 if (ctx->ctr) 669 crypto_free_skcipher(ctx->ctr); 670 } 671 672 /* ********************** ALGS ************************************ */ 673 674 static struct crypto_alg algs_ecb_cbc[] = { 675 { 676 .cra_name = "ecb(aes)", 677 .cra_driver_name = "ecb-aes-omap", 678 .cra_priority = 300, 679 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 680 CRYPTO_ALG_KERN_DRIVER_ONLY | 681 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 682 .cra_blocksize = AES_BLOCK_SIZE, 683 .cra_ctxsize = sizeof(struct omap_aes_ctx), 684 .cra_alignmask = 0, 685 .cra_type = &crypto_ablkcipher_type, 686 .cra_module = THIS_MODULE, 687 .cra_init = omap_aes_cra_init, 688 .cra_exit = omap_aes_cra_exit, 689 .cra_u.ablkcipher = { 690 .min_keysize = AES_MIN_KEY_SIZE, 691 .max_keysize = AES_MAX_KEY_SIZE, 692 .setkey = omap_aes_setkey, 693 .encrypt = omap_aes_ecb_encrypt, 694 .decrypt = omap_aes_ecb_decrypt, 695 } 696 }, 697 { 698 .cra_name = "cbc(aes)", 699 .cra_driver_name = "cbc-aes-omap", 700 .cra_priority = 300, 701 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 702 CRYPTO_ALG_KERN_DRIVER_ONLY | 703 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 704 .cra_blocksize = AES_BLOCK_SIZE, 705 .cra_ctxsize = sizeof(struct omap_aes_ctx), 706 .cra_alignmask = 0, 707 .cra_type = &crypto_ablkcipher_type, 708 .cra_module = THIS_MODULE, 709 .cra_init = omap_aes_cra_init, 710 .cra_exit = omap_aes_cra_exit, 711 .cra_u.ablkcipher = { 712 .min_keysize = AES_MIN_KEY_SIZE, 713 .max_keysize = AES_MAX_KEY_SIZE, 714 .ivsize = AES_BLOCK_SIZE, 715 .setkey = omap_aes_setkey, 716 .encrypt = omap_aes_cbc_encrypt, 717 .decrypt = omap_aes_cbc_decrypt, 718 } 719 } 720 }; 721 722 static struct crypto_alg algs_ctr[] = { 723 { 724 .cra_name = "ctr(aes)", 725 .cra_driver_name = "ctr-aes-omap", 726 .cra_priority = 300, 727 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 728 CRYPTO_ALG_KERN_DRIVER_ONLY | 729 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, 730 .cra_blocksize = AES_BLOCK_SIZE, 731 .cra_ctxsize = sizeof(struct omap_aes_ctx), 732 .cra_alignmask = 0, 733 .cra_type = &crypto_ablkcipher_type, 734 .cra_module = THIS_MODULE, 735 .cra_init = omap_aes_cra_init, 736 .cra_exit = omap_aes_cra_exit, 737 .cra_u.ablkcipher = { 738 .min_keysize = AES_MIN_KEY_SIZE, 739 .max_keysize = AES_MAX_KEY_SIZE, 740 .geniv = "eseqiv", 741 .ivsize = AES_BLOCK_SIZE, 742 .setkey = omap_aes_setkey, 743 .encrypt = omap_aes_ctr_encrypt, 744 .decrypt = omap_aes_ctr_decrypt, 745 } 746 } , 747 }; 748 749 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 750 { 751 .algs_list = algs_ecb_cbc, 752 .size = ARRAY_SIZE(algs_ecb_cbc), 753 }, 754 }; 755 756 static struct aead_alg algs_aead_gcm[] = { 757 { 758 .base = { 759 .cra_name = "gcm(aes)", 760 .cra_driver_name = "gcm-aes-omap", 761 .cra_priority = 300, 762 .cra_flags = CRYPTO_ALG_ASYNC | 763 CRYPTO_ALG_KERN_DRIVER_ONLY, 764 .cra_blocksize = 1, 765 .cra_ctxsize = sizeof(struct omap_aes_ctx), 766 .cra_alignmask = 0xf, 767 .cra_module = THIS_MODULE, 768 }, 769 .init = omap_aes_gcm_cra_init, 770 .exit = omap_aes_gcm_cra_exit, 771 .ivsize = GCM_AES_IV_SIZE, 772 .maxauthsize = AES_BLOCK_SIZE, 773 .setkey = omap_aes_gcm_setkey, 774 .encrypt = omap_aes_gcm_encrypt, 775 .decrypt = omap_aes_gcm_decrypt, 776 }, 777 { 778 .base = { 779 .cra_name = "rfc4106(gcm(aes))", 780 .cra_driver_name = "rfc4106-gcm-aes-omap", 781 .cra_priority = 300, 782 .cra_flags = CRYPTO_ALG_ASYNC | 783 CRYPTO_ALG_KERN_DRIVER_ONLY, 784 .cra_blocksize = 1, 785 .cra_ctxsize = sizeof(struct omap_aes_ctx), 786 .cra_alignmask = 0xf, 787 .cra_module = THIS_MODULE, 788 }, 789 .init = omap_aes_gcm_cra_init, 790 .exit = omap_aes_gcm_cra_exit, 791 .maxauthsize = AES_BLOCK_SIZE, 792 .ivsize = GCM_RFC4106_IV_SIZE, 793 .setkey = omap_aes_4106gcm_setkey, 794 .encrypt = omap_aes_4106gcm_encrypt, 795 .decrypt = omap_aes_4106gcm_decrypt, 796 }, 797 }; 798 799 static struct omap_aes_aead_algs omap_aes_aead_info = { 800 .algs_list = algs_aead_gcm, 801 .size = ARRAY_SIZE(algs_aead_gcm), 802 }; 803 804 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 805 .algs_info = omap_aes_algs_info_ecb_cbc, 806 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 807 .trigger = omap_aes_dma_trigger_omap2, 808 .key_ofs = 0x1c, 809 .iv_ofs = 0x20, 810 .ctrl_ofs = 0x30, 811 .data_ofs = 0x34, 812 .rev_ofs = 0x44, 813 .mask_ofs = 0x48, 814 .dma_enable_in = BIT(2), 815 .dma_enable_out = BIT(3), 816 .dma_start = BIT(5), 817 .major_mask = 0xf0, 818 .major_shift = 4, 819 .minor_mask = 0x0f, 820 .minor_shift = 0, 821 }; 822 823 #ifdef CONFIG_OF 824 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 825 { 826 .algs_list = algs_ecb_cbc, 827 .size = ARRAY_SIZE(algs_ecb_cbc), 828 }, 829 { 830 .algs_list = algs_ctr, 831 .size = ARRAY_SIZE(algs_ctr), 832 }, 833 }; 834 835 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 836 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 837 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 838 .trigger = omap_aes_dma_trigger_omap2, 839 .key_ofs = 0x1c, 840 .iv_ofs = 0x20, 841 .ctrl_ofs = 0x30, 842 .data_ofs = 0x34, 843 .rev_ofs = 0x44, 844 .mask_ofs = 0x48, 845 .dma_enable_in = BIT(2), 846 .dma_enable_out = BIT(3), 847 .dma_start = BIT(5), 848 .major_mask = 0xf0, 849 .major_shift = 4, 850 .minor_mask = 0x0f, 851 .minor_shift = 0, 852 }; 853 854 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 855 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 856 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 857 .aead_algs_info = &omap_aes_aead_info, 858 .trigger = omap_aes_dma_trigger_omap4, 859 .key_ofs = 0x3c, 860 .iv_ofs = 0x40, 861 .ctrl_ofs = 0x50, 862 .data_ofs = 0x60, 863 .rev_ofs = 0x80, 864 .mask_ofs = 0x84, 865 .irq_status_ofs = 0x8c, 866 .irq_enable_ofs = 0x90, 867 .dma_enable_in = BIT(5), 868 .dma_enable_out = BIT(6), 869 .major_mask = 0x0700, 870 .major_shift = 8, 871 .minor_mask = 0x003f, 872 .minor_shift = 0, 873 }; 874 875 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 876 { 877 struct omap_aes_dev *dd = dev_id; 878 u32 status, i; 879 u32 *src, *dst; 880 881 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 882 if (status & AES_REG_IRQ_DATA_IN) { 883 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 884 885 BUG_ON(!dd->in_sg); 886 887 BUG_ON(_calc_walked(in) > dd->in_sg->length); 888 889 src = sg_virt(dd->in_sg) + _calc_walked(in); 890 891 for (i = 0; i < AES_BLOCK_WORDS; i++) { 892 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 893 894 scatterwalk_advance(&dd->in_walk, 4); 895 if (dd->in_sg->length == _calc_walked(in)) { 896 dd->in_sg = sg_next(dd->in_sg); 897 if (dd->in_sg) { 898 scatterwalk_start(&dd->in_walk, 899 dd->in_sg); 900 src = sg_virt(dd->in_sg) + 901 _calc_walked(in); 902 } 903 } else { 904 src++; 905 } 906 } 907 908 /* Clear IRQ status */ 909 status &= ~AES_REG_IRQ_DATA_IN; 910 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 911 912 /* Enable DATA_OUT interrupt */ 913 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 914 915 } else if (status & AES_REG_IRQ_DATA_OUT) { 916 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 917 918 BUG_ON(!dd->out_sg); 919 920 BUG_ON(_calc_walked(out) > dd->out_sg->length); 921 922 dst = sg_virt(dd->out_sg) + _calc_walked(out); 923 924 for (i = 0; i < AES_BLOCK_WORDS; i++) { 925 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 926 scatterwalk_advance(&dd->out_walk, 4); 927 if (dd->out_sg->length == _calc_walked(out)) { 928 dd->out_sg = sg_next(dd->out_sg); 929 if (dd->out_sg) { 930 scatterwalk_start(&dd->out_walk, 931 dd->out_sg); 932 dst = sg_virt(dd->out_sg) + 933 _calc_walked(out); 934 } 935 } else { 936 dst++; 937 } 938 } 939 940 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 941 942 /* Clear IRQ status */ 943 status &= ~AES_REG_IRQ_DATA_OUT; 944 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 945 946 if (!dd->total) 947 /* All bytes read! */ 948 tasklet_schedule(&dd->done_task); 949 else 950 /* Enable DATA_IN interrupt for next block */ 951 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 952 } 953 954 return IRQ_HANDLED; 955 } 956 957 static const struct of_device_id omap_aes_of_match[] = { 958 { 959 .compatible = "ti,omap2-aes", 960 .data = &omap_aes_pdata_omap2, 961 }, 962 { 963 .compatible = "ti,omap3-aes", 964 .data = &omap_aes_pdata_omap3, 965 }, 966 { 967 .compatible = "ti,omap4-aes", 968 .data = &omap_aes_pdata_omap4, 969 }, 970 {}, 971 }; 972 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 973 974 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 975 struct device *dev, struct resource *res) 976 { 977 struct device_node *node = dev->of_node; 978 int err = 0; 979 980 dd->pdata = of_device_get_match_data(dev); 981 if (!dd->pdata) { 982 dev_err(dev, "no compatible OF match\n"); 983 err = -EINVAL; 984 goto err; 985 } 986 987 err = of_address_to_resource(node, 0, res); 988 if (err < 0) { 989 dev_err(dev, "can't translate OF node address\n"); 990 err = -EINVAL; 991 goto err; 992 } 993 994 err: 995 return err; 996 } 997 #else 998 static const struct of_device_id omap_aes_of_match[] = { 999 {}, 1000 }; 1001 1002 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1003 struct device *dev, struct resource *res) 1004 { 1005 return -EINVAL; 1006 } 1007 #endif 1008 1009 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 1010 struct platform_device *pdev, struct resource *res) 1011 { 1012 struct device *dev = &pdev->dev; 1013 struct resource *r; 1014 int err = 0; 1015 1016 /* Get the base address */ 1017 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1018 if (!r) { 1019 dev_err(dev, "no MEM resource info\n"); 1020 err = -ENODEV; 1021 goto err; 1022 } 1023 memcpy(res, r, sizeof(*res)); 1024 1025 /* Only OMAP2/3 can be non-DT */ 1026 dd->pdata = &omap_aes_pdata_omap2; 1027 1028 err: 1029 return err; 1030 } 1031 1032 static int omap_aes_probe(struct platform_device *pdev) 1033 { 1034 struct device *dev = &pdev->dev; 1035 struct omap_aes_dev *dd; 1036 struct crypto_alg *algp; 1037 struct aead_alg *aalg; 1038 struct resource res; 1039 int err = -ENOMEM, i, j, irq = -1; 1040 u32 reg; 1041 1042 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1043 if (dd == NULL) { 1044 dev_err(dev, "unable to alloc data struct.\n"); 1045 goto err_data; 1046 } 1047 dd->dev = dev; 1048 platform_set_drvdata(pdev, dd); 1049 1050 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1051 1052 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1053 omap_aes_get_res_pdev(dd, pdev, &res); 1054 if (err) 1055 goto err_res; 1056 1057 dd->io_base = devm_ioremap_resource(dev, &res); 1058 if (IS_ERR(dd->io_base)) { 1059 err = PTR_ERR(dd->io_base); 1060 goto err_res; 1061 } 1062 dd->phys_base = res.start; 1063 1064 pm_runtime_use_autosuspend(dev); 1065 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1066 1067 pm_runtime_enable(dev); 1068 err = pm_runtime_get_sync(dev); 1069 if (err < 0) { 1070 dev_err(dev, "%s: failed to get_sync(%d)\n", 1071 __func__, err); 1072 goto err_res; 1073 } 1074 1075 omap_aes_dma_stop(dd); 1076 1077 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1078 1079 pm_runtime_put_sync(dev); 1080 1081 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1082 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1083 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1084 1085 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1086 1087 err = omap_aes_dma_init(dd); 1088 if (err == -EPROBE_DEFER) { 1089 goto err_irq; 1090 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1091 dd->pio_only = 1; 1092 1093 irq = platform_get_irq(pdev, 0); 1094 if (irq < 0) { 1095 dev_err(dev, "can't get IRQ resource\n"); 1096 err = irq; 1097 goto err_irq; 1098 } 1099 1100 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1101 dev_name(dev), dd); 1102 if (err) { 1103 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1104 goto err_irq; 1105 } 1106 } 1107 1108 spin_lock_init(&dd->lock); 1109 1110 INIT_LIST_HEAD(&dd->list); 1111 spin_lock(&list_lock); 1112 list_add_tail(&dd->list, &dev_list); 1113 spin_unlock(&list_lock); 1114 1115 /* Initialize crypto engine */ 1116 dd->engine = crypto_engine_alloc_init(dev, 1); 1117 if (!dd->engine) { 1118 err = -ENOMEM; 1119 goto err_engine; 1120 } 1121 1122 dd->engine->prepare_cipher_request = omap_aes_prepare_req; 1123 dd->engine->cipher_one_request = omap_aes_crypt_req; 1124 err = crypto_engine_start(dd->engine); 1125 if (err) 1126 goto err_engine; 1127 1128 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1129 if (!dd->pdata->algs_info[i].registered) { 1130 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1131 algp = &dd->pdata->algs_info[i].algs_list[j]; 1132 1133 pr_debug("reg alg: %s\n", algp->cra_name); 1134 INIT_LIST_HEAD(&algp->cra_list); 1135 1136 err = crypto_register_alg(algp); 1137 if (err) 1138 goto err_algs; 1139 1140 dd->pdata->algs_info[i].registered++; 1141 } 1142 } 1143 } 1144 1145 if (dd->pdata->aead_algs_info && 1146 !dd->pdata->aead_algs_info->registered) { 1147 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1148 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1149 algp = &aalg->base; 1150 1151 pr_debug("reg alg: %s\n", algp->cra_name); 1152 INIT_LIST_HEAD(&algp->cra_list); 1153 1154 err = crypto_register_aead(aalg); 1155 if (err) 1156 goto err_aead_algs; 1157 1158 dd->pdata->aead_algs_info->registered++; 1159 } 1160 } 1161 1162 return 0; 1163 err_aead_algs: 1164 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1165 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1166 crypto_unregister_aead(aalg); 1167 } 1168 err_algs: 1169 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1170 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1171 crypto_unregister_alg( 1172 &dd->pdata->algs_info[i].algs_list[j]); 1173 1174 err_engine: 1175 if (dd->engine) 1176 crypto_engine_exit(dd->engine); 1177 1178 omap_aes_dma_cleanup(dd); 1179 err_irq: 1180 tasklet_kill(&dd->done_task); 1181 pm_runtime_disable(dev); 1182 err_res: 1183 dd = NULL; 1184 err_data: 1185 dev_err(dev, "initialization failed.\n"); 1186 return err; 1187 } 1188 1189 static int omap_aes_remove(struct platform_device *pdev) 1190 { 1191 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1192 struct aead_alg *aalg; 1193 int i, j; 1194 1195 if (!dd) 1196 return -ENODEV; 1197 1198 spin_lock(&list_lock); 1199 list_del(&dd->list); 1200 spin_unlock(&list_lock); 1201 1202 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1203 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1204 crypto_unregister_alg( 1205 &dd->pdata->algs_info[i].algs_list[j]); 1206 1207 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { 1208 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1209 crypto_unregister_aead(aalg); 1210 } 1211 1212 crypto_engine_exit(dd->engine); 1213 1214 tasklet_kill(&dd->done_task); 1215 omap_aes_dma_cleanup(dd); 1216 pm_runtime_disable(dd->dev); 1217 dd = NULL; 1218 1219 return 0; 1220 } 1221 1222 #ifdef CONFIG_PM_SLEEP 1223 static int omap_aes_suspend(struct device *dev) 1224 { 1225 pm_runtime_put_sync(dev); 1226 return 0; 1227 } 1228 1229 static int omap_aes_resume(struct device *dev) 1230 { 1231 pm_runtime_get_sync(dev); 1232 return 0; 1233 } 1234 #endif 1235 1236 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1237 1238 static struct platform_driver omap_aes_driver = { 1239 .probe = omap_aes_probe, 1240 .remove = omap_aes_remove, 1241 .driver = { 1242 .name = "omap-aes", 1243 .pm = &omap_aes_pm_ops, 1244 .of_match_table = omap_aes_of_match, 1245 }, 1246 }; 1247 1248 module_platform_driver(omap_aes_driver); 1249 1250 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1251 MODULE_LICENSE("GPL v2"); 1252 MODULE_AUTHOR("Dmitry Kasatkin"); 1253 1254