1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP AES HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 */ 15 16 #define pr_fmt(fmt) "%20s: " fmt, __func__ 17 #define prn(num) pr_debug(#num "=%d\n", num) 18 #define prx(num) pr_debug(#num "=%x\n", num) 19 20 #include <linux/err.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/kernel.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/io.h> 34 #include <linux/crypto.h> 35 #include <linux/interrupt.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/aes.h> 38 #include <crypto/algapi.h> 39 40 #define DST_MAXBURST 4 41 #define DMA_MIN (DST_MAXBURST * sizeof(u32)) 42 43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 44 45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 46 number. For example 7:0 */ 47 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 49 50 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 51 ((x ^ 0x01) * 0x04)) 52 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 53 54 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 55 #define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7) 56 #define AES_REG_CTRL_CTR_WIDTH_32 0 57 #define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) 58 #define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) 59 #define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7) 60 #define AES_REG_CTRL_CTR BIT(6) 61 #define AES_REG_CTRL_CBC BIT(5) 62 #define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3) 63 #define AES_REG_CTRL_DIRECTION BIT(2) 64 #define AES_REG_CTRL_INPUT_READY BIT(1) 65 #define AES_REG_CTRL_OUTPUT_READY BIT(0) 66 #define AES_REG_CTRL_MASK GENMASK(24, 2) 67 68 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 69 70 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) 71 72 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 73 #define AES_REG_MASK_SIDLE BIT(6) 74 #define AES_REG_MASK_START BIT(5) 75 #define AES_REG_MASK_DMA_OUT_EN BIT(3) 76 #define AES_REG_MASK_DMA_IN_EN BIT(2) 77 #define AES_REG_MASK_SOFTRESET BIT(1) 78 #define AES_REG_AUTOIDLE BIT(0) 79 80 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) 81 82 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 83 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 84 #define AES_REG_IRQ_DATA_IN BIT(1) 85 #define AES_REG_IRQ_DATA_OUT BIT(2) 86 #define DEFAULT_TIMEOUT (5*HZ) 87 88 #define FLAGS_MODE_MASK 0x000f 89 #define FLAGS_ENCRYPT BIT(0) 90 #define FLAGS_CBC BIT(1) 91 #define FLAGS_GIV BIT(2) 92 #define FLAGS_CTR BIT(3) 93 94 #define FLAGS_INIT BIT(4) 95 #define FLAGS_FAST BIT(5) 96 #define FLAGS_BUSY BIT(6) 97 98 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) 99 100 struct omap_aes_ctx { 101 struct omap_aes_dev *dd; 102 103 int keylen; 104 u32 key[AES_KEYSIZE_256 / sizeof(u32)]; 105 unsigned long flags; 106 }; 107 108 struct omap_aes_reqctx { 109 unsigned long mode; 110 }; 111 112 #define OMAP_AES_QUEUE_LENGTH 1 113 #define OMAP_AES_CACHE_SIZE 0 114 115 struct omap_aes_algs_info { 116 struct crypto_alg *algs_list; 117 unsigned int size; 118 unsigned int registered; 119 }; 120 121 struct omap_aes_pdata { 122 struct omap_aes_algs_info *algs_info; 123 unsigned int algs_info_size; 124 125 void (*trigger)(struct omap_aes_dev *dd, int length); 126 127 u32 key_ofs; 128 u32 iv_ofs; 129 u32 ctrl_ofs; 130 u32 data_ofs; 131 u32 rev_ofs; 132 u32 mask_ofs; 133 u32 irq_enable_ofs; 134 u32 irq_status_ofs; 135 136 u32 dma_enable_in; 137 u32 dma_enable_out; 138 u32 dma_start; 139 140 u32 major_mask; 141 u32 major_shift; 142 u32 minor_mask; 143 u32 minor_shift; 144 }; 145 146 struct omap_aes_dev { 147 struct list_head list; 148 unsigned long phys_base; 149 void __iomem *io_base; 150 struct omap_aes_ctx *ctx; 151 struct device *dev; 152 unsigned long flags; 153 int err; 154 155 struct tasklet_struct done_task; 156 157 struct ablkcipher_request *req; 158 struct crypto_engine *engine; 159 160 /* 161 * total is used by PIO mode for book keeping so introduce 162 * variable total_save as need it to calc page_order 163 */ 164 size_t total; 165 size_t total_save; 166 167 struct scatterlist *in_sg; 168 struct scatterlist *out_sg; 169 170 /* Buffers for copying for unaligned cases */ 171 struct scatterlist in_sgl; 172 struct scatterlist out_sgl; 173 struct scatterlist *orig_out; 174 int sgs_copied; 175 176 struct scatter_walk in_walk; 177 struct scatter_walk out_walk; 178 struct dma_chan *dma_lch_in; 179 struct dma_chan *dma_lch_out; 180 int in_sg_len; 181 int out_sg_len; 182 int pio_only; 183 const struct omap_aes_pdata *pdata; 184 }; 185 186 /* keep registered devices data here */ 187 static LIST_HEAD(dev_list); 188 static DEFINE_SPINLOCK(list_lock); 189 190 #ifdef DEBUG 191 #define omap_aes_read(dd, offset) \ 192 ({ \ 193 int _read_ret; \ 194 _read_ret = __raw_readl(dd->io_base + offset); \ 195 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 196 offset, _read_ret); \ 197 _read_ret; \ 198 }) 199 #else 200 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 201 { 202 return __raw_readl(dd->io_base + offset); 203 } 204 #endif 205 206 #ifdef DEBUG 207 #define omap_aes_write(dd, offset, value) \ 208 do { \ 209 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 210 offset, value); \ 211 __raw_writel(value, dd->io_base + offset); \ 212 } while (0) 213 #else 214 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 215 u32 value) 216 { 217 __raw_writel(value, dd->io_base + offset); 218 } 219 #endif 220 221 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 222 u32 value, u32 mask) 223 { 224 u32 val; 225 226 val = omap_aes_read(dd, offset); 227 val &= ~mask; 228 val |= value; 229 omap_aes_write(dd, offset, val); 230 } 231 232 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 233 u32 *value, int count) 234 { 235 for (; count--; value++, offset += 4) 236 omap_aes_write(dd, offset, *value); 237 } 238 239 static int omap_aes_hw_init(struct omap_aes_dev *dd) 240 { 241 if (!(dd->flags & FLAGS_INIT)) { 242 dd->flags |= FLAGS_INIT; 243 dd->err = 0; 244 } 245 246 return 0; 247 } 248 249 static int omap_aes_write_ctrl(struct omap_aes_dev *dd) 250 { 251 unsigned int key32; 252 int i, err; 253 u32 val; 254 255 err = omap_aes_hw_init(dd); 256 if (err) 257 return err; 258 259 key32 = dd->ctx->keylen / sizeof(u32); 260 261 /* it seems a key should always be set even if it has not changed */ 262 for (i = 0; i < key32; i++) { 263 omap_aes_write(dd, AES_REG_KEY(dd, i), 264 __le32_to_cpu(dd->ctx->key[i])); 265 } 266 267 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) 268 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); 269 270 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 271 if (dd->flags & FLAGS_CBC) 272 val |= AES_REG_CTRL_CBC; 273 if (dd->flags & FLAGS_CTR) 274 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 275 276 if (dd->flags & FLAGS_ENCRYPT) 277 val |= AES_REG_CTRL_DIRECTION; 278 279 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 280 281 return 0; 282 } 283 284 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 285 { 286 u32 mask, val; 287 288 val = dd->pdata->dma_start; 289 290 if (dd->dma_lch_out != NULL) 291 val |= dd->pdata->dma_enable_out; 292 if (dd->dma_lch_in != NULL) 293 val |= dd->pdata->dma_enable_in; 294 295 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 296 dd->pdata->dma_start; 297 298 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 299 300 } 301 302 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 303 { 304 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 305 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 306 307 omap_aes_dma_trigger_omap2(dd, length); 308 } 309 310 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 311 { 312 u32 mask; 313 314 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 315 dd->pdata->dma_start; 316 317 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 318 } 319 320 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) 321 { 322 struct omap_aes_dev *dd = NULL, *tmp; 323 324 spin_lock_bh(&list_lock); 325 if (!ctx->dd) { 326 list_for_each_entry(tmp, &dev_list, list) { 327 /* FIXME: take fist available aes core */ 328 dd = tmp; 329 break; 330 } 331 ctx->dd = dd; 332 } else { 333 /* already found before */ 334 dd = ctx->dd; 335 } 336 spin_unlock_bh(&list_lock); 337 338 return dd; 339 } 340 341 static void omap_aes_dma_out_callback(void *data) 342 { 343 struct omap_aes_dev *dd = data; 344 345 /* dma_lch_out - completed */ 346 tasklet_schedule(&dd->done_task); 347 } 348 349 static int omap_aes_dma_init(struct omap_aes_dev *dd) 350 { 351 int err; 352 353 dd->dma_lch_out = NULL; 354 dd->dma_lch_in = NULL; 355 356 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 357 if (IS_ERR(dd->dma_lch_in)) { 358 dev_err(dd->dev, "Unable to request in DMA channel\n"); 359 return PTR_ERR(dd->dma_lch_in); 360 } 361 362 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 363 if (IS_ERR(dd->dma_lch_out)) { 364 dev_err(dd->dev, "Unable to request out DMA channel\n"); 365 err = PTR_ERR(dd->dma_lch_out); 366 goto err_dma_out; 367 } 368 369 return 0; 370 371 err_dma_out: 372 dma_release_channel(dd->dma_lch_in); 373 374 return err; 375 } 376 377 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 378 { 379 if (dd->pio_only) 380 return; 381 382 dma_release_channel(dd->dma_lch_out); 383 dma_release_channel(dd->dma_lch_in); 384 } 385 386 static void sg_copy_buf(void *buf, struct scatterlist *sg, 387 unsigned int start, unsigned int nbytes, int out) 388 { 389 struct scatter_walk walk; 390 391 if (!nbytes) 392 return; 393 394 scatterwalk_start(&walk, sg); 395 scatterwalk_advance(&walk, start); 396 scatterwalk_copychunks(buf, &walk, nbytes, out); 397 scatterwalk_done(&walk, out, 0); 398 } 399 400 static int omap_aes_crypt_dma(struct crypto_tfm *tfm, 401 struct scatterlist *in_sg, struct scatterlist *out_sg, 402 int in_sg_len, int out_sg_len) 403 { 404 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 405 struct omap_aes_dev *dd = ctx->dd; 406 struct dma_async_tx_descriptor *tx_in, *tx_out; 407 struct dma_slave_config cfg; 408 int ret; 409 410 if (dd->pio_only) { 411 scatterwalk_start(&dd->in_walk, dd->in_sg); 412 scatterwalk_start(&dd->out_walk, dd->out_sg); 413 414 /* Enable DATAIN interrupt and let it take 415 care of the rest */ 416 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 417 return 0; 418 } 419 420 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 421 422 memset(&cfg, 0, sizeof(cfg)); 423 424 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 425 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 428 cfg.src_maxburst = DST_MAXBURST; 429 cfg.dst_maxburst = DST_MAXBURST; 430 431 /* IN */ 432 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 433 if (ret) { 434 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 435 ret); 436 return ret; 437 } 438 439 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 440 DMA_MEM_TO_DEV, 441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 442 if (!tx_in) { 443 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 444 return -EINVAL; 445 } 446 447 /* No callback necessary */ 448 tx_in->callback_param = dd; 449 450 /* OUT */ 451 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 452 if (ret) { 453 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 454 ret); 455 return ret; 456 } 457 458 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 459 DMA_DEV_TO_MEM, 460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 461 if (!tx_out) { 462 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 463 return -EINVAL; 464 } 465 466 tx_out->callback = omap_aes_dma_out_callback; 467 tx_out->callback_param = dd; 468 469 dmaengine_submit(tx_in); 470 dmaengine_submit(tx_out); 471 472 dma_async_issue_pending(dd->dma_lch_in); 473 dma_async_issue_pending(dd->dma_lch_out); 474 475 /* start DMA */ 476 dd->pdata->trigger(dd, dd->total); 477 478 return 0; 479 } 480 481 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 482 { 483 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 484 crypto_ablkcipher_reqtfm(dd->req)); 485 int err; 486 487 pr_debug("total: %d\n", dd->total); 488 489 if (!dd->pio_only) { 490 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 491 DMA_TO_DEVICE); 492 if (!err) { 493 dev_err(dd->dev, "dma_map_sg() error\n"); 494 return -EINVAL; 495 } 496 497 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 498 DMA_FROM_DEVICE); 499 if (!err) { 500 dev_err(dd->dev, "dma_map_sg() error\n"); 501 return -EINVAL; 502 } 503 } 504 505 err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 506 dd->out_sg_len); 507 if (err && !dd->pio_only) { 508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 510 DMA_FROM_DEVICE); 511 } 512 513 return err; 514 } 515 516 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 517 { 518 struct ablkcipher_request *req = dd->req; 519 520 pr_debug("err: %d\n", err); 521 522 crypto_finalize_request(dd->engine, req, err); 523 } 524 525 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 526 { 527 pr_debug("total: %d\n", dd->total); 528 529 omap_aes_dma_stop(dd); 530 531 532 return 0; 533 } 534 535 static int omap_aes_check_aligned(struct scatterlist *sg, int total) 536 { 537 int len = 0; 538 539 if (!IS_ALIGNED(total, AES_BLOCK_SIZE)) 540 return -EINVAL; 541 542 while (sg) { 543 if (!IS_ALIGNED(sg->offset, 4)) 544 return -1; 545 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) 546 return -1; 547 548 len += sg->length; 549 sg = sg_next(sg); 550 } 551 552 if (len != total) 553 return -1; 554 555 return 0; 556 } 557 558 static int omap_aes_copy_sgs(struct omap_aes_dev *dd) 559 { 560 void *buf_in, *buf_out; 561 int pages, total; 562 563 total = ALIGN(dd->total, AES_BLOCK_SIZE); 564 pages = get_order(total); 565 566 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); 567 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages); 568 569 if (!buf_in || !buf_out) { 570 pr_err("Couldn't allocated pages for unaligned cases.\n"); 571 return -1; 572 } 573 574 dd->orig_out = dd->out_sg; 575 576 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0); 577 578 sg_init_table(&dd->in_sgl, 1); 579 sg_set_buf(&dd->in_sgl, buf_in, total); 580 dd->in_sg = &dd->in_sgl; 581 dd->in_sg_len = 1; 582 583 sg_init_table(&dd->out_sgl, 1); 584 sg_set_buf(&dd->out_sgl, buf_out, total); 585 dd->out_sg = &dd->out_sgl; 586 dd->out_sg_len = 1; 587 588 return 0; 589 } 590 591 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 592 struct ablkcipher_request *req) 593 { 594 if (req) 595 return crypto_transfer_request_to_engine(dd->engine, req); 596 597 return 0; 598 } 599 600 static int omap_aes_prepare_req(struct crypto_engine *engine, 601 struct ablkcipher_request *req) 602 { 603 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 604 crypto_ablkcipher_reqtfm(req)); 605 struct omap_aes_dev *dd = omap_aes_find_dev(ctx); 606 struct omap_aes_reqctx *rctx; 607 608 if (!dd) 609 return -ENODEV; 610 611 /* assign new request to device */ 612 dd->req = req; 613 dd->total = req->nbytes; 614 dd->total_save = req->nbytes; 615 dd->in_sg = req->src; 616 dd->out_sg = req->dst; 617 618 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 619 if (dd->in_sg_len < 0) 620 return dd->in_sg_len; 621 622 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 623 if (dd->out_sg_len < 0) 624 return dd->out_sg_len; 625 626 if (omap_aes_check_aligned(dd->in_sg, dd->total) || 627 omap_aes_check_aligned(dd->out_sg, dd->total)) { 628 if (omap_aes_copy_sgs(dd)) 629 pr_err("Failed to copy SGs for unaligned cases\n"); 630 dd->sgs_copied = 1; 631 } else { 632 dd->sgs_copied = 0; 633 } 634 635 rctx = ablkcipher_request_ctx(req); 636 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 637 rctx->mode &= FLAGS_MODE_MASK; 638 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 639 640 dd->ctx = ctx; 641 ctx->dd = dd; 642 643 return omap_aes_write_ctrl(dd); 644 } 645 646 static int omap_aes_crypt_req(struct crypto_engine *engine, 647 struct ablkcipher_request *req) 648 { 649 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 650 crypto_ablkcipher_reqtfm(req)); 651 struct omap_aes_dev *dd = omap_aes_find_dev(ctx); 652 653 if (!dd) 654 return -ENODEV; 655 656 return omap_aes_crypt_dma_start(dd); 657 } 658 659 static void omap_aes_done_task(unsigned long data) 660 { 661 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 662 void *buf_in, *buf_out; 663 int pages, len; 664 665 pr_debug("enter done_task\n"); 666 667 if (!dd->pio_only) { 668 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 669 DMA_FROM_DEVICE); 670 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 671 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 672 DMA_FROM_DEVICE); 673 omap_aes_crypt_dma_stop(dd); 674 } 675 676 if (dd->sgs_copied) { 677 buf_in = sg_virt(&dd->in_sgl); 678 buf_out = sg_virt(&dd->out_sgl); 679 680 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1); 681 682 len = ALIGN(dd->total_save, AES_BLOCK_SIZE); 683 pages = get_order(len); 684 free_pages((unsigned long)buf_in, pages); 685 free_pages((unsigned long)buf_out, pages); 686 } 687 688 omap_aes_finish_req(dd, 0); 689 690 pr_debug("exit\n"); 691 } 692 693 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) 694 { 695 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 696 crypto_ablkcipher_reqtfm(req)); 697 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 698 struct omap_aes_dev *dd; 699 700 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 701 !!(mode & FLAGS_ENCRYPT), 702 !!(mode & FLAGS_CBC)); 703 704 dd = omap_aes_find_dev(ctx); 705 if (!dd) 706 return -ENODEV; 707 708 rctx->mode = mode; 709 710 return omap_aes_handle_queue(dd, req); 711 } 712 713 /* ********************** ALG API ************************************ */ 714 715 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 716 unsigned int keylen) 717 { 718 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 719 720 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 721 keylen != AES_KEYSIZE_256) 722 return -EINVAL; 723 724 pr_debug("enter, keylen: %d\n", keylen); 725 726 memcpy(ctx->key, key, keylen); 727 ctx->keylen = keylen; 728 729 return 0; 730 } 731 732 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) 733 { 734 return omap_aes_crypt(req, FLAGS_ENCRYPT); 735 } 736 737 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) 738 { 739 return omap_aes_crypt(req, 0); 740 } 741 742 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) 743 { 744 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 745 } 746 747 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) 748 { 749 return omap_aes_crypt(req, FLAGS_CBC); 750 } 751 752 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) 753 { 754 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 755 } 756 757 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) 758 { 759 return omap_aes_crypt(req, FLAGS_CTR); 760 } 761 762 static int omap_aes_cra_init(struct crypto_tfm *tfm) 763 { 764 struct omap_aes_dev *dd = NULL; 765 int err; 766 767 /* Find AES device, currently picks the first device */ 768 spin_lock_bh(&list_lock); 769 list_for_each_entry(dd, &dev_list, list) { 770 break; 771 } 772 spin_unlock_bh(&list_lock); 773 774 err = pm_runtime_get_sync(dd->dev); 775 if (err < 0) { 776 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", 777 __func__, err); 778 return err; 779 } 780 781 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); 782 783 return 0; 784 } 785 786 static void omap_aes_cra_exit(struct crypto_tfm *tfm) 787 { 788 struct omap_aes_dev *dd = NULL; 789 790 /* Find AES device, currently picks the first device */ 791 spin_lock_bh(&list_lock); 792 list_for_each_entry(dd, &dev_list, list) { 793 break; 794 } 795 spin_unlock_bh(&list_lock); 796 797 pm_runtime_put_sync(dd->dev); 798 } 799 800 /* ********************** ALGS ************************************ */ 801 802 static struct crypto_alg algs_ecb_cbc[] = { 803 { 804 .cra_name = "ecb(aes)", 805 .cra_driver_name = "ecb-aes-omap", 806 .cra_priority = 300, 807 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 808 CRYPTO_ALG_KERN_DRIVER_ONLY | 809 CRYPTO_ALG_ASYNC, 810 .cra_blocksize = AES_BLOCK_SIZE, 811 .cra_ctxsize = sizeof(struct omap_aes_ctx), 812 .cra_alignmask = 0, 813 .cra_type = &crypto_ablkcipher_type, 814 .cra_module = THIS_MODULE, 815 .cra_init = omap_aes_cra_init, 816 .cra_exit = omap_aes_cra_exit, 817 .cra_u.ablkcipher = { 818 .min_keysize = AES_MIN_KEY_SIZE, 819 .max_keysize = AES_MAX_KEY_SIZE, 820 .setkey = omap_aes_setkey, 821 .encrypt = omap_aes_ecb_encrypt, 822 .decrypt = omap_aes_ecb_decrypt, 823 } 824 }, 825 { 826 .cra_name = "cbc(aes)", 827 .cra_driver_name = "cbc-aes-omap", 828 .cra_priority = 300, 829 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 830 CRYPTO_ALG_KERN_DRIVER_ONLY | 831 CRYPTO_ALG_ASYNC, 832 .cra_blocksize = AES_BLOCK_SIZE, 833 .cra_ctxsize = sizeof(struct omap_aes_ctx), 834 .cra_alignmask = 0, 835 .cra_type = &crypto_ablkcipher_type, 836 .cra_module = THIS_MODULE, 837 .cra_init = omap_aes_cra_init, 838 .cra_exit = omap_aes_cra_exit, 839 .cra_u.ablkcipher = { 840 .min_keysize = AES_MIN_KEY_SIZE, 841 .max_keysize = AES_MAX_KEY_SIZE, 842 .ivsize = AES_BLOCK_SIZE, 843 .setkey = omap_aes_setkey, 844 .encrypt = omap_aes_cbc_encrypt, 845 .decrypt = omap_aes_cbc_decrypt, 846 } 847 } 848 }; 849 850 static struct crypto_alg algs_ctr[] = { 851 { 852 .cra_name = "ctr(aes)", 853 .cra_driver_name = "ctr-aes-omap", 854 .cra_priority = 300, 855 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 856 CRYPTO_ALG_KERN_DRIVER_ONLY | 857 CRYPTO_ALG_ASYNC, 858 .cra_blocksize = AES_BLOCK_SIZE, 859 .cra_ctxsize = sizeof(struct omap_aes_ctx), 860 .cra_alignmask = 0, 861 .cra_type = &crypto_ablkcipher_type, 862 .cra_module = THIS_MODULE, 863 .cra_init = omap_aes_cra_init, 864 .cra_exit = omap_aes_cra_exit, 865 .cra_u.ablkcipher = { 866 .min_keysize = AES_MIN_KEY_SIZE, 867 .max_keysize = AES_MAX_KEY_SIZE, 868 .geniv = "eseqiv", 869 .ivsize = AES_BLOCK_SIZE, 870 .setkey = omap_aes_setkey, 871 .encrypt = omap_aes_ctr_encrypt, 872 .decrypt = omap_aes_ctr_decrypt, 873 } 874 } , 875 }; 876 877 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 878 { 879 .algs_list = algs_ecb_cbc, 880 .size = ARRAY_SIZE(algs_ecb_cbc), 881 }, 882 }; 883 884 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 885 .algs_info = omap_aes_algs_info_ecb_cbc, 886 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 887 .trigger = omap_aes_dma_trigger_omap2, 888 .key_ofs = 0x1c, 889 .iv_ofs = 0x20, 890 .ctrl_ofs = 0x30, 891 .data_ofs = 0x34, 892 .rev_ofs = 0x44, 893 .mask_ofs = 0x48, 894 .dma_enable_in = BIT(2), 895 .dma_enable_out = BIT(3), 896 .dma_start = BIT(5), 897 .major_mask = 0xf0, 898 .major_shift = 4, 899 .minor_mask = 0x0f, 900 .minor_shift = 0, 901 }; 902 903 #ifdef CONFIG_OF 904 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 905 { 906 .algs_list = algs_ecb_cbc, 907 .size = ARRAY_SIZE(algs_ecb_cbc), 908 }, 909 { 910 .algs_list = algs_ctr, 911 .size = ARRAY_SIZE(algs_ctr), 912 }, 913 }; 914 915 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 916 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 917 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 918 .trigger = omap_aes_dma_trigger_omap2, 919 .key_ofs = 0x1c, 920 .iv_ofs = 0x20, 921 .ctrl_ofs = 0x30, 922 .data_ofs = 0x34, 923 .rev_ofs = 0x44, 924 .mask_ofs = 0x48, 925 .dma_enable_in = BIT(2), 926 .dma_enable_out = BIT(3), 927 .dma_start = BIT(5), 928 .major_mask = 0xf0, 929 .major_shift = 4, 930 .minor_mask = 0x0f, 931 .minor_shift = 0, 932 }; 933 934 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 935 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 936 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 937 .trigger = omap_aes_dma_trigger_omap4, 938 .key_ofs = 0x3c, 939 .iv_ofs = 0x40, 940 .ctrl_ofs = 0x50, 941 .data_ofs = 0x60, 942 .rev_ofs = 0x80, 943 .mask_ofs = 0x84, 944 .irq_status_ofs = 0x8c, 945 .irq_enable_ofs = 0x90, 946 .dma_enable_in = BIT(5), 947 .dma_enable_out = BIT(6), 948 .major_mask = 0x0700, 949 .major_shift = 8, 950 .minor_mask = 0x003f, 951 .minor_shift = 0, 952 }; 953 954 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 955 { 956 struct omap_aes_dev *dd = dev_id; 957 u32 status, i; 958 u32 *src, *dst; 959 960 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 961 if (status & AES_REG_IRQ_DATA_IN) { 962 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 963 964 BUG_ON(!dd->in_sg); 965 966 BUG_ON(_calc_walked(in) > dd->in_sg->length); 967 968 src = sg_virt(dd->in_sg) + _calc_walked(in); 969 970 for (i = 0; i < AES_BLOCK_WORDS; i++) { 971 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 972 973 scatterwalk_advance(&dd->in_walk, 4); 974 if (dd->in_sg->length == _calc_walked(in)) { 975 dd->in_sg = sg_next(dd->in_sg); 976 if (dd->in_sg) { 977 scatterwalk_start(&dd->in_walk, 978 dd->in_sg); 979 src = sg_virt(dd->in_sg) + 980 _calc_walked(in); 981 } 982 } else { 983 src++; 984 } 985 } 986 987 /* Clear IRQ status */ 988 status &= ~AES_REG_IRQ_DATA_IN; 989 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 990 991 /* Enable DATA_OUT interrupt */ 992 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 993 994 } else if (status & AES_REG_IRQ_DATA_OUT) { 995 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 996 997 BUG_ON(!dd->out_sg); 998 999 BUG_ON(_calc_walked(out) > dd->out_sg->length); 1000 1001 dst = sg_virt(dd->out_sg) + _calc_walked(out); 1002 1003 for (i = 0; i < AES_BLOCK_WORDS; i++) { 1004 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 1005 scatterwalk_advance(&dd->out_walk, 4); 1006 if (dd->out_sg->length == _calc_walked(out)) { 1007 dd->out_sg = sg_next(dd->out_sg); 1008 if (dd->out_sg) { 1009 scatterwalk_start(&dd->out_walk, 1010 dd->out_sg); 1011 dst = sg_virt(dd->out_sg) + 1012 _calc_walked(out); 1013 } 1014 } else { 1015 dst++; 1016 } 1017 } 1018 1019 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 1020 1021 /* Clear IRQ status */ 1022 status &= ~AES_REG_IRQ_DATA_OUT; 1023 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 1024 1025 if (!dd->total) 1026 /* All bytes read! */ 1027 tasklet_schedule(&dd->done_task); 1028 else 1029 /* Enable DATA_IN interrupt for next block */ 1030 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 1031 } 1032 1033 return IRQ_HANDLED; 1034 } 1035 1036 static const struct of_device_id omap_aes_of_match[] = { 1037 { 1038 .compatible = "ti,omap2-aes", 1039 .data = &omap_aes_pdata_omap2, 1040 }, 1041 { 1042 .compatible = "ti,omap3-aes", 1043 .data = &omap_aes_pdata_omap3, 1044 }, 1045 { 1046 .compatible = "ti,omap4-aes", 1047 .data = &omap_aes_pdata_omap4, 1048 }, 1049 {}, 1050 }; 1051 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 1052 1053 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1054 struct device *dev, struct resource *res) 1055 { 1056 struct device_node *node = dev->of_node; 1057 const struct of_device_id *match; 1058 int err = 0; 1059 1060 match = of_match_device(of_match_ptr(omap_aes_of_match), dev); 1061 if (!match) { 1062 dev_err(dev, "no compatible OF match\n"); 1063 err = -EINVAL; 1064 goto err; 1065 } 1066 1067 err = of_address_to_resource(node, 0, res); 1068 if (err < 0) { 1069 dev_err(dev, "can't translate OF node address\n"); 1070 err = -EINVAL; 1071 goto err; 1072 } 1073 1074 dd->pdata = match->data; 1075 1076 err: 1077 return err; 1078 } 1079 #else 1080 static const struct of_device_id omap_aes_of_match[] = { 1081 {}, 1082 }; 1083 1084 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1085 struct device *dev, struct resource *res) 1086 { 1087 return -EINVAL; 1088 } 1089 #endif 1090 1091 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 1092 struct platform_device *pdev, struct resource *res) 1093 { 1094 struct device *dev = &pdev->dev; 1095 struct resource *r; 1096 int err = 0; 1097 1098 /* Get the base address */ 1099 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1100 if (!r) { 1101 dev_err(dev, "no MEM resource info\n"); 1102 err = -ENODEV; 1103 goto err; 1104 } 1105 memcpy(res, r, sizeof(*res)); 1106 1107 /* Only OMAP2/3 can be non-DT */ 1108 dd->pdata = &omap_aes_pdata_omap2; 1109 1110 err: 1111 return err; 1112 } 1113 1114 static int omap_aes_probe(struct platform_device *pdev) 1115 { 1116 struct device *dev = &pdev->dev; 1117 struct omap_aes_dev *dd; 1118 struct crypto_alg *algp; 1119 struct resource res; 1120 int err = -ENOMEM, i, j, irq = -1; 1121 u32 reg; 1122 1123 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1124 if (dd == NULL) { 1125 dev_err(dev, "unable to alloc data struct.\n"); 1126 goto err_data; 1127 } 1128 dd->dev = dev; 1129 platform_set_drvdata(pdev, dd); 1130 1131 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1132 omap_aes_get_res_pdev(dd, pdev, &res); 1133 if (err) 1134 goto err_res; 1135 1136 dd->io_base = devm_ioremap_resource(dev, &res); 1137 if (IS_ERR(dd->io_base)) { 1138 err = PTR_ERR(dd->io_base); 1139 goto err_res; 1140 } 1141 dd->phys_base = res.start; 1142 1143 pm_runtime_enable(dev); 1144 err = pm_runtime_get_sync(dev); 1145 if (err < 0) { 1146 dev_err(dev, "%s: failed to get_sync(%d)\n", 1147 __func__, err); 1148 goto err_res; 1149 } 1150 1151 omap_aes_dma_stop(dd); 1152 1153 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1154 1155 pm_runtime_put_sync(dev); 1156 1157 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1158 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1159 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1160 1161 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1162 1163 err = omap_aes_dma_init(dd); 1164 if (err == -EPROBE_DEFER) { 1165 goto err_irq; 1166 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1167 dd->pio_only = 1; 1168 1169 irq = platform_get_irq(pdev, 0); 1170 if (irq < 0) { 1171 dev_err(dev, "can't get IRQ resource\n"); 1172 goto err_irq; 1173 } 1174 1175 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1176 dev_name(dev), dd); 1177 if (err) { 1178 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1179 goto err_irq; 1180 } 1181 } 1182 1183 1184 INIT_LIST_HEAD(&dd->list); 1185 spin_lock(&list_lock); 1186 list_add_tail(&dd->list, &dev_list); 1187 spin_unlock(&list_lock); 1188 1189 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1190 if (!dd->pdata->algs_info[i].registered) { 1191 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1192 algp = &dd->pdata->algs_info[i].algs_list[j]; 1193 1194 pr_debug("reg alg: %s\n", algp->cra_name); 1195 INIT_LIST_HEAD(&algp->cra_list); 1196 1197 err = crypto_register_alg(algp); 1198 if (err) 1199 goto err_algs; 1200 1201 dd->pdata->algs_info[i].registered++; 1202 } 1203 } 1204 } 1205 1206 /* Initialize crypto engine */ 1207 dd->engine = crypto_engine_alloc_init(dev, 1); 1208 if (!dd->engine) 1209 goto err_algs; 1210 1211 dd->engine->prepare_request = omap_aes_prepare_req; 1212 dd->engine->crypt_one_request = omap_aes_crypt_req; 1213 err = crypto_engine_start(dd->engine); 1214 if (err) 1215 goto err_engine; 1216 1217 return 0; 1218 err_engine: 1219 crypto_engine_exit(dd->engine); 1220 err_algs: 1221 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1222 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1223 crypto_unregister_alg( 1224 &dd->pdata->algs_info[i].algs_list[j]); 1225 1226 omap_aes_dma_cleanup(dd); 1227 err_irq: 1228 tasklet_kill(&dd->done_task); 1229 pm_runtime_disable(dev); 1230 err_res: 1231 dd = NULL; 1232 err_data: 1233 dev_err(dev, "initialization failed.\n"); 1234 return err; 1235 } 1236 1237 static int omap_aes_remove(struct platform_device *pdev) 1238 { 1239 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1240 int i, j; 1241 1242 if (!dd) 1243 return -ENODEV; 1244 1245 spin_lock(&list_lock); 1246 list_del(&dd->list); 1247 spin_unlock(&list_lock); 1248 1249 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1250 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1251 crypto_unregister_alg( 1252 &dd->pdata->algs_info[i].algs_list[j]); 1253 1254 crypto_engine_exit(dd->engine); 1255 tasklet_kill(&dd->done_task); 1256 omap_aes_dma_cleanup(dd); 1257 pm_runtime_disable(dd->dev); 1258 dd = NULL; 1259 1260 return 0; 1261 } 1262 1263 #ifdef CONFIG_PM_SLEEP 1264 static int omap_aes_suspend(struct device *dev) 1265 { 1266 pm_runtime_put_sync(dev); 1267 return 0; 1268 } 1269 1270 static int omap_aes_resume(struct device *dev) 1271 { 1272 pm_runtime_get_sync(dev); 1273 return 0; 1274 } 1275 #endif 1276 1277 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1278 1279 static struct platform_driver omap_aes_driver = { 1280 .probe = omap_aes_probe, 1281 .remove = omap_aes_remove, 1282 .driver = { 1283 .name = "omap-aes", 1284 .pm = &omap_aes_pm_ops, 1285 .of_match_table = omap_aes_of_match, 1286 }, 1287 }; 1288 1289 module_platform_driver(omap_aes_driver); 1290 1291 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1292 MODULE_LICENSE("GPL v2"); 1293 MODULE_AUTHOR("Dmitry Kasatkin"); 1294 1295