1 /* 2 * Cryptographic API. 3 * 4 * Support for OMAP AES HW acceleration. 5 * 6 * Copyright (c) 2010 Nokia Corporation 7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 8 * Copyright (c) 2011 Texas Instruments Incorporated 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 */ 15 16 #define pr_fmt(fmt) "%20s: " fmt, __func__ 17 #define prn(num) pr_debug(#num "=%d\n", num) 18 #define prx(num) pr_debug(#num "=%x\n", num) 19 20 #include <linux/err.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/errno.h> 24 #include <linux/kernel.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/omap-dma.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/io.h> 35 #include <linux/crypto.h> 36 #include <linux/interrupt.h> 37 #include <crypto/scatterwalk.h> 38 #include <crypto/aes.h> 39 40 #define DST_MAXBURST 4 41 #define DMA_MIN (DST_MAXBURST * sizeof(u32)) 42 43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 44 45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 46 number. For example 7:0 */ 47 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 49 50 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 51 ((x ^ 0x01) * 0x04)) 52 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 53 54 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 55 #define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7) 56 #define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7) 57 #define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7) 58 #define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7) 59 #define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7) 60 #define AES_REG_CTRL_CTR (1 << 6) 61 #define AES_REG_CTRL_CBC (1 << 5) 62 #define AES_REG_CTRL_KEY_SIZE (3 << 3) 63 #define AES_REG_CTRL_DIRECTION (1 << 2) 64 #define AES_REG_CTRL_INPUT_READY (1 << 1) 65 #define AES_REG_CTRL_OUTPUT_READY (1 << 0) 66 67 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 68 69 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) 70 71 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 72 #define AES_REG_MASK_SIDLE (1 << 6) 73 #define AES_REG_MASK_START (1 << 5) 74 #define AES_REG_MASK_DMA_OUT_EN (1 << 3) 75 #define AES_REG_MASK_DMA_IN_EN (1 << 2) 76 #define AES_REG_MASK_SOFTRESET (1 << 1) 77 #define AES_REG_AUTOIDLE (1 << 0) 78 79 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) 80 81 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 82 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 83 #define AES_REG_IRQ_DATA_IN BIT(1) 84 #define AES_REG_IRQ_DATA_OUT BIT(2) 85 #define DEFAULT_TIMEOUT (5*HZ) 86 87 #define FLAGS_MODE_MASK 0x000f 88 #define FLAGS_ENCRYPT BIT(0) 89 #define FLAGS_CBC BIT(1) 90 #define FLAGS_GIV BIT(2) 91 #define FLAGS_CTR BIT(3) 92 93 #define FLAGS_INIT BIT(4) 94 #define FLAGS_FAST BIT(5) 95 #define FLAGS_BUSY BIT(6) 96 97 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) 98 99 struct omap_aes_ctx { 100 struct omap_aes_dev *dd; 101 102 int keylen; 103 u32 key[AES_KEYSIZE_256 / sizeof(u32)]; 104 unsigned long flags; 105 }; 106 107 struct omap_aes_reqctx { 108 unsigned long mode; 109 }; 110 111 #define OMAP_AES_QUEUE_LENGTH 1 112 #define OMAP_AES_CACHE_SIZE 0 113 114 struct omap_aes_algs_info { 115 struct crypto_alg *algs_list; 116 unsigned int size; 117 unsigned int registered; 118 }; 119 120 struct omap_aes_pdata { 121 struct omap_aes_algs_info *algs_info; 122 unsigned int algs_info_size; 123 124 void (*trigger)(struct omap_aes_dev *dd, int length); 125 126 u32 key_ofs; 127 u32 iv_ofs; 128 u32 ctrl_ofs; 129 u32 data_ofs; 130 u32 rev_ofs; 131 u32 mask_ofs; 132 u32 irq_enable_ofs; 133 u32 irq_status_ofs; 134 135 u32 dma_enable_in; 136 u32 dma_enable_out; 137 u32 dma_start; 138 139 u32 major_mask; 140 u32 major_shift; 141 u32 minor_mask; 142 u32 minor_shift; 143 }; 144 145 struct omap_aes_dev { 146 struct list_head list; 147 unsigned long phys_base; 148 void __iomem *io_base; 149 struct omap_aes_ctx *ctx; 150 struct device *dev; 151 unsigned long flags; 152 int err; 153 154 spinlock_t lock; 155 struct crypto_queue queue; 156 157 struct tasklet_struct done_task; 158 struct tasklet_struct queue_task; 159 160 struct ablkcipher_request *req; 161 size_t total; 162 struct scatterlist *in_sg; 163 struct scatterlist *out_sg; 164 struct scatter_walk in_walk; 165 struct scatter_walk out_walk; 166 int dma_in; 167 struct dma_chan *dma_lch_in; 168 int dma_out; 169 struct dma_chan *dma_lch_out; 170 int in_sg_len; 171 int out_sg_len; 172 const struct omap_aes_pdata *pdata; 173 }; 174 175 /* keep registered devices data here */ 176 static LIST_HEAD(dev_list); 177 static DEFINE_SPINLOCK(list_lock); 178 179 #ifdef DEBUG 180 #define omap_aes_read(dd, offset) \ 181 ({ \ 182 int _read_ret; \ 183 _read_ret = __raw_readl(dd->io_base + offset); \ 184 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 185 offset, _read_ret); \ 186 _read_ret; \ 187 }) 188 #else 189 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 190 { 191 return __raw_readl(dd->io_base + offset); 192 } 193 #endif 194 195 #ifdef DEBUG 196 #define omap_aes_write(dd, offset, value) \ 197 do { \ 198 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 199 offset, value); \ 200 __raw_writel(value, dd->io_base + offset); \ 201 } while (0) 202 #else 203 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 204 u32 value) 205 { 206 __raw_writel(value, dd->io_base + offset); 207 } 208 #endif 209 210 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 211 u32 value, u32 mask) 212 { 213 u32 val; 214 215 val = omap_aes_read(dd, offset); 216 val &= ~mask; 217 val |= value; 218 omap_aes_write(dd, offset, val); 219 } 220 221 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 222 u32 *value, int count) 223 { 224 for (; count--; value++, offset += 4) 225 omap_aes_write(dd, offset, *value); 226 } 227 228 static int omap_aes_hw_init(struct omap_aes_dev *dd) 229 { 230 if (!(dd->flags & FLAGS_INIT)) { 231 dd->flags |= FLAGS_INIT; 232 dd->err = 0; 233 } 234 235 return 0; 236 } 237 238 static int omap_aes_write_ctrl(struct omap_aes_dev *dd) 239 { 240 unsigned int key32; 241 int i, err; 242 u32 val, mask = 0; 243 244 err = omap_aes_hw_init(dd); 245 if (err) 246 return err; 247 248 key32 = dd->ctx->keylen / sizeof(u32); 249 250 /* it seems a key should always be set even if it has not changed */ 251 for (i = 0; i < key32; i++) { 252 omap_aes_write(dd, AES_REG_KEY(dd, i), 253 __le32_to_cpu(dd->ctx->key[i])); 254 } 255 256 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) 257 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); 258 259 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 260 if (dd->flags & FLAGS_CBC) 261 val |= AES_REG_CTRL_CBC; 262 if (dd->flags & FLAGS_CTR) { 263 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32; 264 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK; 265 } 266 if (dd->flags & FLAGS_ENCRYPT) 267 val |= AES_REG_CTRL_DIRECTION; 268 269 mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION | 270 AES_REG_CTRL_KEY_SIZE; 271 272 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask); 273 274 return 0; 275 } 276 277 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 278 { 279 u32 mask, val; 280 281 val = dd->pdata->dma_start; 282 283 if (dd->dma_lch_out != NULL) 284 val |= dd->pdata->dma_enable_out; 285 if (dd->dma_lch_in != NULL) 286 val |= dd->pdata->dma_enable_in; 287 288 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 289 dd->pdata->dma_start; 290 291 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 292 293 } 294 295 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 296 { 297 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 298 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 299 300 omap_aes_dma_trigger_omap2(dd, length); 301 } 302 303 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 304 { 305 u32 mask; 306 307 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 308 dd->pdata->dma_start; 309 310 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 311 } 312 313 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) 314 { 315 struct omap_aes_dev *dd = NULL, *tmp; 316 317 spin_lock_bh(&list_lock); 318 if (!ctx->dd) { 319 list_for_each_entry(tmp, &dev_list, list) { 320 /* FIXME: take fist available aes core */ 321 dd = tmp; 322 break; 323 } 324 ctx->dd = dd; 325 } else { 326 /* already found before */ 327 dd = ctx->dd; 328 } 329 spin_unlock_bh(&list_lock); 330 331 return dd; 332 } 333 334 static void omap_aes_dma_out_callback(void *data) 335 { 336 struct omap_aes_dev *dd = data; 337 338 /* dma_lch_out - completed */ 339 tasklet_schedule(&dd->done_task); 340 } 341 342 static int omap_aes_dma_init(struct omap_aes_dev *dd) 343 { 344 int err = -ENOMEM; 345 dma_cap_mask_t mask; 346 347 dd->dma_lch_out = NULL; 348 dd->dma_lch_in = NULL; 349 350 dma_cap_zero(mask); 351 dma_cap_set(DMA_SLAVE, mask); 352 353 dd->dma_lch_in = dma_request_slave_channel_compat(mask, 354 omap_dma_filter_fn, 355 &dd->dma_in, 356 dd->dev, "rx"); 357 if (!dd->dma_lch_in) { 358 dev_err(dd->dev, "Unable to request in DMA channel\n"); 359 goto err_dma_in; 360 } 361 362 dd->dma_lch_out = dma_request_slave_channel_compat(mask, 363 omap_dma_filter_fn, 364 &dd->dma_out, 365 dd->dev, "tx"); 366 if (!dd->dma_lch_out) { 367 dev_err(dd->dev, "Unable to request out DMA channel\n"); 368 goto err_dma_out; 369 } 370 371 return 0; 372 373 err_dma_out: 374 dma_release_channel(dd->dma_lch_in); 375 err_dma_in: 376 if (err) 377 pr_err("error: %d\n", err); 378 return err; 379 } 380 381 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 382 { 383 dma_release_channel(dd->dma_lch_out); 384 dma_release_channel(dd->dma_lch_in); 385 } 386 387 static void sg_copy_buf(void *buf, struct scatterlist *sg, 388 unsigned int start, unsigned int nbytes, int out) 389 { 390 struct scatter_walk walk; 391 392 if (!nbytes) 393 return; 394 395 scatterwalk_start(&walk, sg); 396 scatterwalk_advance(&walk, start); 397 scatterwalk_copychunks(buf, &walk, nbytes, out); 398 scatterwalk_done(&walk, out, 0); 399 } 400 401 static int omap_aes_crypt_dma(struct crypto_tfm *tfm, 402 struct scatterlist *in_sg, struct scatterlist *out_sg, 403 int in_sg_len, int out_sg_len) 404 { 405 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); 406 struct omap_aes_dev *dd = ctx->dd; 407 struct dma_async_tx_descriptor *tx_in, *tx_out; 408 struct dma_slave_config cfg; 409 int ret; 410 411 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 412 413 memset(&cfg, 0, sizeof(cfg)); 414 415 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 416 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 417 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 418 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 419 cfg.src_maxburst = DST_MAXBURST; 420 cfg.dst_maxburst = DST_MAXBURST; 421 422 /* IN */ 423 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 424 if (ret) { 425 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 426 ret); 427 return ret; 428 } 429 430 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 431 DMA_MEM_TO_DEV, 432 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 433 if (!tx_in) { 434 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 435 return -EINVAL; 436 } 437 438 /* No callback necessary */ 439 tx_in->callback_param = dd; 440 441 /* OUT */ 442 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 443 if (ret) { 444 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 445 ret); 446 return ret; 447 } 448 449 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 450 DMA_DEV_TO_MEM, 451 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 452 if (!tx_out) { 453 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 454 return -EINVAL; 455 } 456 457 tx_out->callback = omap_aes_dma_out_callback; 458 tx_out->callback_param = dd; 459 460 dmaengine_submit(tx_in); 461 dmaengine_submit(tx_out); 462 463 dma_async_issue_pending(dd->dma_lch_in); 464 dma_async_issue_pending(dd->dma_lch_out); 465 466 /* start DMA */ 467 dd->pdata->trigger(dd, dd->total); 468 469 return 0; 470 } 471 472 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 473 { 474 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 475 crypto_ablkcipher_reqtfm(dd->req)); 476 int err; 477 478 pr_debug("total: %d\n", dd->total); 479 480 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 481 if (!err) { 482 dev_err(dd->dev, "dma_map_sg() error\n"); 483 return -EINVAL; 484 } 485 486 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); 487 if (!err) { 488 dev_err(dd->dev, "dma_map_sg() error\n"); 489 return -EINVAL; 490 } 491 492 err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 493 dd->out_sg_len); 494 if (err) { 495 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 496 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 497 DMA_FROM_DEVICE); 498 } 499 500 return err; 501 } 502 503 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 504 { 505 struct ablkcipher_request *req = dd->req; 506 507 pr_debug("err: %d\n", err); 508 509 dd->flags &= ~FLAGS_BUSY; 510 511 req->base.complete(&req->base, err); 512 } 513 514 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 515 { 516 int err = 0; 517 518 pr_debug("total: %d\n", dd->total); 519 520 omap_aes_dma_stop(dd); 521 522 dmaengine_terminate_all(dd->dma_lch_in); 523 dmaengine_terminate_all(dd->dma_lch_out); 524 525 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 526 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); 527 528 return err; 529 } 530 531 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 532 struct ablkcipher_request *req) 533 { 534 struct crypto_async_request *async_req, *backlog; 535 struct omap_aes_ctx *ctx; 536 struct omap_aes_reqctx *rctx; 537 unsigned long flags; 538 int err, ret = 0; 539 540 spin_lock_irqsave(&dd->lock, flags); 541 if (req) 542 ret = ablkcipher_enqueue_request(&dd->queue, req); 543 if (dd->flags & FLAGS_BUSY) { 544 spin_unlock_irqrestore(&dd->lock, flags); 545 return ret; 546 } 547 backlog = crypto_get_backlog(&dd->queue); 548 async_req = crypto_dequeue_request(&dd->queue); 549 if (async_req) 550 dd->flags |= FLAGS_BUSY; 551 spin_unlock_irqrestore(&dd->lock, flags); 552 553 if (!async_req) 554 return ret; 555 556 if (backlog) 557 backlog->complete(backlog, -EINPROGRESS); 558 559 req = ablkcipher_request_cast(async_req); 560 561 /* assign new request to device */ 562 dd->req = req; 563 dd->total = req->nbytes; 564 dd->in_sg = req->src; 565 dd->out_sg = req->dst; 566 567 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total); 568 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total); 569 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0); 570 571 rctx = ablkcipher_request_ctx(req); 572 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 573 rctx->mode &= FLAGS_MODE_MASK; 574 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 575 576 dd->ctx = ctx; 577 ctx->dd = dd; 578 579 err = omap_aes_write_ctrl(dd); 580 if (!err) 581 err = omap_aes_crypt_dma_start(dd); 582 if (err) { 583 /* aes_task will not finish it, so do it here */ 584 omap_aes_finish_req(dd, err); 585 tasklet_schedule(&dd->queue_task); 586 } 587 588 return ret; /* return ret, which is enqueue return value */ 589 } 590 591 static void omap_aes_done_task(unsigned long data) 592 { 593 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 594 595 pr_debug("enter done_task\n"); 596 597 dma_sync_sg_for_cpu(dd->dev, dd->in_sg, dd->in_sg_len, DMA_FROM_DEVICE); 598 599 omap_aes_crypt_dma_stop(dd); 600 omap_aes_finish_req(dd, 0); 601 omap_aes_handle_queue(dd, NULL); 602 603 pr_debug("exit\n"); 604 } 605 606 static void omap_aes_queue_task(unsigned long data) 607 { 608 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 609 610 omap_aes_handle_queue(dd, NULL); 611 } 612 613 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) 614 { 615 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( 616 crypto_ablkcipher_reqtfm(req)); 617 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); 618 struct omap_aes_dev *dd; 619 620 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 621 !!(mode & FLAGS_ENCRYPT), 622 !!(mode & FLAGS_CBC)); 623 624 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { 625 pr_err("request size is not exact amount of AES blocks\n"); 626 return -EINVAL; 627 } 628 629 dd = omap_aes_find_dev(ctx); 630 if (!dd) 631 return -ENODEV; 632 633 rctx->mode = mode; 634 635 return omap_aes_handle_queue(dd, req); 636 } 637 638 /* ********************** ALG API ************************************ */ 639 640 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 641 unsigned int keylen) 642 { 643 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 644 645 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 646 keylen != AES_KEYSIZE_256) 647 return -EINVAL; 648 649 pr_debug("enter, keylen: %d\n", keylen); 650 651 memcpy(ctx->key, key, keylen); 652 ctx->keylen = keylen; 653 654 return 0; 655 } 656 657 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) 658 { 659 return omap_aes_crypt(req, FLAGS_ENCRYPT); 660 } 661 662 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) 663 { 664 return omap_aes_crypt(req, 0); 665 } 666 667 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) 668 { 669 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 670 } 671 672 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) 673 { 674 return omap_aes_crypt(req, FLAGS_CBC); 675 } 676 677 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) 678 { 679 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 680 } 681 682 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) 683 { 684 return omap_aes_crypt(req, FLAGS_CTR); 685 } 686 687 static int omap_aes_cra_init(struct crypto_tfm *tfm) 688 { 689 struct omap_aes_dev *dd = NULL; 690 691 /* Find AES device, currently picks the first device */ 692 spin_lock_bh(&list_lock); 693 list_for_each_entry(dd, &dev_list, list) { 694 break; 695 } 696 spin_unlock_bh(&list_lock); 697 698 pm_runtime_get_sync(dd->dev); 699 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); 700 701 return 0; 702 } 703 704 static void omap_aes_cra_exit(struct crypto_tfm *tfm) 705 { 706 struct omap_aes_dev *dd = NULL; 707 708 /* Find AES device, currently picks the first device */ 709 spin_lock_bh(&list_lock); 710 list_for_each_entry(dd, &dev_list, list) { 711 break; 712 } 713 spin_unlock_bh(&list_lock); 714 715 pm_runtime_put_sync(dd->dev); 716 } 717 718 /* ********************** ALGS ************************************ */ 719 720 static struct crypto_alg algs_ecb_cbc[] = { 721 { 722 .cra_name = "ecb(aes)", 723 .cra_driver_name = "ecb-aes-omap", 724 .cra_priority = 100, 725 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 726 CRYPTO_ALG_KERN_DRIVER_ONLY | 727 CRYPTO_ALG_ASYNC, 728 .cra_blocksize = AES_BLOCK_SIZE, 729 .cra_ctxsize = sizeof(struct omap_aes_ctx), 730 .cra_alignmask = 0, 731 .cra_type = &crypto_ablkcipher_type, 732 .cra_module = THIS_MODULE, 733 .cra_init = omap_aes_cra_init, 734 .cra_exit = omap_aes_cra_exit, 735 .cra_u.ablkcipher = { 736 .min_keysize = AES_MIN_KEY_SIZE, 737 .max_keysize = AES_MAX_KEY_SIZE, 738 .setkey = omap_aes_setkey, 739 .encrypt = omap_aes_ecb_encrypt, 740 .decrypt = omap_aes_ecb_decrypt, 741 } 742 }, 743 { 744 .cra_name = "cbc(aes)", 745 .cra_driver_name = "cbc-aes-omap", 746 .cra_priority = 100, 747 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 748 CRYPTO_ALG_KERN_DRIVER_ONLY | 749 CRYPTO_ALG_ASYNC, 750 .cra_blocksize = AES_BLOCK_SIZE, 751 .cra_ctxsize = sizeof(struct omap_aes_ctx), 752 .cra_alignmask = 0, 753 .cra_type = &crypto_ablkcipher_type, 754 .cra_module = THIS_MODULE, 755 .cra_init = omap_aes_cra_init, 756 .cra_exit = omap_aes_cra_exit, 757 .cra_u.ablkcipher = { 758 .min_keysize = AES_MIN_KEY_SIZE, 759 .max_keysize = AES_MAX_KEY_SIZE, 760 .ivsize = AES_BLOCK_SIZE, 761 .setkey = omap_aes_setkey, 762 .encrypt = omap_aes_cbc_encrypt, 763 .decrypt = omap_aes_cbc_decrypt, 764 } 765 } 766 }; 767 768 static struct crypto_alg algs_ctr[] = { 769 { 770 .cra_name = "ctr(aes)", 771 .cra_driver_name = "ctr-aes-omap", 772 .cra_priority = 100, 773 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 774 CRYPTO_ALG_KERN_DRIVER_ONLY | 775 CRYPTO_ALG_ASYNC, 776 .cra_blocksize = AES_BLOCK_SIZE, 777 .cra_ctxsize = sizeof(struct omap_aes_ctx), 778 .cra_alignmask = 0, 779 .cra_type = &crypto_ablkcipher_type, 780 .cra_module = THIS_MODULE, 781 .cra_init = omap_aes_cra_init, 782 .cra_exit = omap_aes_cra_exit, 783 .cra_u.ablkcipher = { 784 .min_keysize = AES_MIN_KEY_SIZE, 785 .max_keysize = AES_MAX_KEY_SIZE, 786 .geniv = "eseqiv", 787 .ivsize = AES_BLOCK_SIZE, 788 .setkey = omap_aes_setkey, 789 .encrypt = omap_aes_ctr_encrypt, 790 .decrypt = omap_aes_ctr_decrypt, 791 } 792 } , 793 }; 794 795 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 796 { 797 .algs_list = algs_ecb_cbc, 798 .size = ARRAY_SIZE(algs_ecb_cbc), 799 }, 800 }; 801 802 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 803 .algs_info = omap_aes_algs_info_ecb_cbc, 804 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 805 .trigger = omap_aes_dma_trigger_omap2, 806 .key_ofs = 0x1c, 807 .iv_ofs = 0x20, 808 .ctrl_ofs = 0x30, 809 .data_ofs = 0x34, 810 .rev_ofs = 0x44, 811 .mask_ofs = 0x48, 812 .dma_enable_in = BIT(2), 813 .dma_enable_out = BIT(3), 814 .dma_start = BIT(5), 815 .major_mask = 0xf0, 816 .major_shift = 4, 817 .minor_mask = 0x0f, 818 .minor_shift = 0, 819 }; 820 821 #ifdef CONFIG_OF 822 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 823 { 824 .algs_list = algs_ecb_cbc, 825 .size = ARRAY_SIZE(algs_ecb_cbc), 826 }, 827 { 828 .algs_list = algs_ctr, 829 .size = ARRAY_SIZE(algs_ctr), 830 }, 831 }; 832 833 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 834 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 835 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 836 .trigger = omap_aes_dma_trigger_omap2, 837 .key_ofs = 0x1c, 838 .iv_ofs = 0x20, 839 .ctrl_ofs = 0x30, 840 .data_ofs = 0x34, 841 .rev_ofs = 0x44, 842 .mask_ofs = 0x48, 843 .dma_enable_in = BIT(2), 844 .dma_enable_out = BIT(3), 845 .dma_start = BIT(5), 846 .major_mask = 0xf0, 847 .major_shift = 4, 848 .minor_mask = 0x0f, 849 .minor_shift = 0, 850 }; 851 852 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 853 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 854 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 855 .trigger = omap_aes_dma_trigger_omap4, 856 .key_ofs = 0x3c, 857 .iv_ofs = 0x40, 858 .ctrl_ofs = 0x50, 859 .data_ofs = 0x60, 860 .rev_ofs = 0x80, 861 .mask_ofs = 0x84, 862 .irq_status_ofs = 0x8c, 863 .irq_enable_ofs = 0x90, 864 .dma_enable_in = BIT(5), 865 .dma_enable_out = BIT(6), 866 .major_mask = 0x0700, 867 .major_shift = 8, 868 .minor_mask = 0x003f, 869 .minor_shift = 0, 870 }; 871 872 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 873 { 874 struct omap_aes_dev *dd = dev_id; 875 u32 status, i; 876 u32 *src, *dst; 877 878 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 879 if (status & AES_REG_IRQ_DATA_IN) { 880 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 881 882 BUG_ON(!dd->in_sg); 883 884 BUG_ON(_calc_walked(in) > dd->in_sg->length); 885 886 src = sg_virt(dd->in_sg) + _calc_walked(in); 887 888 for (i = 0; i < AES_BLOCK_WORDS; i++) { 889 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 890 891 scatterwalk_advance(&dd->in_walk, 4); 892 if (dd->in_sg->length == _calc_walked(in)) { 893 dd->in_sg = scatterwalk_sg_next(dd->in_sg); 894 if (dd->in_sg) { 895 scatterwalk_start(&dd->in_walk, 896 dd->in_sg); 897 src = sg_virt(dd->in_sg) + 898 _calc_walked(in); 899 } 900 } else { 901 src++; 902 } 903 } 904 905 /* Clear IRQ status */ 906 status &= ~AES_REG_IRQ_DATA_IN; 907 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 908 909 /* Enable DATA_OUT interrupt */ 910 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 911 912 } else if (status & AES_REG_IRQ_DATA_OUT) { 913 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 914 915 BUG_ON(!dd->out_sg); 916 917 BUG_ON(_calc_walked(out) > dd->out_sg->length); 918 919 dst = sg_virt(dd->out_sg) + _calc_walked(out); 920 921 for (i = 0; i < AES_BLOCK_WORDS; i++) { 922 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 923 scatterwalk_advance(&dd->out_walk, 4); 924 if (dd->out_sg->length == _calc_walked(out)) { 925 dd->out_sg = scatterwalk_sg_next(dd->out_sg); 926 if (dd->out_sg) { 927 scatterwalk_start(&dd->out_walk, 928 dd->out_sg); 929 dst = sg_virt(dd->out_sg) + 930 _calc_walked(out); 931 } 932 } else { 933 dst++; 934 } 935 } 936 937 dd->total -= AES_BLOCK_SIZE; 938 939 BUG_ON(dd->total < 0); 940 941 /* Clear IRQ status */ 942 status &= ~AES_REG_IRQ_DATA_OUT; 943 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 944 945 if (!dd->total) 946 /* All bytes read! */ 947 tasklet_schedule(&dd->done_task); 948 else 949 /* Enable DATA_IN interrupt for next block */ 950 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 951 } 952 953 return IRQ_HANDLED; 954 } 955 956 static const struct of_device_id omap_aes_of_match[] = { 957 { 958 .compatible = "ti,omap2-aes", 959 .data = &omap_aes_pdata_omap2, 960 }, 961 { 962 .compatible = "ti,omap3-aes", 963 .data = &omap_aes_pdata_omap3, 964 }, 965 { 966 .compatible = "ti,omap4-aes", 967 .data = &omap_aes_pdata_omap4, 968 }, 969 {}, 970 }; 971 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 972 973 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 974 struct device *dev, struct resource *res) 975 { 976 struct device_node *node = dev->of_node; 977 const struct of_device_id *match; 978 int err = 0; 979 980 match = of_match_device(of_match_ptr(omap_aes_of_match), dev); 981 if (!match) { 982 dev_err(dev, "no compatible OF match\n"); 983 err = -EINVAL; 984 goto err; 985 } 986 987 err = of_address_to_resource(node, 0, res); 988 if (err < 0) { 989 dev_err(dev, "can't translate OF node address\n"); 990 err = -EINVAL; 991 goto err; 992 } 993 994 dd->dma_out = -1; /* Dummy value that's unused */ 995 dd->dma_in = -1; /* Dummy value that's unused */ 996 997 dd->pdata = match->data; 998 999 err: 1000 return err; 1001 } 1002 #else 1003 static const struct of_device_id omap_aes_of_match[] = { 1004 {}, 1005 }; 1006 1007 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 1008 struct device *dev, struct resource *res) 1009 { 1010 return -EINVAL; 1011 } 1012 #endif 1013 1014 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 1015 struct platform_device *pdev, struct resource *res) 1016 { 1017 struct device *dev = &pdev->dev; 1018 struct resource *r; 1019 int err = 0; 1020 1021 /* Get the base address */ 1022 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1023 if (!r) { 1024 dev_err(dev, "no MEM resource info\n"); 1025 err = -ENODEV; 1026 goto err; 1027 } 1028 memcpy(res, r, sizeof(*res)); 1029 1030 /* Get the DMA out channel */ 1031 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1032 if (!r) { 1033 dev_err(dev, "no DMA out resource info\n"); 1034 err = -ENODEV; 1035 goto err; 1036 } 1037 dd->dma_out = r->start; 1038 1039 /* Get the DMA in channel */ 1040 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1041 if (!r) { 1042 dev_err(dev, "no DMA in resource info\n"); 1043 err = -ENODEV; 1044 goto err; 1045 } 1046 dd->dma_in = r->start; 1047 1048 /* Only OMAP2/3 can be non-DT */ 1049 dd->pdata = &omap_aes_pdata_omap2; 1050 1051 err: 1052 return err; 1053 } 1054 1055 static int omap_aes_probe(struct platform_device *pdev) 1056 { 1057 struct device *dev = &pdev->dev; 1058 struct omap_aes_dev *dd; 1059 struct crypto_alg *algp; 1060 struct resource res; 1061 int err = -ENOMEM, i, j; 1062 u32 reg; 1063 1064 dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL); 1065 if (dd == NULL) { 1066 dev_err(dev, "unable to alloc data struct.\n"); 1067 goto err_data; 1068 } 1069 dd->dev = dev; 1070 platform_set_drvdata(pdev, dd); 1071 1072 spin_lock_init(&dd->lock); 1073 crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH); 1074 1075 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1076 omap_aes_get_res_pdev(dd, pdev, &res); 1077 if (err) 1078 goto err_res; 1079 1080 dd->io_base = devm_ioremap_resource(dev, &res); 1081 if (IS_ERR(dd->io_base)) { 1082 err = PTR_ERR(dd->io_base); 1083 goto err_res; 1084 } 1085 dd->phys_base = res.start; 1086 1087 pm_runtime_enable(dev); 1088 pm_runtime_get_sync(dev); 1089 1090 omap_aes_dma_stop(dd); 1091 1092 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1093 1094 pm_runtime_put_sync(dev); 1095 1096 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1097 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1098 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1099 1100 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1101 tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd); 1102 1103 err = omap_aes_dma_init(dd); 1104 if (err) 1105 goto err_dma; 1106 1107 INIT_LIST_HEAD(&dd->list); 1108 spin_lock(&list_lock); 1109 list_add_tail(&dd->list, &dev_list); 1110 spin_unlock(&list_lock); 1111 1112 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1113 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1114 algp = &dd->pdata->algs_info[i].algs_list[j]; 1115 1116 pr_debug("reg alg: %s\n", algp->cra_name); 1117 INIT_LIST_HEAD(&algp->cra_list); 1118 1119 err = crypto_register_alg(algp); 1120 if (err) 1121 goto err_algs; 1122 1123 dd->pdata->algs_info[i].registered++; 1124 } 1125 } 1126 1127 return 0; 1128 err_algs: 1129 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1130 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1131 crypto_unregister_alg( 1132 &dd->pdata->algs_info[i].algs_list[j]); 1133 omap_aes_dma_cleanup(dd); 1134 err_dma: 1135 tasklet_kill(&dd->done_task); 1136 tasklet_kill(&dd->queue_task); 1137 pm_runtime_disable(dev); 1138 err_res: 1139 kfree(dd); 1140 dd = NULL; 1141 err_data: 1142 dev_err(dev, "initialization failed.\n"); 1143 return err; 1144 } 1145 1146 static int omap_aes_remove(struct platform_device *pdev) 1147 { 1148 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1149 int i, j; 1150 1151 if (!dd) 1152 return -ENODEV; 1153 1154 spin_lock(&list_lock); 1155 list_del(&dd->list); 1156 spin_unlock(&list_lock); 1157 1158 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1159 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1160 crypto_unregister_alg( 1161 &dd->pdata->algs_info[i].algs_list[j]); 1162 1163 tasklet_kill(&dd->done_task); 1164 tasklet_kill(&dd->queue_task); 1165 omap_aes_dma_cleanup(dd); 1166 pm_runtime_disable(dd->dev); 1167 kfree(dd); 1168 dd = NULL; 1169 1170 return 0; 1171 } 1172 1173 #ifdef CONFIG_PM_SLEEP 1174 static int omap_aes_suspend(struct device *dev) 1175 { 1176 pm_runtime_put_sync(dev); 1177 return 0; 1178 } 1179 1180 static int omap_aes_resume(struct device *dev) 1181 { 1182 pm_runtime_get_sync(dev); 1183 return 0; 1184 } 1185 #endif 1186 1187 static const struct dev_pm_ops omap_aes_pm_ops = { 1188 SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume) 1189 }; 1190 1191 static struct platform_driver omap_aes_driver = { 1192 .probe = omap_aes_probe, 1193 .remove = omap_aes_remove, 1194 .driver = { 1195 .name = "omap-aes", 1196 .owner = THIS_MODULE, 1197 .pm = &omap_aes_pm_ops, 1198 .of_match_table = omap_aes_of_match, 1199 }, 1200 }; 1201 1202 module_platform_driver(omap_aes_driver); 1203 1204 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1205 MODULE_LICENSE("GPL v2"); 1206 MODULE_AUTHOR("Dmitry Kasatkin"); 1207 1208