1 /** 2 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver 3 * 4 * Copyright (C) 2011-2012 International Business Machines Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 only. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * Author: Kent Yoder <yoder1@us.ibm.com> 20 */ 21 22 #include <crypto/internal/hash.h> 23 #include <crypto/sha.h> 24 #include <linux/module.h> 25 #include <asm/vio.h> 26 27 #include "nx_csbcpb.h" 28 #include "nx.h" 29 30 31 static int nx_sha512_init(struct shash_desc *desc) 32 { 33 struct sha512_state *sctx = shash_desc_ctx(desc); 34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 35 struct nx_sg *out_sg; 36 37 nx_ctx_init(nx_ctx, HCOP_FC_SHA); 38 39 memset(sctx, 0, sizeof *sctx); 40 41 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512]; 42 43 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512); 44 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state, 45 SHA512_DIGEST_SIZE, nx_ctx->ap->sglen); 46 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 47 48 return 0; 49 } 50 51 static int nx_sha512_update(struct shash_desc *desc, const u8 *data, 52 unsigned int len) 53 { 54 struct sha512_state *sctx = shash_desc_ctx(desc); 55 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 56 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 57 struct nx_sg *in_sg; 58 u64 to_process, leftover, total, spbc_bits; 59 u32 max_sg_len; 60 unsigned long irq_flags; 61 int rc = 0; 62 63 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 64 65 /* 2 cases for total data len: 66 * 1: < SHA512_BLOCK_SIZE: copy into state, return 0 67 * 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover 68 */ 69 total = sctx->count[0] + len; 70 if (total < SHA512_BLOCK_SIZE) { 71 memcpy(sctx->buf + sctx->count[0], data, len); 72 sctx->count[0] += len; 73 goto out; 74 } 75 76 in_sg = nx_ctx->in_sg; 77 max_sg_len = min_t(u32, nx_driver.of.max_sg_len/sizeof(struct nx_sg), 78 nx_ctx->ap->sglen); 79 80 do { 81 /* 82 * to_process: the SHA512_BLOCK_SIZE data chunk to process in 83 * this update. This value is also restricted by the sg list 84 * limits. 85 */ 86 to_process = min_t(u64, total, nx_ctx->ap->databytelen); 87 to_process = min_t(u64, to_process, 88 NX_PAGE_SIZE * (max_sg_len - 1)); 89 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1); 90 leftover = total - to_process; 91 92 if (sctx->count[0]) { 93 in_sg = nx_build_sg_list(nx_ctx->in_sg, 94 (u8 *) sctx->buf, 95 sctx->count[0], max_sg_len); 96 } 97 in_sg = nx_build_sg_list(in_sg, (u8 *) data, 98 to_process - sctx->count[0], 99 max_sg_len); 100 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * 101 sizeof(struct nx_sg); 102 103 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) { 104 /* 105 * we've hit the nx chip previously and we're updating 106 * again, so copy over the partial digest. 107 */ 108 memcpy(csbcpb->cpb.sha512.input_partial_digest, 109 csbcpb->cpb.sha512.message_digest, 110 SHA512_DIGEST_SIZE); 111 } 112 113 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; 114 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) { 115 rc = -EINVAL; 116 goto out; 117 } 118 119 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 120 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP); 121 if (rc) 122 goto out; 123 124 atomic_inc(&(nx_ctx->stats->sha512_ops)); 125 spbc_bits = csbcpb->cpb.sha512.spbc * 8; 126 csbcpb->cpb.sha512.message_bit_length_lo += spbc_bits; 127 if (csbcpb->cpb.sha512.message_bit_length_lo < spbc_bits) 128 csbcpb->cpb.sha512.message_bit_length_hi++; 129 130 /* everything after the first update is continuation */ 131 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 132 133 total -= to_process; 134 data += to_process - sctx->count[0]; 135 sctx->count[0] = 0; 136 in_sg = nx_ctx->in_sg; 137 } while (leftover >= SHA512_BLOCK_SIZE); 138 139 /* copy the leftover back into the state struct */ 140 if (leftover) 141 memcpy(sctx->buf, data, leftover); 142 sctx->count[0] = leftover; 143 out: 144 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 145 return rc; 146 } 147 148 static int nx_sha512_final(struct shash_desc *desc, u8 *out) 149 { 150 struct sha512_state *sctx = shash_desc_ctx(desc); 151 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 152 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 153 struct nx_sg *in_sg, *out_sg; 154 u32 max_sg_len; 155 u64 count0; 156 unsigned long irq_flags; 157 int rc; 158 159 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 160 161 max_sg_len = min_t(u32, nx_driver.of.max_sg_len, nx_ctx->ap->sglen); 162 163 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) { 164 /* we've hit the nx chip previously, now we're finalizing, 165 * so copy over the partial digest */ 166 memcpy(csbcpb->cpb.sha512.input_partial_digest, 167 csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); 168 } 169 170 /* final is represented by continuing the operation and indicating that 171 * this is not an intermediate operation */ 172 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 173 174 count0 = sctx->count[0] * 8; 175 176 csbcpb->cpb.sha512.message_bit_length_lo += count0; 177 if (csbcpb->cpb.sha512.message_bit_length_lo < count0) 178 csbcpb->cpb.sha512.message_bit_length_hi++; 179 180 in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, sctx->count[0], 181 max_sg_len); 182 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, SHA512_DIGEST_SIZE, 183 max_sg_len); 184 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 185 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 186 187 if (!nx_ctx->op.outlen) { 188 rc = -EINVAL; 189 goto out; 190 } 191 192 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 193 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP); 194 if (rc) 195 goto out; 196 197 atomic_inc(&(nx_ctx->stats->sha512_ops)); 198 atomic64_add(csbcpb->cpb.sha512.message_bit_length_lo / 8, 199 &(nx_ctx->stats->sha512_bytes)); 200 201 memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); 202 out: 203 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 204 return rc; 205 } 206 207 static int nx_sha512_export(struct shash_desc *desc, void *out) 208 { 209 struct sha512_state *sctx = shash_desc_ctx(desc); 210 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 211 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 212 struct sha512_state *octx = out; 213 unsigned long irq_flags; 214 215 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 216 217 /* move message_bit_length (128 bits) into count and convert its value 218 * to bytes */ 219 octx->count[0] = csbcpb->cpb.sha512.message_bit_length_lo >> 3 | 220 ((csbcpb->cpb.sha512.message_bit_length_hi & 7) << 61); 221 octx->count[1] = csbcpb->cpb.sha512.message_bit_length_hi >> 3; 222 223 octx->count[0] += sctx->count[0]; 224 if (octx->count[0] < sctx->count[0]) 225 octx->count[1]++; 226 227 memcpy(octx->buf, sctx->buf, sizeof(octx->buf)); 228 229 /* if no data has been processed yet, we need to export SHA512's 230 * initial data, in case this context gets imported into a software 231 * context */ 232 if (csbcpb->cpb.sha512.message_bit_length_hi || 233 csbcpb->cpb.sha512.message_bit_length_lo) 234 memcpy(octx->state, csbcpb->cpb.sha512.message_digest, 235 SHA512_DIGEST_SIZE); 236 else { 237 octx->state[0] = SHA512_H0; 238 octx->state[1] = SHA512_H1; 239 octx->state[2] = SHA512_H2; 240 octx->state[3] = SHA512_H3; 241 octx->state[4] = SHA512_H4; 242 octx->state[5] = SHA512_H5; 243 octx->state[6] = SHA512_H6; 244 octx->state[7] = SHA512_H7; 245 } 246 247 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 248 return 0; 249 } 250 251 static int nx_sha512_import(struct shash_desc *desc, const void *in) 252 { 253 struct sha512_state *sctx = shash_desc_ctx(desc); 254 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 255 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 256 const struct sha512_state *ictx = in; 257 unsigned long irq_flags; 258 259 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 260 261 memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf)); 262 sctx->count[0] = ictx->count[0] & 0x3f; 263 csbcpb->cpb.sha512.message_bit_length_lo = (ictx->count[0] & ~0x3f) 264 << 3; 265 csbcpb->cpb.sha512.message_bit_length_hi = ictx->count[1] << 3 | 266 ictx->count[0] >> 61; 267 268 if (csbcpb->cpb.sha512.message_bit_length_hi || 269 csbcpb->cpb.sha512.message_bit_length_lo) { 270 memcpy(csbcpb->cpb.sha512.message_digest, ictx->state, 271 SHA512_DIGEST_SIZE); 272 273 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 274 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; 275 } 276 277 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 278 return 0; 279 } 280 281 struct shash_alg nx_shash_sha512_alg = { 282 .digestsize = SHA512_DIGEST_SIZE, 283 .init = nx_sha512_init, 284 .update = nx_sha512_update, 285 .final = nx_sha512_final, 286 .export = nx_sha512_export, 287 .import = nx_sha512_import, 288 .descsize = sizeof(struct sha512_state), 289 .statesize = sizeof(struct sha512_state), 290 .base = { 291 .cra_name = "sha512", 292 .cra_driver_name = "sha512-nx", 293 .cra_priority = 300, 294 .cra_flags = CRYPTO_ALG_TYPE_SHASH, 295 .cra_blocksize = SHA512_BLOCK_SIZE, 296 .cra_module = THIS_MODULE, 297 .cra_ctxsize = sizeof(struct nx_crypto_ctx), 298 .cra_init = nx_crypto_ctx_sha_init, 299 .cra_exit = nx_crypto_ctx_exit, 300 } 301 }; 302