1 /** 2 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver 3 * 4 * Copyright (C) 2011-2012 International Business Machines Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 only. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * Author: Kent Yoder <yoder1@us.ibm.com> 20 */ 21 22 #include <crypto/internal/hash.h> 23 #include <crypto/sha.h> 24 #include <linux/module.h> 25 #include <asm/vio.h> 26 27 #include "nx_csbcpb.h" 28 #include "nx.h" 29 30 31 static int nx_sha512_init(struct shash_desc *desc) 32 { 33 struct sha512_state *sctx = shash_desc_ctx(desc); 34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 35 struct nx_sg *out_sg; 36 int len; 37 u32 max_sg_len; 38 39 nx_ctx_init(nx_ctx, HCOP_FC_SHA); 40 41 memset(sctx, 0, sizeof *sctx); 42 43 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512]; 44 45 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512); 46 47 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 48 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 49 max_sg_len = min_t(u64, max_sg_len, 50 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 51 52 len = SHA512_DIGEST_SIZE; 53 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state, 54 &len, max_sg_len); 55 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 56 57 if (len != SHA512_DIGEST_SIZE) 58 return -EINVAL; 59 60 sctx->state[0] = __cpu_to_be64(SHA512_H0); 61 sctx->state[1] = __cpu_to_be64(SHA512_H1); 62 sctx->state[2] = __cpu_to_be64(SHA512_H2); 63 sctx->state[3] = __cpu_to_be64(SHA512_H3); 64 sctx->state[4] = __cpu_to_be64(SHA512_H4); 65 sctx->state[5] = __cpu_to_be64(SHA512_H5); 66 sctx->state[6] = __cpu_to_be64(SHA512_H6); 67 sctx->state[7] = __cpu_to_be64(SHA512_H7); 68 sctx->count[0] = 0; 69 70 return 0; 71 } 72 73 static int nx_sha512_update(struct shash_desc *desc, const u8 *data, 74 unsigned int len) 75 { 76 struct sha512_state *sctx = shash_desc_ctx(desc); 77 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 78 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 79 struct nx_sg *in_sg; 80 u64 to_process, leftover = 0, total; 81 unsigned long irq_flags; 82 int rc = 0; 83 int data_len; 84 u32 max_sg_len; 85 u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE); 86 87 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 88 89 /* 2 cases for total data len: 90 * 1: < SHA512_BLOCK_SIZE: copy into state, return 0 91 * 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover 92 */ 93 total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len; 94 if (total < SHA512_BLOCK_SIZE) { 95 memcpy(sctx->buf + buf_len, data, len); 96 sctx->count[0] += len; 97 goto out; 98 } 99 100 memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE); 101 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; 102 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 103 104 in_sg = nx_ctx->in_sg; 105 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 106 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 107 max_sg_len = min_t(u64, max_sg_len, 108 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 109 110 do { 111 /* 112 * to_process: the SHA512_BLOCK_SIZE data chunk to process in 113 * this update. This value is also restricted by the sg list 114 * limits. 115 */ 116 to_process = total - leftover; 117 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1); 118 leftover = total - to_process; 119 120 if (buf_len) { 121 data_len = buf_len; 122 in_sg = nx_build_sg_list(nx_ctx->in_sg, 123 (u8 *) sctx->buf, 124 &data_len, max_sg_len); 125 126 if (data_len != buf_len) { 127 rc = -EINVAL; 128 goto out; 129 } 130 } 131 132 data_len = to_process - buf_len; 133 in_sg = nx_build_sg_list(in_sg, (u8 *) data, 134 &data_len, max_sg_len); 135 136 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 137 138 if (data_len != (to_process - buf_len)) { 139 rc = -EINVAL; 140 goto out; 141 } 142 143 to_process = (data_len + buf_len); 144 leftover = total - to_process; 145 146 /* 147 * we've hit the nx chip previously and we're updating 148 * again, so copy over the partial digest. 149 */ 150 memcpy(csbcpb->cpb.sha512.input_partial_digest, 151 csbcpb->cpb.sha512.message_digest, 152 SHA512_DIGEST_SIZE); 153 154 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) { 155 rc = -EINVAL; 156 goto out; 157 } 158 159 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 160 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP); 161 if (rc) 162 goto out; 163 164 atomic_inc(&(nx_ctx->stats->sha512_ops)); 165 166 total -= to_process; 167 data += to_process - buf_len; 168 buf_len = 0; 169 170 } while (leftover >= SHA512_BLOCK_SIZE); 171 172 /* copy the leftover back into the state struct */ 173 if (leftover) 174 memcpy(sctx->buf, data, leftover); 175 sctx->count[0] += len; 176 memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); 177 out: 178 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 179 return rc; 180 } 181 182 static int nx_sha512_final(struct shash_desc *desc, u8 *out) 183 { 184 struct sha512_state *sctx = shash_desc_ctx(desc); 185 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 186 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 187 struct nx_sg *in_sg, *out_sg; 188 u32 max_sg_len; 189 u64 count0; 190 unsigned long irq_flags; 191 int rc = 0; 192 int len; 193 194 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 195 196 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 197 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 198 max_sg_len = min_t(u64, max_sg_len, 199 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 200 201 /* final is represented by continuing the operation and indicating that 202 * this is not an intermediate operation */ 203 if (sctx->count[0] >= SHA512_BLOCK_SIZE) { 204 /* we've hit the nx chip previously, now we're finalizing, 205 * so copy over the partial digest */ 206 memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state, 207 SHA512_DIGEST_SIZE); 208 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 209 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 210 } else { 211 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 212 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION; 213 } 214 215 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 216 217 count0 = sctx->count[0] * 8; 218 219 csbcpb->cpb.sha512.message_bit_length_lo = count0; 220 221 len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1); 222 in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len, 223 max_sg_len); 224 225 if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) { 226 rc = -EINVAL; 227 goto out; 228 } 229 230 len = SHA512_DIGEST_SIZE; 231 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, 232 max_sg_len); 233 234 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 235 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 236 237 if (!nx_ctx->op.outlen) { 238 rc = -EINVAL; 239 goto out; 240 } 241 242 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 243 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP); 244 if (rc) 245 goto out; 246 247 atomic_inc(&(nx_ctx->stats->sha512_ops)); 248 atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes)); 249 250 memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE); 251 out: 252 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 253 return rc; 254 } 255 256 static int nx_sha512_export(struct shash_desc *desc, void *out) 257 { 258 struct sha512_state *sctx = shash_desc_ctx(desc); 259 260 memcpy(out, sctx, sizeof(*sctx)); 261 262 return 0; 263 } 264 265 static int nx_sha512_import(struct shash_desc *desc, const void *in) 266 { 267 struct sha512_state *sctx = shash_desc_ctx(desc); 268 269 memcpy(sctx, in, sizeof(*sctx)); 270 271 return 0; 272 } 273 274 struct shash_alg nx_shash_sha512_alg = { 275 .digestsize = SHA512_DIGEST_SIZE, 276 .init = nx_sha512_init, 277 .update = nx_sha512_update, 278 .final = nx_sha512_final, 279 .export = nx_sha512_export, 280 .import = nx_sha512_import, 281 .descsize = sizeof(struct sha512_state), 282 .statesize = sizeof(struct sha512_state), 283 .base = { 284 .cra_name = "sha512", 285 .cra_driver_name = "sha512-nx", 286 .cra_priority = 300, 287 .cra_flags = CRYPTO_ALG_TYPE_SHASH, 288 .cra_blocksize = SHA512_BLOCK_SIZE, 289 .cra_module = THIS_MODULE, 290 .cra_ctxsize = sizeof(struct nx_crypto_ctx), 291 .cra_init = nx_crypto_ctx_sha_init, 292 .cra_exit = nx_crypto_ctx_exit, 293 } 294 }; 295