1 /** 2 * SHA-256 routines supporting the Power 7+ Nest Accelerators driver 3 * 4 * Copyright (C) 2011-2012 International Business Machines Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 only. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * Author: Kent Yoder <yoder1@us.ibm.com> 20 */ 21 22 #include <crypto/internal/hash.h> 23 #include <crypto/sha.h> 24 #include <linux/module.h> 25 #include <asm/vio.h> 26 #include <asm/byteorder.h> 27 28 #include "nx_csbcpb.h" 29 #include "nx.h" 30 31 32 static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm) 33 { 34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm); 35 int err; 36 37 err = nx_crypto_ctx_sha_init(tfm); 38 if (err) 39 return err; 40 41 nx_ctx_init(nx_ctx, HCOP_FC_SHA); 42 43 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256]; 44 45 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256); 46 47 return 0; 48 } 49 50 static int nx_sha256_init(struct shash_desc *desc) { 51 struct sha256_state *sctx = shash_desc_ctx(desc); 52 53 memset(sctx, 0, sizeof *sctx); 54 55 sctx->state[0] = __cpu_to_be32(SHA256_H0); 56 sctx->state[1] = __cpu_to_be32(SHA256_H1); 57 sctx->state[2] = __cpu_to_be32(SHA256_H2); 58 sctx->state[3] = __cpu_to_be32(SHA256_H3); 59 sctx->state[4] = __cpu_to_be32(SHA256_H4); 60 sctx->state[5] = __cpu_to_be32(SHA256_H5); 61 sctx->state[6] = __cpu_to_be32(SHA256_H6); 62 sctx->state[7] = __cpu_to_be32(SHA256_H7); 63 sctx->count = 0; 64 65 return 0; 66 } 67 68 static int nx_sha256_update(struct shash_desc *desc, const u8 *data, 69 unsigned int len) 70 { 71 struct sha256_state *sctx = shash_desc_ctx(desc); 72 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 73 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 74 struct nx_sg *out_sg; 75 u64 to_process = 0, leftover, total; 76 unsigned long irq_flags; 77 int rc = 0; 78 int data_len; 79 u32 max_sg_len; 80 u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE); 81 82 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 83 84 /* 2 cases for total data len: 85 * 1: < SHA256_BLOCK_SIZE: copy into state, return 0 86 * 2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover 87 */ 88 total = (sctx->count % SHA256_BLOCK_SIZE) + len; 89 if (total < SHA256_BLOCK_SIZE) { 90 memcpy(sctx->buf + buf_len, data, len); 91 sctx->count += len; 92 goto out; 93 } 94 95 memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE); 96 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE; 97 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 98 99 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 100 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 101 max_sg_len = min_t(u64, max_sg_len, 102 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 103 104 data_len = SHA256_DIGEST_SIZE; 105 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state, 106 &data_len, max_sg_len); 107 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 108 109 if (data_len != SHA256_DIGEST_SIZE) { 110 rc = -EINVAL; 111 goto out; 112 } 113 114 do { 115 int used_sgs = 0; 116 struct nx_sg *in_sg = nx_ctx->in_sg; 117 118 if (buf_len) { 119 data_len = buf_len; 120 in_sg = nx_build_sg_list(in_sg, 121 (u8 *) sctx->buf, 122 &data_len, 123 max_sg_len); 124 125 if (data_len != buf_len) { 126 rc = -EINVAL; 127 goto out; 128 } 129 used_sgs = in_sg - nx_ctx->in_sg; 130 } 131 132 /* to_process: SHA256_BLOCK_SIZE aligned chunk to be 133 * processed in this iteration. This value is restricted 134 * by sg list limits and number of sgs we already used 135 * for leftover data. (see above) 136 * In ideal case, we could allow NX_PAGE_SIZE * max_sg_len, 137 * but because data may not be aligned, we need to account 138 * for that too. */ 139 to_process = min_t(u64, total, 140 (max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE); 141 to_process = to_process & ~(SHA256_BLOCK_SIZE - 1); 142 143 data_len = to_process - buf_len; 144 in_sg = nx_build_sg_list(in_sg, (u8 *) data, 145 &data_len, max_sg_len); 146 147 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 148 149 to_process = data_len + buf_len; 150 leftover = total - to_process; 151 152 /* 153 * we've hit the nx chip previously and we're updating 154 * again, so copy over the partial digest. 155 */ 156 memcpy(csbcpb->cpb.sha256.input_partial_digest, 157 csbcpb->cpb.sha256.message_digest, 158 SHA256_DIGEST_SIZE); 159 160 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) { 161 rc = -EINVAL; 162 goto out; 163 } 164 165 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); 166 if (rc) 167 goto out; 168 169 atomic_inc(&(nx_ctx->stats->sha256_ops)); 170 171 total -= to_process; 172 data += to_process - buf_len; 173 buf_len = 0; 174 175 } while (leftover >= SHA256_BLOCK_SIZE); 176 177 /* copy the leftover back into the state struct */ 178 if (leftover) 179 memcpy(sctx->buf, data, leftover); 180 181 sctx->count += len; 182 memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE); 183 out: 184 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 185 return rc; 186 } 187 188 static int nx_sha256_final(struct shash_desc *desc, u8 *out) 189 { 190 struct sha256_state *sctx = shash_desc_ctx(desc); 191 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); 192 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb; 193 struct nx_sg *in_sg, *out_sg; 194 unsigned long irq_flags; 195 u32 max_sg_len; 196 int rc = 0; 197 int len; 198 199 spin_lock_irqsave(&nx_ctx->lock, irq_flags); 200 201 max_sg_len = min_t(u64, nx_ctx->ap->sglen, 202 nx_driver.of.max_sg_len/sizeof(struct nx_sg)); 203 max_sg_len = min_t(u64, max_sg_len, 204 nx_ctx->ap->databytelen/NX_PAGE_SIZE); 205 206 /* final is represented by continuing the operation and indicating that 207 * this is not an intermediate operation */ 208 if (sctx->count >= SHA256_BLOCK_SIZE) { 209 /* we've hit the nx chip previously, now we're finalizing, 210 * so copy over the partial digest */ 211 memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE); 212 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 213 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION; 214 } else { 215 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE; 216 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION; 217 } 218 219 csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8); 220 221 len = sctx->count & (SHA256_BLOCK_SIZE - 1); 222 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf, 223 &len, max_sg_len); 224 225 if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) { 226 rc = -EINVAL; 227 goto out; 228 } 229 230 len = SHA256_DIGEST_SIZE; 231 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len); 232 233 if (len != SHA256_DIGEST_SIZE) { 234 rc = -EINVAL; 235 goto out; 236 } 237 238 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg); 239 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg); 240 if (!nx_ctx->op.outlen) { 241 rc = -EINVAL; 242 goto out; 243 } 244 245 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0); 246 if (rc) 247 goto out; 248 249 atomic_inc(&(nx_ctx->stats->sha256_ops)); 250 251 atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes)); 252 memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE); 253 out: 254 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags); 255 return rc; 256 } 257 258 static int nx_sha256_export(struct shash_desc *desc, void *out) 259 { 260 struct sha256_state *sctx = shash_desc_ctx(desc); 261 262 memcpy(out, sctx, sizeof(*sctx)); 263 264 return 0; 265 } 266 267 static int nx_sha256_import(struct shash_desc *desc, const void *in) 268 { 269 struct sha256_state *sctx = shash_desc_ctx(desc); 270 271 memcpy(sctx, in, sizeof(*sctx)); 272 273 return 0; 274 } 275 276 struct shash_alg nx_shash_sha256_alg = { 277 .digestsize = SHA256_DIGEST_SIZE, 278 .init = nx_sha256_init, 279 .update = nx_sha256_update, 280 .final = nx_sha256_final, 281 .export = nx_sha256_export, 282 .import = nx_sha256_import, 283 .descsize = sizeof(struct sha256_state), 284 .statesize = sizeof(struct sha256_state), 285 .base = { 286 .cra_name = "sha256", 287 .cra_driver_name = "sha256-nx", 288 .cra_priority = 300, 289 .cra_blocksize = SHA256_BLOCK_SIZE, 290 .cra_module = THIS_MODULE, 291 .cra_ctxsize = sizeof(struct nx_crypto_ctx), 292 .cra_init = nx_crypto_ctx_sha256_init, 293 .cra_exit = nx_crypto_ctx_exit, 294 } 295 }; 296