1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _N2_CORE_H 3 #define _N2_CORE_H 4 5 #ifndef __ASSEMBLY__ 6 7 struct ino_blob { 8 u64 intr; 9 u64 ino; 10 }; 11 12 struct spu_mdesc_info { 13 u64 cfg_handle; 14 struct ino_blob *ino_table; 15 int num_intrs; 16 }; 17 18 struct n2_crypto { 19 struct spu_mdesc_info cwq_info; 20 struct list_head cwq_list; 21 }; 22 23 struct n2_mau { 24 struct spu_mdesc_info mau_info; 25 struct list_head mau_list; 26 }; 27 28 #define CWQ_ENTRY_SIZE 64 29 #define CWQ_NUM_ENTRIES 64 30 31 #define MAU_ENTRY_SIZE 64 32 #define MAU_NUM_ENTRIES 64 33 34 struct cwq_initial_entry { 35 u64 control; 36 u64 src_addr; 37 u64 auth_key_addr; 38 u64 auth_iv_addr; 39 u64 final_auth_state_addr; 40 u64 enc_key_addr; 41 u64 enc_iv_addr; 42 u64 dest_addr; 43 }; 44 45 struct cwq_ext_entry { 46 u64 len; 47 u64 src_addr; 48 u64 resv1; 49 u64 resv2; 50 u64 resv3; 51 u64 resv4; 52 u64 resv5; 53 u64 resv6; 54 }; 55 56 struct cwq_final_entry { 57 u64 control; 58 u64 src_addr; 59 u64 resv1; 60 u64 resv2; 61 u64 resv3; 62 u64 resv4; 63 u64 resv5; 64 u64 resv6; 65 }; 66 67 #define CONTROL_LEN 0x000000000000ffffULL 68 #define CONTROL_LEN_SHIFT 0 69 #define CONTROL_HMAC_KEY_LEN 0x0000000000ff0000ULL 70 #define CONTROL_HMAC_KEY_LEN_SHIFT 16 71 #define CONTROL_ENC_TYPE 0x00000000ff000000ULL 72 #define CONTROL_ENC_TYPE_SHIFT 24 73 #define ENC_TYPE_ALG_RC4_STREAM 0x00ULL 74 #define ENC_TYPE_ALG_RC4_NOSTREAM 0x04ULL 75 #define ENC_TYPE_ALG_DES 0x08ULL 76 #define ENC_TYPE_ALG_3DES 0x0cULL 77 #define ENC_TYPE_ALG_AES128 0x10ULL 78 #define ENC_TYPE_ALG_AES192 0x14ULL 79 #define ENC_TYPE_ALG_AES256 0x18ULL 80 #define ENC_TYPE_ALG_RESERVED 0x1cULL 81 #define ENC_TYPE_ALG_MASK 0x1cULL 82 #define ENC_TYPE_CHAINING_ECB 0x00ULL 83 #define ENC_TYPE_CHAINING_CBC 0x01ULL 84 #define ENC_TYPE_CHAINING_CFB 0x02ULL 85 #define ENC_TYPE_CHAINING_COUNTER 0x03ULL 86 #define ENC_TYPE_CHAINING_MASK 0x03ULL 87 #define CONTROL_AUTH_TYPE 0x0000001f00000000ULL 88 #define CONTROL_AUTH_TYPE_SHIFT 32 89 #define AUTH_TYPE_RESERVED 0x00ULL 90 #define AUTH_TYPE_MD5 0x01ULL 91 #define AUTH_TYPE_SHA1 0x02ULL 92 #define AUTH_TYPE_SHA256 0x03ULL 93 #define AUTH_TYPE_CRC32 0x04ULL 94 #define AUTH_TYPE_HMAC_MD5 0x05ULL 95 #define AUTH_TYPE_HMAC_SHA1 0x06ULL 96 #define AUTH_TYPE_HMAC_SHA256 0x07ULL 97 #define AUTH_TYPE_TCP_CHECKSUM 0x08ULL 98 #define AUTH_TYPE_SSL_HMAC_MD5 0x09ULL 99 #define AUTH_TYPE_SSL_HMAC_SHA1 0x0aULL 100 #define AUTH_TYPE_SSL_HMAC_SHA256 0x0bULL 101 #define CONTROL_STRAND 0x000000e000000000ULL 102 #define CONTROL_STRAND_SHIFT 37 103 #define CONTROL_HASH_LEN 0x0000ff0000000000ULL 104 #define CONTROL_HASH_LEN_SHIFT 40 105 #define CONTROL_INTERRUPT 0x0001000000000000ULL 106 #define CONTROL_STORE_FINAL_AUTH_STATE 0x0002000000000000ULL 107 #define CONTROL_RESERVED 0x001c000000000000ULL 108 #define CONTROL_HV_DONE 0x0004000000000000ULL 109 #define CONTROL_HV_PROTOCOL_ERROR 0x0008000000000000ULL 110 #define CONTROL_HV_HARDWARE_ERROR 0x0010000000000000ULL 111 #define CONTROL_END_OF_BLOCK 0x0020000000000000ULL 112 #define CONTROL_START_OF_BLOCK 0x0040000000000000ULL 113 #define CONTROL_ENCRYPT 0x0080000000000000ULL 114 #define CONTROL_OPCODE 0xff00000000000000ULL 115 #define CONTROL_OPCODE_SHIFT 56 116 #define OPCODE_INPLACE_BIT 0x80ULL 117 #define OPCODE_SSL_KEYBLOCK 0x10ULL 118 #define OPCODE_COPY 0x20ULL 119 #define OPCODE_ENCRYPT 0x40ULL 120 #define OPCODE_AUTH_MAC 0x41ULL 121 122 #endif /* !(__ASSEMBLY__) */ 123 124 /* NCS v2.0 hypervisor interfaces */ 125 #define HV_NCS_QTYPE_MAU 0x01 126 #define HV_NCS_QTYPE_CWQ 0x02 127 128 /* ncs_qconf() 129 * TRAP: HV_FAST_TRAP 130 * FUNCTION: HV_FAST_NCS_QCONF 131 * ARG0: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) 132 * ARG1: Real address of queue, or handle for unconfigure 133 * ARG2: Number of entries in queue, zero for unconfigure 134 * RET0: status 135 * RET1: queue handle 136 * 137 * Configure a queue in the stream processing unit. 138 * 139 * The real address given as the base must be 64-byte 140 * aligned. 141 * 142 * The queue size can range from a minimum of 2 to a maximum 143 * of 64. The queue size must be a power of two. 144 * 145 * To unconfigure a queue, specify a length of zero and place 146 * the queue handle into ARG1. 147 * 148 * On configure success the hypervisor will set the FIRST, HEAD, 149 * and TAIL registers to the address of the first entry in the 150 * queue. The LAST register will be set to point to the last 151 * entry in the queue. 152 */ 153 #define HV_FAST_NCS_QCONF 0x111 154 155 /* ncs_qinfo() 156 * TRAP: HV_FAST_TRAP 157 * FUNCTION: HV_FAST_NCS_QINFO 158 * ARG0: Queue handle 159 * RET0: status 160 * RET1: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) 161 * RET2: Queue base address 162 * RET3: Number of entries 163 */ 164 #define HV_FAST_NCS_QINFO 0x112 165 166 /* ncs_gethead() 167 * TRAP: HV_FAST_TRAP 168 * FUNCTION: HV_FAST_NCS_GETHEAD 169 * ARG0: Queue handle 170 * RET0: status 171 * RET1: queue head offset 172 */ 173 #define HV_FAST_NCS_GETHEAD 0x113 174 175 /* ncs_gettail() 176 * TRAP: HV_FAST_TRAP 177 * FUNCTION: HV_FAST_NCS_GETTAIL 178 * ARG0: Queue handle 179 * RET0: status 180 * RET1: queue tail offset 181 */ 182 #define HV_FAST_NCS_GETTAIL 0x114 183 184 /* ncs_settail() 185 * TRAP: HV_FAST_TRAP 186 * FUNCTION: HV_FAST_NCS_SETTAIL 187 * ARG0: Queue handle 188 * ARG1: New tail offset 189 * RET0: status 190 */ 191 #define HV_FAST_NCS_SETTAIL 0x115 192 193 /* ncs_qhandle_to_devino() 194 * TRAP: HV_FAST_TRAP 195 * FUNCTION: HV_FAST_NCS_QHANDLE_TO_DEVINO 196 * ARG0: Queue handle 197 * RET0: status 198 * RET1: devino 199 */ 200 #define HV_FAST_NCS_QHANDLE_TO_DEVINO 0x116 201 202 /* ncs_sethead_marker() 203 * TRAP: HV_FAST_TRAP 204 * FUNCTION: HV_FAST_NCS_SETHEAD_MARKER 205 * ARG0: Queue handle 206 * ARG1: New head offset 207 * RET0: status 208 */ 209 #define HV_FAST_NCS_SETHEAD_MARKER 0x117 210 211 #ifndef __ASSEMBLY__ 212 extern unsigned long sun4v_ncs_qconf(unsigned long queue_type, 213 unsigned long queue_ra, 214 unsigned long num_entries, 215 unsigned long *qhandle); 216 extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle, 217 unsigned long *queue_type, 218 unsigned long *queue_ra, 219 unsigned long *num_entries); 220 extern unsigned long sun4v_ncs_gethead(unsigned long qhandle, 221 unsigned long *head); 222 extern unsigned long sun4v_ncs_gettail(unsigned long qhandle, 223 unsigned long *tail); 224 extern unsigned long sun4v_ncs_settail(unsigned long qhandle, 225 unsigned long tail); 226 extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle, 227 unsigned long *devino); 228 extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle, 229 unsigned long head); 230 #endif /* !(__ASSEMBLY__) */ 231 232 #endif /* _N2_CORE_H */ 233