xref: /openbmc/linux/drivers/crypto/mxs-dcp.c (revision f220d3eb)
1 /*
2  * Freescale i.MX23/i.MX28 Data Co-Processor driver
3  *
4  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5  *
6  * The code contained herein is licensed under the GNU General Public
7  * License. You may obtain a copy of the GNU General Public License
8  * Version 2 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/gpl-license.html
11  * http://www.gnu.org/copyleft/gpl.html
12  */
13 
14 #include <linux/dma-mapping.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/stmp_device.h>
23 
24 #include <crypto/aes.h>
25 #include <crypto/sha.h>
26 #include <crypto/internal/hash.h>
27 #include <crypto/internal/skcipher.h>
28 
29 #define DCP_MAX_CHANS	4
30 #define DCP_BUF_SZ	PAGE_SIZE
31 
32 #define DCP_ALIGNMENT	64
33 
34 /* DCP DMA descriptor. */
35 struct dcp_dma_desc {
36 	uint32_t	next_cmd_addr;
37 	uint32_t	control0;
38 	uint32_t	control1;
39 	uint32_t	source;
40 	uint32_t	destination;
41 	uint32_t	size;
42 	uint32_t	payload;
43 	uint32_t	status;
44 };
45 
46 /* Coherent aligned block for bounce buffering. */
47 struct dcp_coherent_block {
48 	uint8_t			aes_in_buf[DCP_BUF_SZ];
49 	uint8_t			aes_out_buf[DCP_BUF_SZ];
50 	uint8_t			sha_in_buf[DCP_BUF_SZ];
51 
52 	uint8_t			aes_key[2 * AES_KEYSIZE_128];
53 
54 	struct dcp_dma_desc	desc[DCP_MAX_CHANS];
55 };
56 
57 struct dcp {
58 	struct device			*dev;
59 	void __iomem			*base;
60 
61 	uint32_t			caps;
62 
63 	struct dcp_coherent_block	*coh;
64 
65 	struct completion		completion[DCP_MAX_CHANS];
66 	struct mutex			mutex[DCP_MAX_CHANS];
67 	struct task_struct		*thread[DCP_MAX_CHANS];
68 	struct crypto_queue		queue[DCP_MAX_CHANS];
69 };
70 
71 enum dcp_chan {
72 	DCP_CHAN_HASH_SHA	= 0,
73 	DCP_CHAN_CRYPTO		= 2,
74 };
75 
76 struct dcp_async_ctx {
77 	/* Common context */
78 	enum dcp_chan	chan;
79 	uint32_t	fill;
80 
81 	/* SHA Hash-specific context */
82 	struct mutex			mutex;
83 	uint32_t			alg;
84 	unsigned int			hot:1;
85 
86 	/* Crypto-specific context */
87 	struct crypto_skcipher		*fallback;
88 	unsigned int			key_len;
89 	uint8_t				key[AES_KEYSIZE_128];
90 };
91 
92 struct dcp_aes_req_ctx {
93 	unsigned int	enc:1;
94 	unsigned int	ecb:1;
95 };
96 
97 struct dcp_sha_req_ctx {
98 	unsigned int	init:1;
99 	unsigned int	fini:1;
100 };
101 
102 /*
103  * There can even be only one instance of the MXS DCP due to the
104  * design of Linux Crypto API.
105  */
106 static struct dcp *global_sdcp;
107 
108 /* DCP register layout. */
109 #define MXS_DCP_CTRL				0x00
110 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES	(1 << 23)
111 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING	(1 << 22)
112 
113 #define MXS_DCP_STAT				0x10
114 #define MXS_DCP_STAT_CLR			0x18
115 #define MXS_DCP_STAT_IRQ_MASK			0xf
116 
117 #define MXS_DCP_CHANNELCTRL			0x20
118 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK	0xff
119 
120 #define MXS_DCP_CAPABILITY1			0x40
121 #define MXS_DCP_CAPABILITY1_SHA256		(4 << 16)
122 #define MXS_DCP_CAPABILITY1_SHA1		(1 << 16)
123 #define MXS_DCP_CAPABILITY1_AES128		(1 << 0)
124 
125 #define MXS_DCP_CONTEXT				0x50
126 
127 #define MXS_DCP_CH_N_CMDPTR(n)			(0x100 + ((n) * 0x40))
128 
129 #define MXS_DCP_CH_N_SEMA(n)			(0x110 + ((n) * 0x40))
130 
131 #define MXS_DCP_CH_N_STAT(n)			(0x120 + ((n) * 0x40))
132 #define MXS_DCP_CH_N_STAT_CLR(n)		(0x128 + ((n) * 0x40))
133 
134 /* DMA descriptor bits. */
135 #define MXS_DCP_CONTROL0_HASH_TERM		(1 << 13)
136 #define MXS_DCP_CONTROL0_HASH_INIT		(1 << 12)
137 #define MXS_DCP_CONTROL0_PAYLOAD_KEY		(1 << 11)
138 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT		(1 << 8)
139 #define MXS_DCP_CONTROL0_CIPHER_INIT		(1 << 9)
140 #define MXS_DCP_CONTROL0_ENABLE_HASH		(1 << 6)
141 #define MXS_DCP_CONTROL0_ENABLE_CIPHER		(1 << 5)
142 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE		(1 << 1)
143 #define MXS_DCP_CONTROL0_INTERRUPT		(1 << 0)
144 
145 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256	(2 << 16)
146 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1	(0 << 16)
147 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC	(1 << 4)
148 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB	(0 << 4)
149 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128	(0 << 0)
150 
151 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
152 {
153 	struct dcp *sdcp = global_sdcp;
154 	const int chan = actx->chan;
155 	uint32_t stat;
156 	unsigned long ret;
157 	struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
158 
159 	dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
160 					      DMA_TO_DEVICE);
161 
162 	reinit_completion(&sdcp->completion[chan]);
163 
164 	/* Clear status register. */
165 	writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
166 
167 	/* Load the DMA descriptor. */
168 	writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
169 
170 	/* Increment the semaphore to start the DMA transfer. */
171 	writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
172 
173 	ret = wait_for_completion_timeout(&sdcp->completion[chan],
174 					  msecs_to_jiffies(1000));
175 	if (!ret) {
176 		dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
177 			chan, readl(sdcp->base + MXS_DCP_STAT));
178 		return -ETIMEDOUT;
179 	}
180 
181 	stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
182 	if (stat & 0xff) {
183 		dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
184 			chan, stat);
185 		return -EINVAL;
186 	}
187 
188 	dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
189 
190 	return 0;
191 }
192 
193 /*
194  * Encryption (AES128)
195  */
196 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
197 			   struct ablkcipher_request *req, int init)
198 {
199 	struct dcp *sdcp = global_sdcp;
200 	struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
201 	struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
202 	int ret;
203 
204 	dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
205 					     2 * AES_KEYSIZE_128,
206 					     DMA_TO_DEVICE);
207 	dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
208 					     DCP_BUF_SZ, DMA_TO_DEVICE);
209 	dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
210 					     DCP_BUF_SZ, DMA_FROM_DEVICE);
211 
212 	/* Fill in the DMA descriptor. */
213 	desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
214 		    MXS_DCP_CONTROL0_INTERRUPT |
215 		    MXS_DCP_CONTROL0_ENABLE_CIPHER;
216 
217 	/* Payload contains the key. */
218 	desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
219 
220 	if (rctx->enc)
221 		desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
222 	if (init)
223 		desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
224 
225 	desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
226 
227 	if (rctx->ecb)
228 		desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
229 	else
230 		desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
231 
232 	desc->next_cmd_addr = 0;
233 	desc->source = src_phys;
234 	desc->destination = dst_phys;
235 	desc->size = actx->fill;
236 	desc->payload = key_phys;
237 	desc->status = 0;
238 
239 	ret = mxs_dcp_start_dma(actx);
240 
241 	dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
242 			 DMA_TO_DEVICE);
243 	dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
244 	dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
245 
246 	return ret;
247 }
248 
249 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
250 {
251 	struct dcp *sdcp = global_sdcp;
252 
253 	struct ablkcipher_request *req = ablkcipher_request_cast(arq);
254 	struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
255 	struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
256 
257 	struct scatterlist *dst = req->dst;
258 	struct scatterlist *src = req->src;
259 	const int nents = sg_nents(req->src);
260 
261 	const int out_off = DCP_BUF_SZ;
262 	uint8_t *in_buf = sdcp->coh->aes_in_buf;
263 	uint8_t *out_buf = sdcp->coh->aes_out_buf;
264 
265 	uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
266 	uint32_t dst_off = 0;
267 
268 	uint8_t *key = sdcp->coh->aes_key;
269 
270 	int ret = 0;
271 	int split = 0;
272 	unsigned int i, len, clen, rem = 0;
273 	int init = 0;
274 
275 	actx->fill = 0;
276 
277 	/* Copy the key from the temporary location. */
278 	memcpy(key, actx->key, actx->key_len);
279 
280 	if (!rctx->ecb) {
281 		/* Copy the CBC IV just past the key. */
282 		memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
283 		/* CBC needs the INIT set. */
284 		init = 1;
285 	} else {
286 		memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
287 	}
288 
289 	for_each_sg(req->src, src, nents, i) {
290 		src_buf = sg_virt(src);
291 		len = sg_dma_len(src);
292 
293 		do {
294 			if (actx->fill + len > out_off)
295 				clen = out_off - actx->fill;
296 			else
297 				clen = len;
298 
299 			memcpy(in_buf + actx->fill, src_buf, clen);
300 			len -= clen;
301 			src_buf += clen;
302 			actx->fill += clen;
303 
304 			/*
305 			 * If we filled the buffer or this is the last SG,
306 			 * submit the buffer.
307 			 */
308 			if (actx->fill == out_off || sg_is_last(src)) {
309 				ret = mxs_dcp_run_aes(actx, req, init);
310 				if (ret)
311 					return ret;
312 				init = 0;
313 
314 				out_tmp = out_buf;
315 				while (dst && actx->fill) {
316 					if (!split) {
317 						dst_buf = sg_virt(dst);
318 						dst_off = 0;
319 					}
320 					rem = min(sg_dma_len(dst) - dst_off,
321 						  actx->fill);
322 
323 					memcpy(dst_buf + dst_off, out_tmp, rem);
324 					out_tmp += rem;
325 					dst_off += rem;
326 					actx->fill -= rem;
327 
328 					if (dst_off == sg_dma_len(dst)) {
329 						dst = sg_next(dst);
330 						split = 0;
331 					} else {
332 						split = 1;
333 					}
334 				}
335 			}
336 		} while (len);
337 	}
338 
339 	return ret;
340 }
341 
342 static int dcp_chan_thread_aes(void *data)
343 {
344 	struct dcp *sdcp = global_sdcp;
345 	const int chan = DCP_CHAN_CRYPTO;
346 
347 	struct crypto_async_request *backlog;
348 	struct crypto_async_request *arq;
349 
350 	int ret;
351 
352 	do {
353 		__set_current_state(TASK_INTERRUPTIBLE);
354 
355 		mutex_lock(&sdcp->mutex[chan]);
356 		backlog = crypto_get_backlog(&sdcp->queue[chan]);
357 		arq = crypto_dequeue_request(&sdcp->queue[chan]);
358 		mutex_unlock(&sdcp->mutex[chan]);
359 
360 		if (backlog)
361 			backlog->complete(backlog, -EINPROGRESS);
362 
363 		if (arq) {
364 			ret = mxs_dcp_aes_block_crypt(arq);
365 			arq->complete(arq, ret);
366 			continue;
367 		}
368 
369 		schedule();
370 	} while (!kthread_should_stop());
371 
372 	return 0;
373 }
374 
375 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
376 {
377 	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
378 	struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm);
379 	SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
380 	int ret;
381 
382 	skcipher_request_set_tfm(subreq, ctx->fallback);
383 	skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
384 	skcipher_request_set_crypt(subreq, req->src, req->dst,
385 				   req->nbytes, req->info);
386 
387 	if (enc)
388 		ret = crypto_skcipher_encrypt(subreq);
389 	else
390 		ret = crypto_skcipher_decrypt(subreq);
391 
392 	skcipher_request_zero(subreq);
393 
394 	return ret;
395 }
396 
397 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
398 {
399 	struct dcp *sdcp = global_sdcp;
400 	struct crypto_async_request *arq = &req->base;
401 	struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
402 	struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
403 	int ret;
404 
405 	if (unlikely(actx->key_len != AES_KEYSIZE_128))
406 		return mxs_dcp_block_fallback(req, enc);
407 
408 	rctx->enc = enc;
409 	rctx->ecb = ecb;
410 	actx->chan = DCP_CHAN_CRYPTO;
411 
412 	mutex_lock(&sdcp->mutex[actx->chan]);
413 	ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
414 	mutex_unlock(&sdcp->mutex[actx->chan]);
415 
416 	wake_up_process(sdcp->thread[actx->chan]);
417 
418 	return -EINPROGRESS;
419 }
420 
421 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
422 {
423 	return mxs_dcp_aes_enqueue(req, 0, 1);
424 }
425 
426 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
427 {
428 	return mxs_dcp_aes_enqueue(req, 1, 1);
429 }
430 
431 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
432 {
433 	return mxs_dcp_aes_enqueue(req, 0, 0);
434 }
435 
436 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
437 {
438 	return mxs_dcp_aes_enqueue(req, 1, 0);
439 }
440 
441 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
442 			      unsigned int len)
443 {
444 	struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
445 	unsigned int ret;
446 
447 	/*
448 	 * AES 128 is supposed by the hardware, store key into temporary
449 	 * buffer and exit. We must use the temporary buffer here, since
450 	 * there can still be an operation in progress.
451 	 */
452 	actx->key_len = len;
453 	if (len == AES_KEYSIZE_128) {
454 		memcpy(actx->key, key, len);
455 		return 0;
456 	}
457 
458 	/*
459 	 * If the requested AES key size is not supported by the hardware,
460 	 * but is supported by in-kernel software implementation, we use
461 	 * software fallback.
462 	 */
463 	crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
464 	crypto_skcipher_set_flags(actx->fallback,
465 				  tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
466 
467 	ret = crypto_skcipher_setkey(actx->fallback, key, len);
468 	if (!ret)
469 		return 0;
470 
471 	tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
472 	tfm->base.crt_flags |= crypto_skcipher_get_flags(actx->fallback) &
473 			       CRYPTO_TFM_RES_MASK;
474 
475 	return ret;
476 }
477 
478 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
479 {
480 	const char *name = crypto_tfm_alg_name(tfm);
481 	const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
482 	struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
483 	struct crypto_skcipher *blk;
484 
485 	blk = crypto_alloc_skcipher(name, 0, flags);
486 	if (IS_ERR(blk))
487 		return PTR_ERR(blk);
488 
489 	actx->fallback = blk;
490 	tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
491 	return 0;
492 }
493 
494 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
495 {
496 	struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
497 
498 	crypto_free_skcipher(actx->fallback);
499 }
500 
501 /*
502  * Hashing (SHA1/SHA256)
503  */
504 static int mxs_dcp_run_sha(struct ahash_request *req)
505 {
506 	struct dcp *sdcp = global_sdcp;
507 	int ret;
508 
509 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
510 	struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
511 	struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
512 	struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
513 
514 	struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
515 
516 	dma_addr_t digest_phys = 0;
517 	dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
518 					     DCP_BUF_SZ, DMA_TO_DEVICE);
519 
520 	/* Fill in the DMA descriptor. */
521 	desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
522 		    MXS_DCP_CONTROL0_INTERRUPT |
523 		    MXS_DCP_CONTROL0_ENABLE_HASH;
524 	if (rctx->init)
525 		desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
526 
527 	desc->control1 = actx->alg;
528 	desc->next_cmd_addr = 0;
529 	desc->source = buf_phys;
530 	desc->destination = 0;
531 	desc->size = actx->fill;
532 	desc->payload = 0;
533 	desc->status = 0;
534 
535 	/* Set HASH_TERM bit for last transfer block. */
536 	if (rctx->fini) {
537 		digest_phys = dma_map_single(sdcp->dev, req->result,
538 					     halg->digestsize, DMA_FROM_DEVICE);
539 		desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
540 		desc->payload = digest_phys;
541 	}
542 
543 	ret = mxs_dcp_start_dma(actx);
544 
545 	if (rctx->fini)
546 		dma_unmap_single(sdcp->dev, digest_phys, halg->digestsize,
547 				 DMA_FROM_DEVICE);
548 
549 	dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
550 
551 	return ret;
552 }
553 
554 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
555 {
556 	struct dcp *sdcp = global_sdcp;
557 
558 	struct ahash_request *req = ahash_request_cast(arq);
559 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
560 	struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
561 	struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
562 	struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
563 	const int nents = sg_nents(req->src);
564 
565 	uint8_t *in_buf = sdcp->coh->sha_in_buf;
566 
567 	uint8_t *src_buf;
568 
569 	struct scatterlist *src;
570 
571 	unsigned int i, len, clen;
572 	int ret;
573 
574 	int fin = rctx->fini;
575 	if (fin)
576 		rctx->fini = 0;
577 
578 	for_each_sg(req->src, src, nents, i) {
579 		src_buf = sg_virt(src);
580 		len = sg_dma_len(src);
581 
582 		do {
583 			if (actx->fill + len > DCP_BUF_SZ)
584 				clen = DCP_BUF_SZ - actx->fill;
585 			else
586 				clen = len;
587 
588 			memcpy(in_buf + actx->fill, src_buf, clen);
589 			len -= clen;
590 			src_buf += clen;
591 			actx->fill += clen;
592 
593 			/*
594 			 * If we filled the buffer and still have some
595 			 * more data, submit the buffer.
596 			 */
597 			if (len && actx->fill == DCP_BUF_SZ) {
598 				ret = mxs_dcp_run_sha(req);
599 				if (ret)
600 					return ret;
601 				actx->fill = 0;
602 				rctx->init = 0;
603 			}
604 		} while (len);
605 	}
606 
607 	if (fin) {
608 		rctx->fini = 1;
609 
610 		/* Submit whatever is left. */
611 		if (!req->result)
612 			return -EINVAL;
613 
614 		ret = mxs_dcp_run_sha(req);
615 		if (ret)
616 			return ret;
617 
618 		actx->fill = 0;
619 
620 		/* For some reason, the result is flipped. */
621 		for (i = 0; i < halg->digestsize / 2; i++) {
622 			swap(req->result[i],
623 			     req->result[halg->digestsize - i - 1]);
624 		}
625 	}
626 
627 	return 0;
628 }
629 
630 static int dcp_chan_thread_sha(void *data)
631 {
632 	struct dcp *sdcp = global_sdcp;
633 	const int chan = DCP_CHAN_HASH_SHA;
634 
635 	struct crypto_async_request *backlog;
636 	struct crypto_async_request *arq;
637 
638 	struct dcp_sha_req_ctx *rctx;
639 
640 	struct ahash_request *req;
641 	int ret, fini;
642 
643 	do {
644 		__set_current_state(TASK_INTERRUPTIBLE);
645 
646 		mutex_lock(&sdcp->mutex[chan]);
647 		backlog = crypto_get_backlog(&sdcp->queue[chan]);
648 		arq = crypto_dequeue_request(&sdcp->queue[chan]);
649 		mutex_unlock(&sdcp->mutex[chan]);
650 
651 		if (backlog)
652 			backlog->complete(backlog, -EINPROGRESS);
653 
654 		if (arq) {
655 			req = ahash_request_cast(arq);
656 			rctx = ahash_request_ctx(req);
657 
658 			ret = dcp_sha_req_to_buf(arq);
659 			fini = rctx->fini;
660 			arq->complete(arq, ret);
661 			if (!fini)
662 				continue;
663 		}
664 
665 		schedule();
666 	} while (!kthread_should_stop());
667 
668 	return 0;
669 }
670 
671 static int dcp_sha_init(struct ahash_request *req)
672 {
673 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
674 	struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
675 
676 	struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
677 
678 	/*
679 	 * Start hashing session. The code below only inits the
680 	 * hashing session context, nothing more.
681 	 */
682 	memset(actx, 0, sizeof(*actx));
683 
684 	if (strcmp(halg->base.cra_name, "sha1") == 0)
685 		actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
686 	else
687 		actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
688 
689 	actx->fill = 0;
690 	actx->hot = 0;
691 	actx->chan = DCP_CHAN_HASH_SHA;
692 
693 	mutex_init(&actx->mutex);
694 
695 	return 0;
696 }
697 
698 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
699 {
700 	struct dcp *sdcp = global_sdcp;
701 
702 	struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
703 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
704 	struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
705 
706 	int ret;
707 
708 	/*
709 	 * Ignore requests that have no data in them and are not
710 	 * the trailing requests in the stream of requests.
711 	 */
712 	if (!req->nbytes && !fini)
713 		return 0;
714 
715 	mutex_lock(&actx->mutex);
716 
717 	rctx->fini = fini;
718 
719 	if (!actx->hot) {
720 		actx->hot = 1;
721 		rctx->init = 1;
722 	}
723 
724 	mutex_lock(&sdcp->mutex[actx->chan]);
725 	ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
726 	mutex_unlock(&sdcp->mutex[actx->chan]);
727 
728 	wake_up_process(sdcp->thread[actx->chan]);
729 	mutex_unlock(&actx->mutex);
730 
731 	return -EINPROGRESS;
732 }
733 
734 static int dcp_sha_update(struct ahash_request *req)
735 {
736 	return dcp_sha_update_fx(req, 0);
737 }
738 
739 static int dcp_sha_final(struct ahash_request *req)
740 {
741 	ahash_request_set_crypt(req, NULL, req->result, 0);
742 	req->nbytes = 0;
743 	return dcp_sha_update_fx(req, 1);
744 }
745 
746 static int dcp_sha_finup(struct ahash_request *req)
747 {
748 	return dcp_sha_update_fx(req, 1);
749 }
750 
751 static int dcp_sha_digest(struct ahash_request *req)
752 {
753 	int ret;
754 
755 	ret = dcp_sha_init(req);
756 	if (ret)
757 		return ret;
758 
759 	return dcp_sha_finup(req);
760 }
761 
762 static int dcp_sha_noimport(struct ahash_request *req, const void *in)
763 {
764 	return -ENOSYS;
765 }
766 
767 static int dcp_sha_noexport(struct ahash_request *req, void *out)
768 {
769 	return -ENOSYS;
770 }
771 
772 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
773 {
774 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
775 				 sizeof(struct dcp_sha_req_ctx));
776 	return 0;
777 }
778 
779 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
780 {
781 }
782 
783 /* AES 128 ECB and AES 128 CBC */
784 static struct crypto_alg dcp_aes_algs[] = {
785 	{
786 		.cra_name		= "ecb(aes)",
787 		.cra_driver_name	= "ecb-aes-dcp",
788 		.cra_priority		= 400,
789 		.cra_alignmask		= 15,
790 		.cra_flags		= CRYPTO_ALG_TYPE_ABLKCIPHER |
791 					  CRYPTO_ALG_ASYNC |
792 					  CRYPTO_ALG_NEED_FALLBACK,
793 		.cra_init		= mxs_dcp_aes_fallback_init,
794 		.cra_exit		= mxs_dcp_aes_fallback_exit,
795 		.cra_blocksize		= AES_BLOCK_SIZE,
796 		.cra_ctxsize		= sizeof(struct dcp_async_ctx),
797 		.cra_type		= &crypto_ablkcipher_type,
798 		.cra_module		= THIS_MODULE,
799 		.cra_u	= {
800 			.ablkcipher = {
801 				.min_keysize	= AES_MIN_KEY_SIZE,
802 				.max_keysize	= AES_MAX_KEY_SIZE,
803 				.setkey		= mxs_dcp_aes_setkey,
804 				.encrypt	= mxs_dcp_aes_ecb_encrypt,
805 				.decrypt	= mxs_dcp_aes_ecb_decrypt
806 			},
807 		},
808 	}, {
809 		.cra_name		= "cbc(aes)",
810 		.cra_driver_name	= "cbc-aes-dcp",
811 		.cra_priority		= 400,
812 		.cra_alignmask		= 15,
813 		.cra_flags		= CRYPTO_ALG_TYPE_ABLKCIPHER |
814 					  CRYPTO_ALG_ASYNC |
815 					  CRYPTO_ALG_NEED_FALLBACK,
816 		.cra_init		= mxs_dcp_aes_fallback_init,
817 		.cra_exit		= mxs_dcp_aes_fallback_exit,
818 		.cra_blocksize		= AES_BLOCK_SIZE,
819 		.cra_ctxsize		= sizeof(struct dcp_async_ctx),
820 		.cra_type		= &crypto_ablkcipher_type,
821 		.cra_module		= THIS_MODULE,
822 		.cra_u = {
823 			.ablkcipher = {
824 				.min_keysize	= AES_MIN_KEY_SIZE,
825 				.max_keysize	= AES_MAX_KEY_SIZE,
826 				.setkey		= mxs_dcp_aes_setkey,
827 				.encrypt	= mxs_dcp_aes_cbc_encrypt,
828 				.decrypt	= mxs_dcp_aes_cbc_decrypt,
829 				.ivsize		= AES_BLOCK_SIZE,
830 			},
831 		},
832 	},
833 };
834 
835 /* SHA1 */
836 static struct ahash_alg dcp_sha1_alg = {
837 	.init	= dcp_sha_init,
838 	.update	= dcp_sha_update,
839 	.final	= dcp_sha_final,
840 	.finup	= dcp_sha_finup,
841 	.digest	= dcp_sha_digest,
842 	.import = dcp_sha_noimport,
843 	.export = dcp_sha_noexport,
844 	.halg	= {
845 		.digestsize	= SHA1_DIGEST_SIZE,
846 		.base		= {
847 			.cra_name		= "sha1",
848 			.cra_driver_name	= "sha1-dcp",
849 			.cra_priority		= 400,
850 			.cra_alignmask		= 63,
851 			.cra_flags		= CRYPTO_ALG_ASYNC,
852 			.cra_blocksize		= SHA1_BLOCK_SIZE,
853 			.cra_ctxsize		= sizeof(struct dcp_async_ctx),
854 			.cra_module		= THIS_MODULE,
855 			.cra_init		= dcp_sha_cra_init,
856 			.cra_exit		= dcp_sha_cra_exit,
857 		},
858 	},
859 };
860 
861 /* SHA256 */
862 static struct ahash_alg dcp_sha256_alg = {
863 	.init	= dcp_sha_init,
864 	.update	= dcp_sha_update,
865 	.final	= dcp_sha_final,
866 	.finup	= dcp_sha_finup,
867 	.digest	= dcp_sha_digest,
868 	.import = dcp_sha_noimport,
869 	.export = dcp_sha_noexport,
870 	.halg	= {
871 		.digestsize	= SHA256_DIGEST_SIZE,
872 		.base		= {
873 			.cra_name		= "sha256",
874 			.cra_driver_name	= "sha256-dcp",
875 			.cra_priority		= 400,
876 			.cra_alignmask		= 63,
877 			.cra_flags		= CRYPTO_ALG_ASYNC,
878 			.cra_blocksize		= SHA256_BLOCK_SIZE,
879 			.cra_ctxsize		= sizeof(struct dcp_async_ctx),
880 			.cra_module		= THIS_MODULE,
881 			.cra_init		= dcp_sha_cra_init,
882 			.cra_exit		= dcp_sha_cra_exit,
883 		},
884 	},
885 };
886 
887 static irqreturn_t mxs_dcp_irq(int irq, void *context)
888 {
889 	struct dcp *sdcp = context;
890 	uint32_t stat;
891 	int i;
892 
893 	stat = readl(sdcp->base + MXS_DCP_STAT);
894 	stat &= MXS_DCP_STAT_IRQ_MASK;
895 	if (!stat)
896 		return IRQ_NONE;
897 
898 	/* Clear the interrupts. */
899 	writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
900 
901 	/* Complete the DMA requests that finished. */
902 	for (i = 0; i < DCP_MAX_CHANS; i++)
903 		if (stat & (1 << i))
904 			complete(&sdcp->completion[i]);
905 
906 	return IRQ_HANDLED;
907 }
908 
909 static int mxs_dcp_probe(struct platform_device *pdev)
910 {
911 	struct device *dev = &pdev->dev;
912 	struct dcp *sdcp = NULL;
913 	int i, ret;
914 
915 	struct resource *iores;
916 	int dcp_vmi_irq, dcp_irq;
917 
918 	if (global_sdcp) {
919 		dev_err(dev, "Only one DCP instance allowed!\n");
920 		return -ENODEV;
921 	}
922 
923 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
924 	dcp_vmi_irq = platform_get_irq(pdev, 0);
925 	if (dcp_vmi_irq < 0) {
926 		dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_vmi_irq);
927 		return dcp_vmi_irq;
928 	}
929 
930 	dcp_irq = platform_get_irq(pdev, 1);
931 	if (dcp_irq < 0) {
932 		dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_irq);
933 		return dcp_irq;
934 	}
935 
936 	sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
937 	if (!sdcp)
938 		return -ENOMEM;
939 
940 	sdcp->dev = dev;
941 	sdcp->base = devm_ioremap_resource(dev, iores);
942 	if (IS_ERR(sdcp->base))
943 		return PTR_ERR(sdcp->base);
944 
945 
946 	ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
947 			       "dcp-vmi-irq", sdcp);
948 	if (ret) {
949 		dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
950 		return ret;
951 	}
952 
953 	ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
954 			       "dcp-irq", sdcp);
955 	if (ret) {
956 		dev_err(dev, "Failed to claim DCP IRQ!\n");
957 		return ret;
958 	}
959 
960 	/* Allocate coherent helper block. */
961 	sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
962 				   GFP_KERNEL);
963 	if (!sdcp->coh)
964 		return -ENOMEM;
965 
966 	/* Re-align the structure so it fits the DCP constraints. */
967 	sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
968 
969 	/* Restart the DCP block. */
970 	ret = stmp_reset_block(sdcp->base);
971 	if (ret)
972 		return ret;
973 
974 	/* Initialize control register. */
975 	writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
976 	       MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
977 	       sdcp->base + MXS_DCP_CTRL);
978 
979 	/* Enable all DCP DMA channels. */
980 	writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
981 	       sdcp->base + MXS_DCP_CHANNELCTRL);
982 
983 	/*
984 	 * We do not enable context switching. Give the context buffer a
985 	 * pointer to an illegal address so if context switching is
986 	 * inadvertantly enabled, the DCP will return an error instead of
987 	 * trashing good memory. The DCP DMA cannot access ROM, so any ROM
988 	 * address will do.
989 	 */
990 	writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
991 	for (i = 0; i < DCP_MAX_CHANS; i++)
992 		writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
993 	writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
994 
995 	global_sdcp = sdcp;
996 
997 	platform_set_drvdata(pdev, sdcp);
998 
999 	for (i = 0; i < DCP_MAX_CHANS; i++) {
1000 		mutex_init(&sdcp->mutex[i]);
1001 		init_completion(&sdcp->completion[i]);
1002 		crypto_init_queue(&sdcp->queue[i], 50);
1003 	}
1004 
1005 	/* Create the SHA and AES handler threads. */
1006 	sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1007 						      NULL, "mxs_dcp_chan/sha");
1008 	if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1009 		dev_err(dev, "Error starting SHA thread!\n");
1010 		return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1011 	}
1012 
1013 	sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1014 						    NULL, "mxs_dcp_chan/aes");
1015 	if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1016 		dev_err(dev, "Error starting SHA thread!\n");
1017 		ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1018 		goto err_destroy_sha_thread;
1019 	}
1020 
1021 	/* Register the various crypto algorithms. */
1022 	sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1023 
1024 	if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1025 		ret = crypto_register_algs(dcp_aes_algs,
1026 					   ARRAY_SIZE(dcp_aes_algs));
1027 		if (ret) {
1028 			/* Failed to register algorithm. */
1029 			dev_err(dev, "Failed to register AES crypto!\n");
1030 			goto err_destroy_aes_thread;
1031 		}
1032 	}
1033 
1034 	if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1035 		ret = crypto_register_ahash(&dcp_sha1_alg);
1036 		if (ret) {
1037 			dev_err(dev, "Failed to register %s hash!\n",
1038 				dcp_sha1_alg.halg.base.cra_name);
1039 			goto err_unregister_aes;
1040 		}
1041 	}
1042 
1043 	if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1044 		ret = crypto_register_ahash(&dcp_sha256_alg);
1045 		if (ret) {
1046 			dev_err(dev, "Failed to register %s hash!\n",
1047 				dcp_sha256_alg.halg.base.cra_name);
1048 			goto err_unregister_sha1;
1049 		}
1050 	}
1051 
1052 	return 0;
1053 
1054 err_unregister_sha1:
1055 	if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1056 		crypto_unregister_ahash(&dcp_sha1_alg);
1057 
1058 err_unregister_aes:
1059 	if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1060 		crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1061 
1062 err_destroy_aes_thread:
1063 	kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1064 
1065 err_destroy_sha_thread:
1066 	kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1067 	return ret;
1068 }
1069 
1070 static int mxs_dcp_remove(struct platform_device *pdev)
1071 {
1072 	struct dcp *sdcp = platform_get_drvdata(pdev);
1073 
1074 	if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1075 		crypto_unregister_ahash(&dcp_sha256_alg);
1076 
1077 	if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1078 		crypto_unregister_ahash(&dcp_sha1_alg);
1079 
1080 	if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1081 		crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1082 
1083 	kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1084 	kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1085 
1086 	platform_set_drvdata(pdev, NULL);
1087 
1088 	global_sdcp = NULL;
1089 
1090 	return 0;
1091 }
1092 
1093 static const struct of_device_id mxs_dcp_dt_ids[] = {
1094 	{ .compatible = "fsl,imx23-dcp", .data = NULL, },
1095 	{ .compatible = "fsl,imx28-dcp", .data = NULL, },
1096 	{ /* sentinel */ }
1097 };
1098 
1099 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1100 
1101 static struct platform_driver mxs_dcp_driver = {
1102 	.probe	= mxs_dcp_probe,
1103 	.remove	= mxs_dcp_remove,
1104 	.driver	= {
1105 		.name		= "mxs-dcp",
1106 		.of_match_table	= mxs_dcp_dt_ids,
1107 	},
1108 };
1109 
1110 module_platform_driver(mxs_dcp_driver);
1111 
1112 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1113 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1114 MODULE_LICENSE("GPL");
1115 MODULE_ALIAS("platform:mxs-dcp");
1116