119d8e8c7SSrujana Challa // SPDX-License-Identifier: GPL-2.0-only
219d8e8c7SSrujana Challa /* Copyright (C) 2020 Marvell. */
319d8e8c7SSrujana Challa
419d8e8c7SSrujana Challa #include "otx2_cpt_common.h"
519d8e8c7SSrujana Challa #include "otx2_cptvf.h"
619d8e8c7SSrujana Challa #include <rvu_reg.h>
719d8e8c7SSrujana Challa
otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev * cptvf,struct pci_dev * pdev)84cd8c315SSrujana Challa int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev)
94cd8c315SSrujana Challa {
104cd8c315SSrujana Challa struct otx2_mbox_dev *mdev;
114cd8c315SSrujana Challa struct otx2_mbox *otx2_mbox;
124cd8c315SSrujana Challa
134cd8c315SSrujana Challa cptvf->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
144cd8c315SSrujana Challa if (!cptvf->bbuf_base)
154cd8c315SSrujana Challa return -ENOMEM;
164cd8c315SSrujana Challa /*
174cd8c315SSrujana Challa * Overwrite mbox mbase to point to bounce buffer, so that PF/VF
184cd8c315SSrujana Challa * prepare all mbox messages in bounce buffer instead of directly
194cd8c315SSrujana Challa * in hw mbox memory.
204cd8c315SSrujana Challa */
214cd8c315SSrujana Challa otx2_mbox = &cptvf->pfvf_mbox;
224cd8c315SSrujana Challa mdev = &otx2_mbox->dev[0];
234cd8c315SSrujana Challa mdev->mbase = cptvf->bbuf_base;
244cd8c315SSrujana Challa
254cd8c315SSrujana Challa return 0;
264cd8c315SSrujana Challa }
274cd8c315SSrujana Challa
otx2_cpt_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)284cd8c315SSrujana Challa static void otx2_cpt_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
294cd8c315SSrujana Challa {
304cd8c315SSrujana Challa u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
314cd8c315SSrujana Challa void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
324cd8c315SSrujana Challa struct otx2_mbox_dev *mdev = &mbox->dev[devid];
334cd8c315SSrujana Challa struct mbox_hdr *hdr;
344cd8c315SSrujana Challa u64 msg_size;
354cd8c315SSrujana Challa
364cd8c315SSrujana Challa if (mdev->mbase == hw_mbase)
374cd8c315SSrujana Challa return;
384cd8c315SSrujana Challa
394cd8c315SSrujana Challa hdr = hw_mbase + mbox->rx_start;
404cd8c315SSrujana Challa msg_size = hdr->msg_size;
414cd8c315SSrujana Challa
424cd8c315SSrujana Challa if (msg_size > mbox->rx_size - msgs_offset)
434cd8c315SSrujana Challa msg_size = mbox->rx_size - msgs_offset;
444cd8c315SSrujana Challa
454cd8c315SSrujana Challa /* Copy mbox messages from mbox memory to bounce buffer */
464cd8c315SSrujana Challa memcpy(mdev->mbase + mbox->rx_start,
474cd8c315SSrujana Challa hw_mbase + mbox->rx_start, msg_size + msgs_offset);
484cd8c315SSrujana Challa }
494cd8c315SSrujana Challa
otx2_cptvf_pfvf_mbox_intr(int __always_unused irq,void * arg)5019d8e8c7SSrujana Challa irqreturn_t otx2_cptvf_pfvf_mbox_intr(int __always_unused irq, void *arg)
5119d8e8c7SSrujana Challa {
5219d8e8c7SSrujana Challa struct otx2_cptvf_dev *cptvf = arg;
5319d8e8c7SSrujana Challa u64 intr;
5419d8e8c7SSrujana Challa
5519d8e8c7SSrujana Challa /* Read the interrupt bits */
5619d8e8c7SSrujana Challa intr = otx2_cpt_read64(cptvf->reg_base, BLKADDR_RVUM, 0,
5719d8e8c7SSrujana Challa OTX2_RVU_VF_INT);
5819d8e8c7SSrujana Challa
5919d8e8c7SSrujana Challa if (intr & 0x1ULL) {
6019d8e8c7SSrujana Challa /* Schedule work queue function to process the MBOX request */
6119d8e8c7SSrujana Challa queue_work(cptvf->pfvf_mbox_wq, &cptvf->pfvf_mbox_work);
6219d8e8c7SSrujana Challa /* Clear and ack the interrupt */
6319d8e8c7SSrujana Challa otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
6419d8e8c7SSrujana Challa OTX2_RVU_VF_INT, 0x1ULL);
6519d8e8c7SSrujana Challa }
6619d8e8c7SSrujana Challa return IRQ_HANDLED;
6719d8e8c7SSrujana Challa }
6819d8e8c7SSrujana Challa
process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev * cptvf,struct mbox_msghdr * msg)6919d8e8c7SSrujana Challa static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,
7019d8e8c7SSrujana Challa struct mbox_msghdr *msg)
7119d8e8c7SSrujana Challa {
7219d8e8c7SSrujana Challa struct otx2_cptlfs_info *lfs = &cptvf->lfs;
738ec8015aSSrujana Challa struct otx2_cpt_kvf_limits_rsp *rsp_limits;
748ec8015aSSrujana Challa struct otx2_cpt_egrp_num_rsp *rsp_grp;
7519d8e8c7SSrujana Challa struct cpt_rd_wr_reg_msg *rsp_reg;
7619d8e8c7SSrujana Challa struct msix_offset_rsp *rsp_msix;
7719d8e8c7SSrujana Challa int i;
7819d8e8c7SSrujana Challa
7919d8e8c7SSrujana Challa if (msg->id >= MBOX_MSG_MAX) {
8019d8e8c7SSrujana Challa dev_err(&cptvf->pdev->dev,
8119d8e8c7SSrujana Challa "MBOX msg with unknown ID %d\n", msg->id);
8219d8e8c7SSrujana Challa return;
8319d8e8c7SSrujana Challa }
8419d8e8c7SSrujana Challa if (msg->sig != OTX2_MBOX_RSP_SIG) {
8519d8e8c7SSrujana Challa dev_err(&cptvf->pdev->dev,
8619d8e8c7SSrujana Challa "MBOX msg with wrong signature %x, ID %d\n",
8719d8e8c7SSrujana Challa msg->sig, msg->id);
8819d8e8c7SSrujana Challa return;
8919d8e8c7SSrujana Challa }
9019d8e8c7SSrujana Challa switch (msg->id) {
9119d8e8c7SSrujana Challa case MBOX_MSG_READY:
9219d8e8c7SSrujana Challa cptvf->vf_id = ((msg->pcifunc >> RVU_PFVF_FUNC_SHIFT)
9319d8e8c7SSrujana Challa & RVU_PFVF_FUNC_MASK) - 1;
9419d8e8c7SSrujana Challa break;
9519d8e8c7SSrujana Challa case MBOX_MSG_ATTACH_RESOURCES:
9619d8e8c7SSrujana Challa /* Check if resources were successfully attached */
9719d8e8c7SSrujana Challa if (!msg->rc)
9819d8e8c7SSrujana Challa lfs->are_lfs_attached = 1;
9919d8e8c7SSrujana Challa break;
10019d8e8c7SSrujana Challa case MBOX_MSG_DETACH_RESOURCES:
10119d8e8c7SSrujana Challa /* Check if resources were successfully detached */
10219d8e8c7SSrujana Challa if (!msg->rc)
10319d8e8c7SSrujana Challa lfs->are_lfs_attached = 0;
10419d8e8c7SSrujana Challa break;
10519d8e8c7SSrujana Challa case MBOX_MSG_MSIX_OFFSET:
10619d8e8c7SSrujana Challa rsp_msix = (struct msix_offset_rsp *) msg;
10719d8e8c7SSrujana Challa for (i = 0; i < rsp_msix->cptlfs; i++)
10819d8e8c7SSrujana Challa lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i];
10919d8e8c7SSrujana Challa break;
11019d8e8c7SSrujana Challa case MBOX_MSG_CPT_RD_WR_REGISTER:
11119d8e8c7SSrujana Challa rsp_reg = (struct cpt_rd_wr_reg_msg *) msg;
11219d8e8c7SSrujana Challa if (msg->rc) {
11319d8e8c7SSrujana Challa dev_err(&cptvf->pdev->dev,
11419d8e8c7SSrujana Challa "Reg %llx rd/wr(%d) failed %d\n",
11519d8e8c7SSrujana Challa rsp_reg->reg_offset, rsp_reg->is_write,
11619d8e8c7SSrujana Challa msg->rc);
11719d8e8c7SSrujana Challa return;
11819d8e8c7SSrujana Challa }
11919d8e8c7SSrujana Challa if (!rsp_reg->is_write)
12019d8e8c7SSrujana Challa *rsp_reg->ret_val = rsp_reg->val;
12119d8e8c7SSrujana Challa break;
1228ec8015aSSrujana Challa case MBOX_MSG_GET_ENG_GRP_NUM:
1238ec8015aSSrujana Challa rsp_grp = (struct otx2_cpt_egrp_num_rsp *) msg;
1248ec8015aSSrujana Challa cptvf->lfs.kcrypto_eng_grp_num = rsp_grp->eng_grp_num;
1258ec8015aSSrujana Challa break;
1268ec8015aSSrujana Challa case MBOX_MSG_GET_KVF_LIMITS:
1278ec8015aSSrujana Challa rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;
1288ec8015aSSrujana Challa cptvf->lfs.kvf_limits = rsp_limits->kvf_limits;
1298ec8015aSSrujana Challa break;
13019d8e8c7SSrujana Challa default:
13119d8e8c7SSrujana Challa dev_err(&cptvf->pdev->dev, "Unsupported msg %d received.\n",
13219d8e8c7SSrujana Challa msg->id);
13319d8e8c7SSrujana Challa break;
13419d8e8c7SSrujana Challa }
13519d8e8c7SSrujana Challa }
13619d8e8c7SSrujana Challa
otx2_cptvf_pfvf_mbox_handler(struct work_struct * work)13719d8e8c7SSrujana Challa void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work)
13819d8e8c7SSrujana Challa {
13919d8e8c7SSrujana Challa struct otx2_cptvf_dev *cptvf;
14019d8e8c7SSrujana Challa struct otx2_mbox *pfvf_mbox;
14119d8e8c7SSrujana Challa struct otx2_mbox_dev *mdev;
14219d8e8c7SSrujana Challa struct mbox_hdr *rsp_hdr;
14319d8e8c7SSrujana Challa struct mbox_msghdr *msg;
14419d8e8c7SSrujana Challa int offset, i;
14519d8e8c7SSrujana Challa
14619d8e8c7SSrujana Challa /* sync with mbox memory region */
14719d8e8c7SSrujana Challa smp_rmb();
14819d8e8c7SSrujana Challa
14919d8e8c7SSrujana Challa cptvf = container_of(work, struct otx2_cptvf_dev, pfvf_mbox_work);
15019d8e8c7SSrujana Challa pfvf_mbox = &cptvf->pfvf_mbox;
1514cd8c315SSrujana Challa otx2_cpt_sync_mbox_bbuf(pfvf_mbox, 0);
15219d8e8c7SSrujana Challa mdev = &pfvf_mbox->dev[0];
15319d8e8c7SSrujana Challa rsp_hdr = (struct mbox_hdr *)(mdev->mbase + pfvf_mbox->rx_start);
15419d8e8c7SSrujana Challa if (rsp_hdr->num_msgs == 0)
15519d8e8c7SSrujana Challa return;
15619d8e8c7SSrujana Challa offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
15719d8e8c7SSrujana Challa
15819d8e8c7SSrujana Challa for (i = 0; i < rsp_hdr->num_msgs; i++) {
15919d8e8c7SSrujana Challa msg = (struct mbox_msghdr *)(mdev->mbase + pfvf_mbox->rx_start +
16019d8e8c7SSrujana Challa offset);
16119d8e8c7SSrujana Challa process_pfvf_mbox_mbox_msg(cptvf, msg);
16219d8e8c7SSrujana Challa offset = msg->next_msgoff;
16319d8e8c7SSrujana Challa mdev->msgs_acked++;
16419d8e8c7SSrujana Challa }
16519d8e8c7SSrujana Challa otx2_mbox_reset(pfvf_mbox, 0);
16619d8e8c7SSrujana Challa }
1678ec8015aSSrujana Challa
otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev * cptvf,int eng_type)1688ec8015aSSrujana Challa int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type)
1698ec8015aSSrujana Challa {
1708ec8015aSSrujana Challa struct otx2_mbox *mbox = &cptvf->pfvf_mbox;
1718ec8015aSSrujana Challa struct pci_dev *pdev = cptvf->pdev;
1728ec8015aSSrujana Challa struct otx2_cpt_egrp_num_msg *req;
1738ec8015aSSrujana Challa
1748ec8015aSSrujana Challa req = (struct otx2_cpt_egrp_num_msg *)
1758ec8015aSSrujana Challa otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
1768ec8015aSSrujana Challa sizeof(struct otx2_cpt_egrp_num_rsp));
1778ec8015aSSrujana Challa if (req == NULL) {
1788ec8015aSSrujana Challa dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
1798ec8015aSSrujana Challa return -EFAULT;
1808ec8015aSSrujana Challa }
1818ec8015aSSrujana Challa req->hdr.id = MBOX_MSG_GET_ENG_GRP_NUM;
1828ec8015aSSrujana Challa req->hdr.sig = OTX2_MBOX_REQ_SIG;
1838ec8015aSSrujana Challa req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);
1848ec8015aSSrujana Challa req->eng_type = eng_type;
1858ec8015aSSrujana Challa
1868ec8015aSSrujana Challa return otx2_cpt_send_mbox_msg(mbox, pdev);
1878ec8015aSSrujana Challa }
1888ec8015aSSrujana Challa
otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev * cptvf)1898ec8015aSSrujana Challa int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf)
1908ec8015aSSrujana Challa {
1918ec8015aSSrujana Challa struct otx2_mbox *mbox = &cptvf->pfvf_mbox;
1928ec8015aSSrujana Challa struct pci_dev *pdev = cptvf->pdev;
1938ec8015aSSrujana Challa struct mbox_msghdr *req;
1948ec8015aSSrujana Challa
1958ec8015aSSrujana Challa req = (struct mbox_msghdr *)
1968ec8015aSSrujana Challa otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
1978ec8015aSSrujana Challa sizeof(struct otx2_cpt_kvf_limits_rsp));
1988ec8015aSSrujana Challa if (req == NULL) {
1998ec8015aSSrujana Challa dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
2008ec8015aSSrujana Challa return -EFAULT;
2018ec8015aSSrujana Challa }
2028ec8015aSSrujana Challa req->id = MBOX_MSG_GET_KVF_LIMITS;
2038ec8015aSSrujana Challa req->sig = OTX2_MBOX_REQ_SIG;
2048ec8015aSSrujana Challa req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);
2058ec8015aSSrujana Challa
206*0cb3c9cdSye xingchen return otx2_cpt_send_mbox_msg(mbox, pdev);
2078ec8015aSSrujana Challa }
208