1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 5 #ifndef __OTX2_CPTPF_UCODE_H 6 #define __OTX2_CPTPF_UCODE_H 7 8 #include <linux/pci.h> 9 #include <linux/types.h> 10 #include <linux/module.h> 11 #include "otx2_cpt_hw_types.h" 12 #include "otx2_cpt_common.h" 13 14 /* 15 * On OcteonTX2 platform IPSec ucode can use both IE and SE engines therefore 16 * IE and SE engines can be attached to the same engine group. 17 */ 18 #define OTX2_CPT_MAX_ETYPES_PER_GRP 2 19 20 /* CPT ucode signature size */ 21 #define OTX2_CPT_UCODE_SIGN_LEN 256 22 23 /* Microcode version string length */ 24 #define OTX2_CPT_UCODE_VER_STR_SZ 44 25 26 /* Maximum number of supported engines/cores on OcteonTX2 platform */ 27 #define OTX2_CPT_MAX_ENGINES 128 28 29 #define OTX2_CPT_ENGS_BITMASK_LEN BITS_TO_LONGS(OTX2_CPT_MAX_ENGINES) 30 31 /* Microcode types */ 32 enum otx2_cpt_ucode_type { 33 OTX2_CPT_AE_UC_TYPE = 1, /* AE-MAIN */ 34 OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */ 35 OTX2_CPT_SE_UC_TYPE2 = 21,/* Fast Path IPSec + AirCrypto */ 36 OTX2_CPT_SE_UC_TYPE3 = 22,/* 37 * Hash + HMAC + FlexiCrypto + RNG + 38 * Full Feature IPSec + AirCrypto + Kasumi 39 */ 40 OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */ 41 OTX2_CPT_IE_UC_TYPE2 = 31, /* Fast Path IPSec */ 42 OTX2_CPT_IE_UC_TYPE3 = 32, /* 43 * Hash + HMAC + FlexiCrypto + RNG + 44 * Full Future IPSec 45 */ 46 }; 47 48 struct otx2_cpt_bitmap { 49 unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN]; 50 int size; 51 }; 52 53 struct otx2_cpt_engines { 54 int type; 55 int count; 56 }; 57 58 /* Microcode version number */ 59 struct otx2_cpt_ucode_ver_num { 60 u8 nn; 61 u8 xx; 62 u8 yy; 63 u8 zz; 64 }; 65 66 struct otx2_cpt_ucode_hdr { 67 struct otx2_cpt_ucode_ver_num ver_num; 68 u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ]; 69 __be32 code_length; 70 u32 padding[3]; 71 }; 72 73 struct otx2_cpt_ucode { 74 u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/* 75 * ucode version in readable 76 * format 77 */ 78 struct otx2_cpt_ucode_ver_num ver_num;/* ucode version number */ 79 char filename[OTX2_CPT_NAME_LENGTH];/* ucode filename */ 80 dma_addr_t dma; /* phys address of ucode image */ 81 void *va; /* virt address of ucode image */ 82 u32 size; /* ucode image size */ 83 int type; /* ucode image type SE, IE, AE or SE+IE */ 84 }; 85 86 struct otx2_cpt_uc_info_t { 87 struct list_head list; 88 struct otx2_cpt_ucode ucode;/* microcode information */ 89 const struct firmware *fw; 90 }; 91 92 /* Maximum and current number of engines available for all engine groups */ 93 struct otx2_cpt_engs_available { 94 int max_se_cnt; 95 int max_ie_cnt; 96 int max_ae_cnt; 97 int se_cnt; 98 int ie_cnt; 99 int ae_cnt; 100 }; 101 102 /* Engines reserved to an engine group */ 103 struct otx2_cpt_engs_rsvd { 104 int type; /* engine type */ 105 int count; /* number of engines attached */ 106 int offset; /* constant offset of engine type in the bitmap */ 107 unsigned long *bmap; /* attached engines bitmap */ 108 struct otx2_cpt_ucode *ucode; /* ucode used by these engines */ 109 }; 110 111 struct otx2_cpt_mirror_info { 112 int is_ena; /* 113 * is mirroring enabled, it is set only for engine 114 * group which mirrors another engine group 115 */ 116 int idx; /* 117 * index of engine group which is mirrored by this 118 * group, set only for engine group which mirrors 119 * another group 120 */ 121 int ref_count; /* 122 * number of times this engine group is mirrored by 123 * other groups, this is set only for engine group 124 * which is mirrored by other group(s) 125 */ 126 }; 127 128 struct otx2_cpt_eng_grp_info { 129 struct otx2_cpt_eng_grps *g; /* pointer to engine_groups structure */ 130 /* engines attached */ 131 struct otx2_cpt_engs_rsvd engs[OTX2_CPT_MAX_ETYPES_PER_GRP]; 132 /* ucodes information */ 133 struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP]; 134 /* engine group mirroring information */ 135 struct otx2_cpt_mirror_info mirror; 136 int idx; /* engine group index */ 137 bool is_enabled; /* 138 * is engine group enabled, engine group is enabled 139 * when it has engines attached and ucode loaded 140 */ 141 }; 142 143 struct otx2_cpt_eng_grps { 144 struct otx2_cpt_eng_grp_info grp[OTX2_CPT_MAX_ENGINE_GROUPS]; 145 struct otx2_cpt_engs_available avail; 146 void *obj; /* device specific data */ 147 int engs_num; /* total number of engines supported */ 148 u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */ 149 bool is_grps_created; /* Is the engine groups are already created */ 150 }; 151 struct otx2_cptpf_dev; 152 int otx2_cpt_init_eng_grps(struct pci_dev *pdev, 153 struct otx2_cpt_eng_grps *eng_grps); 154 void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev, 155 struct otx2_cpt_eng_grps *eng_grps); 156 int otx2_cpt_create_eng_grps(struct pci_dev *pdev, 157 struct otx2_cpt_eng_grps *eng_grps); 158 int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf); 159 int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type); 160 int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf); 161 162 #endif /* __OTX2_CPTPF_UCODE_H */ 163