1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 #ifndef __OTX2_CPTLF_H 5 #define __OTX2_CPTLF_H 6 7 #include <linux/soc/marvell/octeontx2/asm.h> 8 #include <mbox.h> 9 #include <rvu.h> 10 #include "otx2_cpt_common.h" 11 #include "otx2_cpt_reqmgr.h" 12 13 /* 14 * CPT instruction and pending queues user requested length in CPT_INST_S msgs 15 */ 16 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200 17 18 /* 19 * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S 20 * messages. 21 */ 22 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40) 23 24 /* 25 * CPT instruction and pending queues length in CPT_INST_S messages 26 */ 27 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 28 29 /* CPT instruction queue length in bytes */ 30 #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 31 OTX2_CPT_INST_SIZE) 32 33 /* CPT instruction group queue length in bytes */ 34 #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 35 36 /* CPT FC length in bytes */ 37 #define OTX2_CPT_Q_FC_LEN 128 38 39 /* CPT instruction queue alignment */ 40 #define OTX2_CPT_INST_Q_ALIGNMENT 128 41 42 /* Mask which selects all engine groups */ 43 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF 44 45 /* Maximum LFs supported in OcteonTX2 for CPT */ 46 #define OTX2_CPT_MAX_LFS_NUM 64 47 48 /* Queue priority */ 49 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 50 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0 51 52 enum otx2_cptlf_state { 53 OTX2_CPTLF_IN_RESET, 54 OTX2_CPTLF_STARTED, 55 }; 56 57 struct otx2_cpt_inst_queue { 58 u8 *vaddr; 59 u8 *real_vaddr; 60 dma_addr_t dma_addr; 61 dma_addr_t real_dma_addr; 62 u32 size; 63 }; 64 65 struct otx2_cptlfs_info; 66 struct otx2_cptlf_wqe { 67 struct tasklet_struct work; 68 struct otx2_cptlfs_info *lfs; 69 u8 lf_num; 70 }; 71 72 struct otx2_cptlf_info { 73 struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */ 74 void __iomem *lmtline; /* Address of LMTLINE */ 75 void __iomem *ioreg; /* LMTLINE send register */ 76 int msix_offset; /* MSI-X interrupts offset */ 77 cpumask_var_t affinity_mask; /* IRQs affinity mask */ 78 u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */ 79 u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */ 80 u8 slot; /* Slot number of this LF */ 81 82 struct otx2_cpt_inst_queue iqueue;/* Instruction queue */ 83 struct otx2_cpt_pending_queue pqueue; /* Pending queue */ 84 struct otx2_cptlf_wqe *wqe; /* Tasklet work info */ 85 }; 86 87 struct otx2_cptlfs_info { 88 /* Registers start address of VF/PF LFs are attached to */ 89 void __iomem *reg_base; 90 #define LMTLINE_SIZE 128 91 void __iomem *lmt_base; 92 struct pci_dev *pdev; /* Device LFs are attached to */ 93 struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM]; 94 struct otx2_mbox *mbox; 95 u8 are_lfs_attached; /* Whether CPT LFs are attached */ 96 u8 lfs_num; /* Number of CPT LFs */ 97 u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */ 98 u8 kvf_limits; /* Kernel crypto limits */ 99 atomic_t state; /* LF's state. started/reset */ 100 int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */ 101 }; 102 103 static inline void otx2_cpt_free_instruction_queues( 104 struct otx2_cptlfs_info *lfs) 105 { 106 struct otx2_cpt_inst_queue *iq; 107 int i; 108 109 for (i = 0; i < lfs->lfs_num; i++) { 110 iq = &lfs->lf[i].iqueue; 111 if (iq->real_vaddr) 112 dma_free_coherent(&lfs->pdev->dev, 113 iq->size, 114 iq->real_vaddr, 115 iq->real_dma_addr); 116 iq->real_vaddr = NULL; 117 iq->vaddr = NULL; 118 } 119 } 120 121 static inline int otx2_cpt_alloc_instruction_queues( 122 struct otx2_cptlfs_info *lfs) 123 { 124 struct otx2_cpt_inst_queue *iq; 125 int ret = 0, i; 126 127 if (!lfs->lfs_num) 128 return -EINVAL; 129 130 for (i = 0; i < lfs->lfs_num; i++) { 131 iq = &lfs->lf[i].iqueue; 132 iq->size = OTX2_CPT_INST_QLEN_BYTES + 133 OTX2_CPT_Q_FC_LEN + 134 OTX2_CPT_INST_GRP_QLEN_BYTES + 135 OTX2_CPT_INST_Q_ALIGNMENT; 136 iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size, 137 &iq->real_dma_addr, GFP_KERNEL); 138 if (!iq->real_vaddr) { 139 ret = -ENOMEM; 140 goto error; 141 } 142 iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES; 143 iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES; 144 145 /* Align pointers */ 146 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT); 147 iq->dma_addr = PTR_ALIGN(iq->dma_addr, 148 OTX2_CPT_INST_Q_ALIGNMENT); 149 } 150 return 0; 151 152 error: 153 otx2_cpt_free_instruction_queues(lfs); 154 return ret; 155 } 156 157 static inline void otx2_cptlf_set_iqueues_base_addr( 158 struct otx2_cptlfs_info *lfs) 159 { 160 union otx2_cptx_lf_q_base lf_q_base; 161 int slot; 162 163 for (slot = 0; slot < lfs->lfs_num; slot++) { 164 lf_q_base.u = lfs->lf[slot].iqueue.dma_addr; 165 otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, 166 OTX2_CPT_LF_Q_BASE, lf_q_base.u); 167 } 168 } 169 170 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 171 { 172 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 173 174 lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 175 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 176 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 177 } 178 179 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs) 180 { 181 int slot; 182 183 for (slot = 0; slot < lfs->lfs_num; slot++) 184 otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]); 185 } 186 187 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 188 { 189 union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 }; 190 union otx2_cptx_lf_inprog lf_inprog; 191 int timeout = 20; 192 193 /* Disable instructions enqueuing */ 194 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 195 OTX2_CPT_LF_CTL, lf_ctl.u); 196 197 /* Wait for instruction queue to become empty */ 198 do { 199 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, 200 lf->slot, OTX2_CPT_LF_INPROG); 201 if (!lf_inprog.s.inflight) 202 break; 203 204 usleep_range(10000, 20000); 205 if (timeout-- < 0) { 206 dev_err(&lf->lfs->pdev->dev, 207 "Error LF %d is still busy.\n", lf->slot); 208 break; 209 } 210 211 } while (1); 212 213 /* 214 * Disable executions in the LF's queue, 215 * the queue should be empty at this point 216 */ 217 lf_inprog.s.eena = 0x0; 218 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 219 OTX2_CPT_LF_INPROG, lf_inprog.u); 220 } 221 222 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 223 { 224 int slot; 225 226 for (slot = 0; slot < lfs->lfs_num; slot++) 227 otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]); 228 } 229 230 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf, 231 bool enable) 232 { 233 union otx2_cptx_lf_ctl lf_ctl; 234 235 lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 236 OTX2_CPT_LF_CTL); 237 238 /* Set iqueue's enqueuing */ 239 lf_ctl.s.ena = enable ? 0x1 : 0x0; 240 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 241 OTX2_CPT_LF_CTL, lf_ctl.u); 242 } 243 244 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf) 245 { 246 otx2_cptlf_set_iqueue_enq(lf, true); 247 } 248 249 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 250 bool enable) 251 { 252 union otx2_cptx_lf_inprog lf_inprog; 253 254 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 255 OTX2_CPT_LF_INPROG); 256 257 /* Set iqueue's execution */ 258 lf_inprog.s.eena = enable ? 0x1 : 0x0; 259 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 260 OTX2_CPT_LF_INPROG, lf_inprog.u); 261 } 262 263 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf) 264 { 265 otx2_cptlf_set_iqueue_exec(lf, true); 266 } 267 268 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf) 269 { 270 otx2_cptlf_set_iqueue_exec(lf, false); 271 } 272 273 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs) 274 { 275 int slot; 276 277 for (slot = 0; slot < lfs->lfs_num; slot++) { 278 otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]); 279 otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]); 280 } 281 } 282 283 static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst, 284 struct otx2_cpt_iq_command *iq_cmd, 285 u64 comp_baddr) 286 { 287 cptinst->u[0] = 0x0; 288 cptinst->s.doneint = true; 289 cptinst->s.res_addr = comp_baddr; 290 cptinst->u[2] = 0x0; 291 cptinst->u[3] = 0x0; 292 cptinst->s.ei0 = iq_cmd->cmd.u; 293 cptinst->s.ei1 = iq_cmd->dptr; 294 cptinst->s.ei2 = iq_cmd->rptr; 295 cptinst->s.ei3 = iq_cmd->cptr.u; 296 } 297 298 /* 299 * On OcteonTX2 platform the parameter insts_num is used as a count of 300 * instructions to be enqueued. The valid values for insts_num are: 301 * 1 - 1 CPT instruction will be enqueued during LMTST operation 302 * 2 - 2 CPT instructions will be enqueued during LMTST operation 303 */ 304 static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, 305 u32 insts_num, struct otx2_cptlf_info *lf) 306 { 307 void __iomem *lmtline = lf->lmtline; 308 long ret; 309 310 /* 311 * Make sure memory areas pointed in CPT_INST_S 312 * are flushed before the instruction is sent to CPT 313 */ 314 dma_wmb(); 315 316 do { 317 /* Copy CPT command to LMTLINE */ 318 memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE); 319 320 /* 321 * LDEOR initiates atomic transfer to I/O device 322 * The following will cause the LMTST to fail (the LDEOR 323 * returns zero): 324 * - No stores have been performed to the LMTLINE since it was 325 * last invalidated. 326 * - The bytes which have been stored to LMTLINE since it was 327 * last invalidated form a pattern that is non-contiguous, does 328 * not start at byte 0, or does not end on a 8-byte boundary. 329 * (i.e.comprises a formation of other than 1–16 8-byte 330 * words.) 331 * 332 * These rules are designed such that an operating system 333 * context switch or hypervisor guest switch need have no 334 * knowledge of the LMTST operations; the switch code does not 335 * need to store to LMTCANCEL. Also note as LMTLINE data cannot 336 * be read, there is no information leakage between processes. 337 */ 338 ret = otx2_lmt_flush(lf->ioreg); 339 340 } while (!ret); 341 } 342 343 static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs) 344 { 345 return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED; 346 } 347 348 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri, 349 int lfs_num); 350 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs); 351 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs); 352 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs); 353 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs); 354 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs); 355 356 #endif /* __OTX2_CPTLF_H */ 357