1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 #ifndef __OTX2_CPTLF_H 5 #define __OTX2_CPTLF_H 6 7 #include <linux/soc/marvell/octeontx2/asm.h> 8 #include <mbox.h> 9 #include <rvu.h> 10 #include "otx2_cpt_common.h" 11 #include "otx2_cpt_reqmgr.h" 12 13 /* 14 * CPT instruction and pending queues user requested length in CPT_INST_S msgs 15 */ 16 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200 17 18 /* 19 * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S 20 * messages. 21 */ 22 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40) 23 24 /* 25 * CPT instruction and pending queues length in CPT_INST_S messages 26 */ 27 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 28 29 /* CPT instruction queue length in bytes */ 30 #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 31 OTX2_CPT_INST_SIZE) 32 33 /* CPT instruction group queue length in bytes */ 34 #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 35 36 /* CPT FC length in bytes */ 37 #define OTX2_CPT_Q_FC_LEN 128 38 39 /* CPT instruction queue alignment */ 40 #define OTX2_CPT_INST_Q_ALIGNMENT 128 41 42 /* Mask which selects all engine groups */ 43 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF 44 45 /* Maximum LFs supported in OcteonTX2 for CPT */ 46 #define OTX2_CPT_MAX_LFS_NUM 64 47 48 /* Queue priority */ 49 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 50 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0 51 52 enum otx2_cptlf_state { 53 OTX2_CPTLF_IN_RESET, 54 OTX2_CPTLF_STARTED, 55 }; 56 57 struct otx2_cpt_inst_queue { 58 u8 *vaddr; 59 u8 *real_vaddr; 60 dma_addr_t dma_addr; 61 dma_addr_t real_dma_addr; 62 u32 size; 63 }; 64 65 struct otx2_cptlfs_info; 66 struct otx2_cptlf_wqe { 67 struct tasklet_struct work; 68 struct otx2_cptlfs_info *lfs; 69 u8 lf_num; 70 }; 71 72 struct otx2_cptlf_info { 73 struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */ 74 void __iomem *lmtline; /* Address of LMTLINE */ 75 void __iomem *ioreg; /* LMTLINE send register */ 76 int msix_offset; /* MSI-X interrupts offset */ 77 cpumask_var_t affinity_mask; /* IRQs affinity mask */ 78 u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */ 79 u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */ 80 u8 slot; /* Slot number of this LF */ 81 82 struct otx2_cpt_inst_queue iqueue;/* Instruction queue */ 83 struct otx2_cpt_pending_queue pqueue; /* Pending queue */ 84 struct otx2_cptlf_wqe *wqe; /* Tasklet work info */ 85 }; 86 87 struct otx2_cptlfs_info { 88 /* Registers start address of VF/PF LFs are attached to */ 89 void __iomem *reg_base; 90 struct pci_dev *pdev; /* Device LFs are attached to */ 91 struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM]; 92 struct otx2_mbox *mbox; 93 u8 are_lfs_attached; /* Whether CPT LFs are attached */ 94 u8 lfs_num; /* Number of CPT LFs */ 95 u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */ 96 u8 kvf_limits; /* Kernel crypto limits */ 97 atomic_t state; /* LF's state. started/reset */ 98 int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */ 99 }; 100 101 static inline void otx2_cpt_free_instruction_queues( 102 struct otx2_cptlfs_info *lfs) 103 { 104 struct otx2_cpt_inst_queue *iq; 105 int i; 106 107 for (i = 0; i < lfs->lfs_num; i++) { 108 iq = &lfs->lf[i].iqueue; 109 if (iq->real_vaddr) 110 dma_free_coherent(&lfs->pdev->dev, 111 iq->size, 112 iq->real_vaddr, 113 iq->real_dma_addr); 114 iq->real_vaddr = NULL; 115 iq->vaddr = NULL; 116 } 117 } 118 119 static inline int otx2_cpt_alloc_instruction_queues( 120 struct otx2_cptlfs_info *lfs) 121 { 122 struct otx2_cpt_inst_queue *iq; 123 int ret = 0, i; 124 125 if (!lfs->lfs_num) 126 return -EINVAL; 127 128 for (i = 0; i < lfs->lfs_num; i++) { 129 iq = &lfs->lf[i].iqueue; 130 iq->size = OTX2_CPT_INST_QLEN_BYTES + 131 OTX2_CPT_Q_FC_LEN + 132 OTX2_CPT_INST_GRP_QLEN_BYTES + 133 OTX2_CPT_INST_Q_ALIGNMENT; 134 iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size, 135 &iq->real_dma_addr, GFP_KERNEL); 136 if (!iq->real_vaddr) { 137 ret = -ENOMEM; 138 goto error; 139 } 140 iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES; 141 iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES; 142 143 /* Align pointers */ 144 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT); 145 iq->dma_addr = PTR_ALIGN(iq->dma_addr, 146 OTX2_CPT_INST_Q_ALIGNMENT); 147 } 148 return 0; 149 150 error: 151 otx2_cpt_free_instruction_queues(lfs); 152 return ret; 153 } 154 155 static inline void otx2_cptlf_set_iqueues_base_addr( 156 struct otx2_cptlfs_info *lfs) 157 { 158 union otx2_cptx_lf_q_base lf_q_base; 159 int slot; 160 161 for (slot = 0; slot < lfs->lfs_num; slot++) { 162 lf_q_base.u = lfs->lf[slot].iqueue.dma_addr; 163 otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, 164 OTX2_CPT_LF_Q_BASE, lf_q_base.u); 165 } 166 } 167 168 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 169 { 170 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 171 172 lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 173 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 174 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 175 } 176 177 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs) 178 { 179 int slot; 180 181 for (slot = 0; slot < lfs->lfs_num; slot++) 182 otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]); 183 } 184 185 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 186 { 187 union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 }; 188 union otx2_cptx_lf_inprog lf_inprog; 189 int timeout = 20; 190 191 /* Disable instructions enqueuing */ 192 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 193 OTX2_CPT_LF_CTL, lf_ctl.u); 194 195 /* Wait for instruction queue to become empty */ 196 do { 197 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, 198 lf->slot, OTX2_CPT_LF_INPROG); 199 if (!lf_inprog.s.inflight) 200 break; 201 202 usleep_range(10000, 20000); 203 if (timeout-- < 0) { 204 dev_err(&lf->lfs->pdev->dev, 205 "Error LF %d is still busy.\n", lf->slot); 206 break; 207 } 208 209 } while (1); 210 211 /* 212 * Disable executions in the LF's queue, 213 * the queue should be empty at this point 214 */ 215 lf_inprog.s.eena = 0x0; 216 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 217 OTX2_CPT_LF_INPROG, lf_inprog.u); 218 } 219 220 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 221 { 222 int slot; 223 224 for (slot = 0; slot < lfs->lfs_num; slot++) 225 otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]); 226 } 227 228 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf, 229 bool enable) 230 { 231 union otx2_cptx_lf_ctl lf_ctl; 232 233 lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 234 OTX2_CPT_LF_CTL); 235 236 /* Set iqueue's enqueuing */ 237 lf_ctl.s.ena = enable ? 0x1 : 0x0; 238 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 239 OTX2_CPT_LF_CTL, lf_ctl.u); 240 } 241 242 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf) 243 { 244 otx2_cptlf_set_iqueue_enq(lf, true); 245 } 246 247 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 248 bool enable) 249 { 250 union otx2_cptx_lf_inprog lf_inprog; 251 252 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 253 OTX2_CPT_LF_INPROG); 254 255 /* Set iqueue's execution */ 256 lf_inprog.s.eena = enable ? 0x1 : 0x0; 257 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 258 OTX2_CPT_LF_INPROG, lf_inprog.u); 259 } 260 261 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf) 262 { 263 otx2_cptlf_set_iqueue_exec(lf, true); 264 } 265 266 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf) 267 { 268 otx2_cptlf_set_iqueue_exec(lf, false); 269 } 270 271 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs) 272 { 273 int slot; 274 275 for (slot = 0; slot < lfs->lfs_num; slot++) { 276 otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]); 277 otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]); 278 } 279 } 280 281 static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst, 282 struct otx2_cpt_iq_command *iq_cmd, 283 u64 comp_baddr) 284 { 285 cptinst->u[0] = 0x0; 286 cptinst->s.doneint = true; 287 cptinst->s.res_addr = comp_baddr; 288 cptinst->u[2] = 0x0; 289 cptinst->u[3] = 0x0; 290 cptinst->s.ei0 = iq_cmd->cmd.u; 291 cptinst->s.ei1 = iq_cmd->dptr; 292 cptinst->s.ei2 = iq_cmd->rptr; 293 cptinst->s.ei3 = iq_cmd->cptr.u; 294 } 295 296 /* 297 * On OcteonTX2 platform the parameter insts_num is used as a count of 298 * instructions to be enqueued. The valid values for insts_num are: 299 * 1 - 1 CPT instruction will be enqueued during LMTST operation 300 * 2 - 2 CPT instructions will be enqueued during LMTST operation 301 */ 302 static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, 303 u32 insts_num, struct otx2_cptlf_info *lf) 304 { 305 void __iomem *lmtline = lf->lmtline; 306 long ret; 307 308 /* 309 * Make sure memory areas pointed in CPT_INST_S 310 * are flushed before the instruction is sent to CPT 311 */ 312 dma_wmb(); 313 314 do { 315 /* Copy CPT command to LMTLINE */ 316 memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE); 317 318 /* 319 * LDEOR initiates atomic transfer to I/O device 320 * The following will cause the LMTST to fail (the LDEOR 321 * returns zero): 322 * - No stores have been performed to the LMTLINE since it was 323 * last invalidated. 324 * - The bytes which have been stored to LMTLINE since it was 325 * last invalidated form a pattern that is non-contiguous, does 326 * not start at byte 0, or does not end on a 8-byte boundary. 327 * (i.e.comprises a formation of other than 1–16 8-byte 328 * words.) 329 * 330 * These rules are designed such that an operating system 331 * context switch or hypervisor guest switch need have no 332 * knowledge of the LMTST operations; the switch code does not 333 * need to store to LMTCANCEL. Also note as LMTLINE data cannot 334 * be read, there is no information leakage between processes. 335 */ 336 ret = otx2_lmt_flush(lf->ioreg); 337 338 } while (!ret); 339 } 340 341 static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs) 342 { 343 return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED; 344 } 345 346 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri, 347 int lfs_num); 348 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs); 349 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs); 350 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs); 351 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs); 352 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs); 353 354 #endif /* __OTX2_CPTLF_H */ 355