1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 #ifndef __OTX2_CPTLF_H 5 #define __OTX2_CPTLF_H 6 7 #include <linux/soc/marvell/octeontx2/asm.h> 8 #include <mbox.h> 9 #include <rvu.h> 10 #include "otx2_cpt_common.h" 11 #include "otx2_cpt_reqmgr.h" 12 13 /* 14 * CPT instruction and pending queues user requested length in CPT_INST_S msgs 15 */ 16 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200 17 18 /* 19 * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S 20 * messages. 21 */ 22 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40) 23 24 /* 25 * CPT instruction and pending queues length in CPT_INST_S messages 26 */ 27 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 28 29 /* CPT instruction queue length in bytes */ 30 #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 31 OTX2_CPT_INST_SIZE) 32 33 /* CPT instruction group queue length in bytes */ 34 #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 35 36 /* CPT FC length in bytes */ 37 #define OTX2_CPT_Q_FC_LEN 128 38 39 /* CPT instruction queue alignment */ 40 #define OTX2_CPT_INST_Q_ALIGNMENT 128 41 42 /* Mask which selects all engine groups */ 43 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF 44 45 /* Maximum LFs supported in OcteonTX2 for CPT */ 46 #define OTX2_CPT_MAX_LFS_NUM 64 47 48 /* Queue priority */ 49 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 50 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0 51 52 enum otx2_cptlf_state { 53 OTX2_CPTLF_IN_RESET, 54 OTX2_CPTLF_STARTED, 55 }; 56 57 struct otx2_cpt_inst_queue { 58 u8 *vaddr; 59 u8 *real_vaddr; 60 dma_addr_t dma_addr; 61 dma_addr_t real_dma_addr; 62 u32 size; 63 }; 64 65 struct otx2_cptlfs_info; 66 struct otx2_cptlf_wqe { 67 struct tasklet_struct work; 68 struct otx2_cptlfs_info *lfs; 69 u8 lf_num; 70 }; 71 72 struct otx2_cptlf_info { 73 struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */ 74 void __iomem *lmtline; /* Address of LMTLINE */ 75 void __iomem *ioreg; /* LMTLINE send register */ 76 int msix_offset; /* MSI-X interrupts offset */ 77 cpumask_var_t affinity_mask; /* IRQs affinity mask */ 78 u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */ 79 u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */ 80 u8 slot; /* Slot number of this LF */ 81 82 struct otx2_cpt_inst_queue iqueue;/* Instruction queue */ 83 struct otx2_cpt_pending_queue pqueue; /* Pending queue */ 84 struct otx2_cptlf_wqe *wqe; /* Tasklet work info */ 85 }; 86 87 struct otx2_cptlfs_info { 88 /* Registers start address of VF/PF LFs are attached to */ 89 void __iomem *reg_base; 90 struct pci_dev *pdev; /* Device LFs are attached to */ 91 struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM]; 92 struct otx2_mbox *mbox; 93 u8 are_lfs_attached; /* Whether CPT LFs are attached */ 94 u8 lfs_num; /* Number of CPT LFs */ 95 u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */ 96 u8 kvf_limits; /* Kernel crypto limits */ 97 atomic_t state; /* LF's state. started/reset */ 98 }; 99 100 static inline void otx2_cpt_free_instruction_queues( 101 struct otx2_cptlfs_info *lfs) 102 { 103 struct otx2_cpt_inst_queue *iq; 104 int i; 105 106 for (i = 0; i < lfs->lfs_num; i++) { 107 iq = &lfs->lf[i].iqueue; 108 if (iq->real_vaddr) 109 dma_free_coherent(&lfs->pdev->dev, 110 iq->size, 111 iq->real_vaddr, 112 iq->real_dma_addr); 113 iq->real_vaddr = NULL; 114 iq->vaddr = NULL; 115 } 116 } 117 118 static inline int otx2_cpt_alloc_instruction_queues( 119 struct otx2_cptlfs_info *lfs) 120 { 121 struct otx2_cpt_inst_queue *iq; 122 int ret = 0, i; 123 124 if (!lfs->lfs_num) 125 return -EINVAL; 126 127 for (i = 0; i < lfs->lfs_num; i++) { 128 iq = &lfs->lf[i].iqueue; 129 iq->size = OTX2_CPT_INST_QLEN_BYTES + 130 OTX2_CPT_Q_FC_LEN + 131 OTX2_CPT_INST_GRP_QLEN_BYTES + 132 OTX2_CPT_INST_Q_ALIGNMENT; 133 iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size, 134 &iq->real_dma_addr, GFP_KERNEL); 135 if (!iq->real_vaddr) { 136 ret = -ENOMEM; 137 goto error; 138 } 139 iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES; 140 iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES; 141 142 /* Align pointers */ 143 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT); 144 iq->dma_addr = PTR_ALIGN(iq->dma_addr, 145 OTX2_CPT_INST_Q_ALIGNMENT); 146 } 147 return 0; 148 149 error: 150 otx2_cpt_free_instruction_queues(lfs); 151 return ret; 152 } 153 154 static inline void otx2_cptlf_set_iqueues_base_addr( 155 struct otx2_cptlfs_info *lfs) 156 { 157 union otx2_cptx_lf_q_base lf_q_base; 158 int slot; 159 160 for (slot = 0; slot < lfs->lfs_num; slot++) { 161 lf_q_base.u = lfs->lf[slot].iqueue.dma_addr; 162 otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, 163 OTX2_CPT_LF_Q_BASE, lf_q_base.u); 164 } 165 } 166 167 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 168 { 169 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 170 171 lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 172 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 173 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 174 } 175 176 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs) 177 { 178 int slot; 179 180 for (slot = 0; slot < lfs->lfs_num; slot++) 181 otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]); 182 } 183 184 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 185 { 186 union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 }; 187 union otx2_cptx_lf_inprog lf_inprog; 188 int timeout = 20; 189 190 /* Disable instructions enqueuing */ 191 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 192 OTX2_CPT_LF_CTL, lf_ctl.u); 193 194 /* Wait for instruction queue to become empty */ 195 do { 196 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, 197 lf->slot, OTX2_CPT_LF_INPROG); 198 if (!lf_inprog.s.inflight) 199 break; 200 201 usleep_range(10000, 20000); 202 if (timeout-- < 0) { 203 dev_err(&lf->lfs->pdev->dev, 204 "Error LF %d is still busy.\n", lf->slot); 205 break; 206 } 207 208 } while (1); 209 210 /* 211 * Disable executions in the LF's queue, 212 * the queue should be empty at this point 213 */ 214 lf_inprog.s.eena = 0x0; 215 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 216 OTX2_CPT_LF_INPROG, lf_inprog.u); 217 } 218 219 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 220 { 221 int slot; 222 223 for (slot = 0; slot < lfs->lfs_num; slot++) 224 otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]); 225 } 226 227 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf, 228 bool enable) 229 { 230 union otx2_cptx_lf_ctl lf_ctl; 231 232 lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 233 OTX2_CPT_LF_CTL); 234 235 /* Set iqueue's enqueuing */ 236 lf_ctl.s.ena = enable ? 0x1 : 0x0; 237 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 238 OTX2_CPT_LF_CTL, lf_ctl.u); 239 } 240 241 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf) 242 { 243 otx2_cptlf_set_iqueue_enq(lf, true); 244 } 245 246 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 247 bool enable) 248 { 249 union otx2_cptx_lf_inprog lf_inprog; 250 251 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 252 OTX2_CPT_LF_INPROG); 253 254 /* Set iqueue's execution */ 255 lf_inprog.s.eena = enable ? 0x1 : 0x0; 256 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 257 OTX2_CPT_LF_INPROG, lf_inprog.u); 258 } 259 260 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf) 261 { 262 otx2_cptlf_set_iqueue_exec(lf, true); 263 } 264 265 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf) 266 { 267 otx2_cptlf_set_iqueue_exec(lf, false); 268 } 269 270 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs) 271 { 272 int slot; 273 274 for (slot = 0; slot < lfs->lfs_num; slot++) { 275 otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]); 276 otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]); 277 } 278 } 279 280 static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst, 281 struct otx2_cpt_iq_command *iq_cmd, 282 u64 comp_baddr) 283 { 284 cptinst->u[0] = 0x0; 285 cptinst->s.doneint = true; 286 cptinst->s.res_addr = comp_baddr; 287 cptinst->u[2] = 0x0; 288 cptinst->u[3] = 0x0; 289 cptinst->s.ei0 = iq_cmd->cmd.u; 290 cptinst->s.ei1 = iq_cmd->dptr; 291 cptinst->s.ei2 = iq_cmd->rptr; 292 cptinst->s.ei3 = iq_cmd->cptr.u; 293 } 294 295 /* 296 * On OcteonTX2 platform the parameter insts_num is used as a count of 297 * instructions to be enqueued. The valid values for insts_num are: 298 * 1 - 1 CPT instruction will be enqueued during LMTST operation 299 * 2 - 2 CPT instructions will be enqueued during LMTST operation 300 */ 301 static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, 302 u32 insts_num, struct otx2_cptlf_info *lf) 303 { 304 void __iomem *lmtline = lf->lmtline; 305 long ret; 306 307 /* 308 * Make sure memory areas pointed in CPT_INST_S 309 * are flushed before the instruction is sent to CPT 310 */ 311 dma_wmb(); 312 313 do { 314 /* Copy CPT command to LMTLINE */ 315 memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE); 316 317 /* 318 * LDEOR initiates atomic transfer to I/O device 319 * The following will cause the LMTST to fail (the LDEOR 320 * returns zero): 321 * - No stores have been performed to the LMTLINE since it was 322 * last invalidated. 323 * - The bytes which have been stored to LMTLINE since it was 324 * last invalidated form a pattern that is non-contiguous, does 325 * not start at byte 0, or does not end on a 8-byte boundary. 326 * (i.e.comprises a formation of other than 1–16 8-byte 327 * words.) 328 * 329 * These rules are designed such that an operating system 330 * context switch or hypervisor guest switch need have no 331 * knowledge of the LMTST operations; the switch code does not 332 * need to store to LMTCANCEL. Also note as LMTLINE data cannot 333 * be read, there is no information leakage between processes. 334 */ 335 ret = otx2_lmt_flush(lf->ioreg); 336 337 } while (!ret); 338 } 339 340 static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs) 341 { 342 return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED; 343 } 344 345 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri, 346 int lfs_num); 347 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs); 348 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs); 349 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs); 350 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs); 351 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs); 352 353 #endif /* __OTX2_CPTLF_H */ 354