1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 #ifndef __OTX2_CPTLF_H 5 #define __OTX2_CPTLF_H 6 7 #include <linux/soc/marvell/octeontx2/asm.h> 8 #include <mbox.h> 9 #include <rvu.h> 10 #include "otx2_cpt_common.h" 11 #include "otx2_cpt_reqmgr.h" 12 13 /* 14 * CPT instruction and pending queues user requested length in CPT_INST_S msgs 15 */ 16 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200 17 18 /* 19 * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S 20 * messages. 21 */ 22 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40) 23 24 /* 25 * CPT instruction and pending queues length in CPT_INST_S messages 26 */ 27 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 28 29 /* CPT instruction queue length in bytes */ 30 #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 31 OTX2_CPT_INST_SIZE) 32 33 /* CPT instruction group queue length in bytes */ 34 #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 35 36 /* CPT FC length in bytes */ 37 #define OTX2_CPT_Q_FC_LEN 128 38 39 /* CPT instruction queue alignment */ 40 #define OTX2_CPT_INST_Q_ALIGNMENT 128 41 42 /* Mask which selects all engine groups */ 43 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF 44 45 /* Maximum LFs supported in OcteonTX2 for CPT */ 46 #define OTX2_CPT_MAX_LFS_NUM 64 47 48 /* Queue priority */ 49 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 50 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0 51 52 enum otx2_cptlf_state { 53 OTX2_CPTLF_IN_RESET, 54 OTX2_CPTLF_STARTED, 55 }; 56 57 struct otx2_cpt_inst_queue { 58 u8 *vaddr; 59 u8 *real_vaddr; 60 dma_addr_t dma_addr; 61 dma_addr_t real_dma_addr; 62 u32 size; 63 }; 64 65 struct otx2_cptlfs_info; 66 struct otx2_cptlf_wqe { 67 struct tasklet_struct work; 68 struct otx2_cptlfs_info *lfs; 69 u8 lf_num; 70 }; 71 72 struct otx2_cptlf_info { 73 struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */ 74 void __iomem *lmtline; /* Address of LMTLINE */ 75 void __iomem *ioreg; /* LMTLINE send register */ 76 int msix_offset; /* MSI-X interrupts offset */ 77 cpumask_var_t affinity_mask; /* IRQs affinity mask */ 78 u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */ 79 u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */ 80 u8 slot; /* Slot number of this LF */ 81 82 struct otx2_cpt_inst_queue iqueue;/* Instruction queue */ 83 struct otx2_cptlf_wqe *wqe; /* Tasklet work info */ 84 }; 85 86 struct otx2_cptlfs_info { 87 /* Registers start address of VF/PF LFs are attached to */ 88 void __iomem *reg_base; 89 struct pci_dev *pdev; /* Device LFs are attached to */ 90 struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM]; 91 struct otx2_mbox *mbox; 92 u8 are_lfs_attached; /* Whether CPT LFs are attached */ 93 u8 lfs_num; /* Number of CPT LFs */ 94 atomic_t state; /* LF's state. started/reset */ 95 }; 96 97 static inline void otx2_cpt_free_instruction_queues( 98 struct otx2_cptlfs_info *lfs) 99 { 100 struct otx2_cpt_inst_queue *iq; 101 int i; 102 103 for (i = 0; i < lfs->lfs_num; i++) { 104 iq = &lfs->lf[i].iqueue; 105 if (iq->real_vaddr) 106 dma_free_coherent(&lfs->pdev->dev, 107 iq->size, 108 iq->real_vaddr, 109 iq->real_dma_addr); 110 iq->real_vaddr = NULL; 111 iq->vaddr = NULL; 112 } 113 } 114 115 static inline int otx2_cpt_alloc_instruction_queues( 116 struct otx2_cptlfs_info *lfs) 117 { 118 struct otx2_cpt_inst_queue *iq; 119 int ret = 0, i; 120 121 if (!lfs->lfs_num) 122 return -EINVAL; 123 124 for (i = 0; i < lfs->lfs_num; i++) { 125 iq = &lfs->lf[i].iqueue; 126 iq->size = OTX2_CPT_INST_QLEN_BYTES + 127 OTX2_CPT_Q_FC_LEN + 128 OTX2_CPT_INST_GRP_QLEN_BYTES + 129 OTX2_CPT_INST_Q_ALIGNMENT; 130 iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size, 131 &iq->real_dma_addr, GFP_KERNEL); 132 if (!iq->real_vaddr) { 133 ret = -ENOMEM; 134 goto error; 135 } 136 iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES; 137 iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES; 138 139 /* Align pointers */ 140 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT); 141 iq->dma_addr = PTR_ALIGN(iq->dma_addr, 142 OTX2_CPT_INST_Q_ALIGNMENT); 143 } 144 return 0; 145 146 error: 147 otx2_cpt_free_instruction_queues(lfs); 148 return ret; 149 } 150 151 static inline void otx2_cptlf_set_iqueues_base_addr( 152 struct otx2_cptlfs_info *lfs) 153 { 154 union otx2_cptx_lf_q_base lf_q_base; 155 int slot; 156 157 for (slot = 0; slot < lfs->lfs_num; slot++) { 158 lf_q_base.u = lfs->lf[slot].iqueue.dma_addr; 159 otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, 160 OTX2_CPT_LF_Q_BASE, lf_q_base.u); 161 } 162 } 163 164 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 165 { 166 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 167 168 lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 169 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 170 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 171 } 172 173 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs) 174 { 175 int slot; 176 177 for (slot = 0; slot < lfs->lfs_num; slot++) 178 otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]); 179 } 180 181 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 182 { 183 union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 }; 184 union otx2_cptx_lf_inprog lf_inprog; 185 int timeout = 20; 186 187 /* Disable instructions enqueuing */ 188 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 189 OTX2_CPT_LF_CTL, lf_ctl.u); 190 191 /* Wait for instruction queue to become empty */ 192 do { 193 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, 194 lf->slot, OTX2_CPT_LF_INPROG); 195 if (!lf_inprog.s.inflight) 196 break; 197 198 usleep_range(10000, 20000); 199 if (timeout-- < 0) { 200 dev_err(&lf->lfs->pdev->dev, 201 "Error LF %d is still busy.\n", lf->slot); 202 break; 203 } 204 205 } while (1); 206 207 /* 208 * Disable executions in the LF's queue, 209 * the queue should be empty at this point 210 */ 211 lf_inprog.s.eena = 0x0; 212 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 213 OTX2_CPT_LF_INPROG, lf_inprog.u); 214 } 215 216 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 217 { 218 int slot; 219 220 for (slot = 0; slot < lfs->lfs_num; slot++) 221 otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]); 222 } 223 224 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf, 225 bool enable) 226 { 227 union otx2_cptx_lf_ctl lf_ctl; 228 229 lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 230 OTX2_CPT_LF_CTL); 231 232 /* Set iqueue's enqueuing */ 233 lf_ctl.s.ena = enable ? 0x1 : 0x0; 234 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 235 OTX2_CPT_LF_CTL, lf_ctl.u); 236 } 237 238 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf) 239 { 240 otx2_cptlf_set_iqueue_enq(lf, true); 241 } 242 243 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 244 bool enable) 245 { 246 union otx2_cptx_lf_inprog lf_inprog; 247 248 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 249 OTX2_CPT_LF_INPROG); 250 251 /* Set iqueue's execution */ 252 lf_inprog.s.eena = enable ? 0x1 : 0x0; 253 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 254 OTX2_CPT_LF_INPROG, lf_inprog.u); 255 } 256 257 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf) 258 { 259 otx2_cptlf_set_iqueue_exec(lf, true); 260 } 261 262 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf) 263 { 264 otx2_cptlf_set_iqueue_exec(lf, false); 265 } 266 267 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs) 268 { 269 int slot; 270 271 for (slot = 0; slot < lfs->lfs_num; slot++) { 272 otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]); 273 otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]); 274 } 275 } 276 277 static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst, 278 struct otx2_cpt_iq_command *iq_cmd, 279 u64 comp_baddr) 280 { 281 cptinst->u[0] = 0x0; 282 cptinst->s.doneint = true; 283 cptinst->s.res_addr = comp_baddr; 284 cptinst->u[2] = 0x0; 285 cptinst->u[3] = 0x0; 286 cptinst->s.ei0 = iq_cmd->cmd.u; 287 cptinst->s.ei1 = iq_cmd->dptr; 288 cptinst->s.ei2 = iq_cmd->rptr; 289 cptinst->s.ei3 = iq_cmd->cptr.u; 290 } 291 292 /* 293 * On OcteonTX2 platform the parameter insts_num is used as a count of 294 * instructions to be enqueued. The valid values for insts_num are: 295 * 1 - 1 CPT instruction will be enqueued during LMTST operation 296 * 2 - 2 CPT instructions will be enqueued during LMTST operation 297 */ 298 static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, 299 u32 insts_num, struct otx2_cptlf_info *lf) 300 { 301 void __iomem *lmtline = lf->lmtline; 302 long ret; 303 304 /* 305 * Make sure memory areas pointed in CPT_INST_S 306 * are flushed before the instruction is sent to CPT 307 */ 308 dma_wmb(); 309 310 do { 311 /* Copy CPT command to LMTLINE */ 312 memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE); 313 314 /* 315 * LDEOR initiates atomic transfer to I/O device 316 * The following will cause the LMTST to fail (the LDEOR 317 * returns zero): 318 * - No stores have been performed to the LMTLINE since it was 319 * last invalidated. 320 * - The bytes which have been stored to LMTLINE since it was 321 * last invalidated form a pattern that is non-contiguous, does 322 * not start at byte 0, or does not end on a 8-byte boundary. 323 * (i.e.comprises a formation of other than 1–16 8-byte 324 * words.) 325 * 326 * These rules are designed such that an operating system 327 * context switch or hypervisor guest switch need have no 328 * knowledge of the LMTST operations; the switch code does not 329 * need to store to LMTCANCEL. Also note as LMTLINE data cannot 330 * be read, there is no information leakage between processes. 331 */ 332 ret = otx2_lmt_flush(lf->ioreg); 333 334 } while (!ret); 335 } 336 337 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri, 338 int lfs_num); 339 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs); 340 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs); 341 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs); 342 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs); 343 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs); 344 345 #endif /* __OTX2_CPTLF_H */ 346