1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 #ifndef __OTX2_CPTLF_H 5 #define __OTX2_CPTLF_H 6 7 #include <mbox.h> 8 #include <rvu.h> 9 #include "otx2_cpt_common.h" 10 11 /* 12 * CPT instruction and pending queues user requested length in CPT_INST_S msgs 13 */ 14 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200 15 16 /* 17 * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S 18 * messages. 19 */ 20 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40) 21 22 /* 23 * CPT instruction and pending queues length in CPT_INST_S messages 24 */ 25 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 26 27 /* CPT instruction queue length in bytes */ 28 #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 29 OTX2_CPT_INST_SIZE) 30 31 /* CPT instruction group queue length in bytes */ 32 #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 33 34 /* CPT FC length in bytes */ 35 #define OTX2_CPT_Q_FC_LEN 128 36 37 /* CPT instruction queue alignment */ 38 #define OTX2_CPT_INST_Q_ALIGNMENT 128 39 40 /* Mask which selects all engine groups */ 41 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF 42 43 /* Maximum LFs supported in OcteonTX2 for CPT */ 44 #define OTX2_CPT_MAX_LFS_NUM 64 45 46 /* Queue priority */ 47 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 48 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0 49 50 enum otx2_cptlf_state { 51 OTX2_CPTLF_IN_RESET, 52 OTX2_CPTLF_STARTED, 53 }; 54 55 struct otx2_cpt_inst_queue { 56 u8 *vaddr; 57 u8 *real_vaddr; 58 dma_addr_t dma_addr; 59 dma_addr_t real_dma_addr; 60 u32 size; 61 }; 62 63 struct otx2_cptlfs_info; 64 struct otx2_cptlf_wqe { 65 struct tasklet_struct work; 66 struct otx2_cptlfs_info *lfs; 67 u8 lf_num; 68 }; 69 70 struct otx2_cptlf_info { 71 struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */ 72 void __iomem *lmtline; /* Address of LMTLINE */ 73 void __iomem *ioreg; /* LMTLINE send register */ 74 int msix_offset; /* MSI-X interrupts offset */ 75 cpumask_var_t affinity_mask; /* IRQs affinity mask */ 76 u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */ 77 u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */ 78 u8 slot; /* Slot number of this LF */ 79 80 struct otx2_cpt_inst_queue iqueue;/* Instruction queue */ 81 struct otx2_cptlf_wqe *wqe; /* Tasklet work info */ 82 }; 83 84 struct otx2_cptlfs_info { 85 /* Registers start address of VF/PF LFs are attached to */ 86 void __iomem *reg_base; 87 struct pci_dev *pdev; /* Device LFs are attached to */ 88 struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM]; 89 struct otx2_mbox *mbox; 90 u8 are_lfs_attached; /* Whether CPT LFs are attached */ 91 u8 lfs_num; /* Number of CPT LFs */ 92 atomic_t state; /* LF's state. started/reset */ 93 }; 94 95 static inline void otx2_cpt_free_instruction_queues( 96 struct otx2_cptlfs_info *lfs) 97 { 98 struct otx2_cpt_inst_queue *iq; 99 int i; 100 101 for (i = 0; i < lfs->lfs_num; i++) { 102 iq = &lfs->lf[i].iqueue; 103 if (iq->real_vaddr) 104 dma_free_coherent(&lfs->pdev->dev, 105 iq->size, 106 iq->real_vaddr, 107 iq->real_dma_addr); 108 iq->real_vaddr = NULL; 109 iq->vaddr = NULL; 110 } 111 } 112 113 static inline int otx2_cpt_alloc_instruction_queues( 114 struct otx2_cptlfs_info *lfs) 115 { 116 struct otx2_cpt_inst_queue *iq; 117 int ret = 0, i; 118 119 if (!lfs->lfs_num) 120 return -EINVAL; 121 122 for (i = 0; i < lfs->lfs_num; i++) { 123 iq = &lfs->lf[i].iqueue; 124 iq->size = OTX2_CPT_INST_QLEN_BYTES + 125 OTX2_CPT_Q_FC_LEN + 126 OTX2_CPT_INST_GRP_QLEN_BYTES + 127 OTX2_CPT_INST_Q_ALIGNMENT; 128 iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size, 129 &iq->real_dma_addr, GFP_KERNEL); 130 if (!iq->real_vaddr) { 131 ret = -ENOMEM; 132 goto error; 133 } 134 iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES; 135 iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES; 136 137 /* Align pointers */ 138 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT); 139 iq->dma_addr = PTR_ALIGN(iq->dma_addr, 140 OTX2_CPT_INST_Q_ALIGNMENT); 141 } 142 return 0; 143 144 error: 145 otx2_cpt_free_instruction_queues(lfs); 146 return ret; 147 } 148 149 static inline void otx2_cptlf_set_iqueues_base_addr( 150 struct otx2_cptlfs_info *lfs) 151 { 152 union otx2_cptx_lf_q_base lf_q_base; 153 int slot; 154 155 for (slot = 0; slot < lfs->lfs_num; slot++) { 156 lf_q_base.u = lfs->lf[slot].iqueue.dma_addr; 157 otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, 158 OTX2_CPT_LF_Q_BASE, lf_q_base.u); 159 } 160 } 161 162 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 163 { 164 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 165 166 lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 167 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 168 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 169 } 170 171 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs) 172 { 173 int slot; 174 175 for (slot = 0; slot < lfs->lfs_num; slot++) 176 otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]); 177 } 178 179 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 180 { 181 union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 }; 182 union otx2_cptx_lf_inprog lf_inprog; 183 int timeout = 20; 184 185 /* Disable instructions enqueuing */ 186 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 187 OTX2_CPT_LF_CTL, lf_ctl.u); 188 189 /* Wait for instruction queue to become empty */ 190 do { 191 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, 192 lf->slot, OTX2_CPT_LF_INPROG); 193 if (!lf_inprog.s.inflight) 194 break; 195 196 usleep_range(10000, 20000); 197 if (timeout-- < 0) { 198 dev_err(&lf->lfs->pdev->dev, 199 "Error LF %d is still busy.\n", lf->slot); 200 break; 201 } 202 203 } while (1); 204 205 /* 206 * Disable executions in the LF's queue, 207 * the queue should be empty at this point 208 */ 209 lf_inprog.s.eena = 0x0; 210 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 211 OTX2_CPT_LF_INPROG, lf_inprog.u); 212 } 213 214 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 215 { 216 int slot; 217 218 for (slot = 0; slot < lfs->lfs_num; slot++) 219 otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]); 220 } 221 222 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf, 223 bool enable) 224 { 225 union otx2_cptx_lf_ctl lf_ctl; 226 227 lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 228 OTX2_CPT_LF_CTL); 229 230 /* Set iqueue's enqueuing */ 231 lf_ctl.s.ena = enable ? 0x1 : 0x0; 232 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 233 OTX2_CPT_LF_CTL, lf_ctl.u); 234 } 235 236 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf) 237 { 238 otx2_cptlf_set_iqueue_enq(lf, true); 239 } 240 241 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 242 bool enable) 243 { 244 union otx2_cptx_lf_inprog lf_inprog; 245 246 lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 247 OTX2_CPT_LF_INPROG); 248 249 /* Set iqueue's execution */ 250 lf_inprog.s.eena = enable ? 0x1 : 0x0; 251 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 252 OTX2_CPT_LF_INPROG, lf_inprog.u); 253 } 254 255 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf) 256 { 257 otx2_cptlf_set_iqueue_exec(lf, true); 258 } 259 260 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf) 261 { 262 otx2_cptlf_set_iqueue_exec(lf, false); 263 } 264 265 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs) 266 { 267 int slot; 268 269 for (slot = 0; slot < lfs->lfs_num; slot++) { 270 otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]); 271 otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]); 272 } 273 } 274 275 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri, 276 int lfs_num); 277 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs); 278 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs); 279 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs); 280 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs); 281 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs); 282 283 #endif /* __OTX2_CPTLF_H */ 284