1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (C) 2020 Marvell.
3  */
4 
5 #ifndef __OTX2_CPT_HW_TYPES_H
6 #define __OTX2_CPT_HW_TYPES_H
7 
8 #include <linux/types.h>
9 
10 /* Device IDs */
11 #define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD
12 #define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE
13 #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
14 #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3
15 
16 /* Mailbox interrupts offset */
17 #define OTX2_CPT_PF_MBOX_INT	6
18 #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
19 
20 /* Maximum supported microcode groups */
21 #define OTX2_CPT_MAX_ENGINE_GROUPS 8
22 
23 /* CPT instruction size in bytes */
24 #define OTX2_CPT_INST_SIZE	64
25 /*
26  * CPT VF MSIX vectors and their offsets
27  */
28 #define OTX2_CPT_VF_MSIX_VECTORS 1
29 #define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)
30 #define CN10K_CPT_VF_MBOX_REGION  (0xC0000)
31 
32 /* CPT LF MSIX vectors */
33 #define OTX2_CPT_LF_MSIX_VECTORS 2
34 
35 /* OcteonTX2 CPT PF registers */
36 #define OTX2_CPT_PF_CONSTANTS           (0x0)
37 #define OTX2_CPT_PF_RESET               (0x100)
38 #define OTX2_CPT_PF_DIAG                (0x120)
39 #define OTX2_CPT_PF_BIST_STATUS         (0x160)
40 #define OTX2_CPT_PF_ECC0_CTL            (0x200)
41 #define OTX2_CPT_PF_ECC0_FLIP           (0x210)
42 #define OTX2_CPT_PF_ECC0_INT            (0x220)
43 #define OTX2_CPT_PF_ECC0_INT_W1S        (0x230)
44 #define OTX2_CPT_PF_ECC0_ENA_W1S        (0x240)
45 #define OTX2_CPT_PF_ECC0_ENA_W1C        (0x250)
46 #define OTX2_CPT_PF_MBOX_INTX(b)        (0x400 | (b) << 3)
47 #define OTX2_CPT_PF_MBOX_INT_W1SX(b)    (0x420 | (b) << 3)
48 #define OTX2_CPT_PF_MBOX_ENA_W1CX(b)    (0x440 | (b) << 3)
49 #define OTX2_CPT_PF_MBOX_ENA_W1SX(b)    (0x460 | (b) << 3)
50 #define OTX2_CPT_PF_EXEC_INT            (0x500)
51 #define OTX2_CPT_PF_EXEC_INT_W1S        (0x520)
52 #define OTX2_CPT_PF_EXEC_ENA_W1C        (0x540)
53 #define OTX2_CPT_PF_EXEC_ENA_W1S        (0x560)
54 #define OTX2_CPT_PF_GX_EN(b)            (0x600 | (b) << 3)
55 #define OTX2_CPT_PF_EXEC_INFO           (0x700)
56 #define OTX2_CPT_PF_EXEC_BUSY           (0x800)
57 #define OTX2_CPT_PF_EXEC_INFO0          (0x900)
58 #define OTX2_CPT_PF_EXEC_INFO1          (0x910)
59 #define OTX2_CPT_PF_INST_REQ_PC         (0x10000)
60 #define OTX2_CPT_PF_INST_LATENCY_PC     (0x10020)
61 #define OTX2_CPT_PF_RD_REQ_PC           (0x10040)
62 #define OTX2_CPT_PF_RD_LATENCY_PC       (0x10060)
63 #define OTX2_CPT_PF_RD_UC_PC            (0x10080)
64 #define OTX2_CPT_PF_ACTIVE_CYCLES_PC    (0x10100)
65 #define OTX2_CPT_PF_EXE_CTL             (0x4000000)
66 #define OTX2_CPT_PF_EXE_STATUS          (0x4000008)
67 #define OTX2_CPT_PF_EXE_CLK             (0x4000010)
68 #define OTX2_CPT_PF_EXE_DBG_CTL         (0x4000018)
69 #define OTX2_CPT_PF_EXE_DBG_DATA        (0x4000020)
70 #define OTX2_CPT_PF_EXE_BIST_STATUS     (0x4000028)
71 #define OTX2_CPT_PF_EXE_REQ_TIMER       (0x4000030)
72 #define OTX2_CPT_PF_EXE_MEM_CTL         (0x4000038)
73 #define OTX2_CPT_PF_EXE_PERF_CTL        (0x4001000)
74 #define OTX2_CPT_PF_EXE_DBG_CNTX(b)     (0x4001100 | (b) << 3)
75 #define OTX2_CPT_PF_EXE_PERF_EVENT_CNT  (0x4001180)
76 #define OTX2_CPT_PF_EXE_EPCI_INBX_CNT(b)  (0x4001200 | (b) << 3)
77 #define OTX2_CPT_PF_EXE_EPCI_OUTBX_CNT(b) (0x4001240 | (b) << 3)
78 #define OTX2_CPT_PF_ENGX_UCODE_BASE(b)  (0x4002000 | (b) << 3)
79 #define OTX2_CPT_PF_QX_CTL(b)           (0x8000000 | (b) << 20)
80 #define OTX2_CPT_PF_QX_GMCTL(b)         (0x8000020 | (b) << 20)
81 #define OTX2_CPT_PF_QX_CTL2(b)          (0x8000100 | (b) << 20)
82 #define OTX2_CPT_PF_VFX_MBOXX(b, c)     (0x8001000 | (b) << 20 | \
83 					 (c) << 8)
84 
85 /* OcteonTX2 CPT LF registers */
86 #define OTX2_CPT_LF_CTL                 (0x10)
87 #define OTX2_CPT_LF_DONE_WAIT           (0x30)
88 #define OTX2_CPT_LF_INPROG              (0x40)
89 #define OTX2_CPT_LF_DONE                (0x50)
90 #define OTX2_CPT_LF_DONE_ACK            (0x60)
91 #define OTX2_CPT_LF_DONE_INT_ENA_W1S    (0x90)
92 #define OTX2_CPT_LF_DONE_INT_ENA_W1C    (0xa0)
93 #define OTX2_CPT_LF_MISC_INT            (0xb0)
94 #define OTX2_CPT_LF_MISC_INT_W1S        (0xc0)
95 #define OTX2_CPT_LF_MISC_INT_ENA_W1S    (0xd0)
96 #define OTX2_CPT_LF_MISC_INT_ENA_W1C    (0xe0)
97 #define OTX2_CPT_LF_Q_BASE              (0xf0)
98 #define OTX2_CPT_LF_Q_SIZE              (0x100)
99 #define OTX2_CPT_LF_Q_INST_PTR          (0x110)
100 #define OTX2_CPT_LF_Q_GRP_PTR           (0x120)
101 #define OTX2_CPT_LF_NQX(a)              (0x400 | (a) << 3)
102 #define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
103 /* LMT LF registers */
104 #define OTX2_CPT_LMT_LFBASE             BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)
105 #define OTX2_CPT_LMT_LF_LMTLINEX(a)     (OTX2_CPT_LMT_LFBASE | 0x000 | \
106 					 (a) << 12)
107 /* RVU VF registers */
108 #define OTX2_RVU_VF_INT                 (0x20)
109 #define OTX2_RVU_VF_INT_W1S             (0x28)
110 #define OTX2_RVU_VF_INT_ENA_W1S         (0x30)
111 #define OTX2_RVU_VF_INT_ENA_W1C         (0x38)
112 
113 /*
114  * Enumeration otx2_cpt_ucode_error_code_e
115  *
116  * Enumerates ucode errors
117  */
118 enum otx2_cpt_ucode_comp_code_e {
119 	OTX2_CPT_UCC_SUCCESS = 0x00,
120 	OTX2_CPT_UCC_INVALID_OPCODE = 0x01,
121 
122 	/* Scatter gather */
123 	OTX2_CPT_UCC_SG_WRITE_LENGTH = 0x02,
124 	OTX2_CPT_UCC_SG_LIST = 0x03,
125 	OTX2_CPT_UCC_SG_NOT_SUPPORTED = 0x04,
126 
127 };
128 
129 /*
130  * Enumeration otx2_cpt_comp_e
131  *
132  * OcteonTX2 CPT Completion Enumeration
133  * Enumerates the values of CPT_RES_S[COMPCODE].
134  */
135 enum otx2_cpt_comp_e {
136 	OTX2_CPT_COMP_E_NOTDONE = 0x00,
137 	OTX2_CPT_COMP_E_GOOD = 0x01,
138 	OTX2_CPT_COMP_E_FAULT = 0x02,
139 	OTX2_CPT_COMP_E_HWERR = 0x04,
140 	OTX2_CPT_COMP_E_INSTERR = 0x05,
141 	OTX2_CPT_COMP_E_LAST_ENTRY = 0x06
142 };
143 
144 /*
145  * Enumeration otx2_cpt_vf_int_vec_e
146  *
147  * OcteonTX2 CPT VF MSI-X Vector Enumeration
148  * Enumerates the MSI-X interrupt vectors.
149  */
150 enum otx2_cpt_vf_int_vec_e {
151 	OTX2_CPT_VF_INT_VEC_E_MBOX = 0x00
152 };
153 
154 /*
155  * Enumeration otx2_cpt_lf_int_vec_e
156  *
157  * OcteonTX2 CPT LF MSI-X Vector Enumeration
158  * Enumerates the MSI-X interrupt vectors.
159  */
160 enum otx2_cpt_lf_int_vec_e {
161 	OTX2_CPT_LF_INT_VEC_E_MISC = 0x00,
162 	OTX2_CPT_LF_INT_VEC_E_DONE = 0x01
163 };
164 
165 /*
166  * Structure otx2_cpt_inst_s
167  *
168  * CPT Instruction Structure
169  * This structure specifies the instruction layout. Instructions are
170  * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
171  * cpt_inst_s_s
172  * Word 0
173  * doneint:1 Done interrupt.
174  *	0 = No interrupts related to this instruction.
175  *	1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
176  *	incremented,and based on the rules described there an interrupt may
177  *	occur.
178  * Word 1
179  * res_addr [127: 64] Result IOVA.
180  *	If nonzero, specifies where to write CPT_RES_S.
181  *	If zero, no result structure will be written.
182  *	Address must be 16-byte aligned.
183  *	Bits <63:49> are ignored by hardware; software should use a
184  *	sign-extended bit <48> for forward compatibility.
185  * Word 2
186  *  grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
187  *	CPT submits work SSO.
188  *	For the SSO to not discard the add-work request, FPA_PF_MAP() must map
189  *	[GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
190  *  tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
191  *	submits work to SSO
192  *  tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
193  *	submits work to SSO.
194  * Word 3
195  *  wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
196  *	work-queue entry that CPT submits work to SSO after all context,
197  *	output data, and result write operations are visible to other
198  *	CNXXXX units and the cores. Bits <2:0> must be zero.
199  *	Bits <63:49> are ignored by hardware; software should
200  *	use a sign-extended bit <48> for forward compatibility.
201  *	Internal:
202  *	Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
203  * Word 4
204  *  ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
205  * Word 5
206  *  ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
207  * Word 6
208  *  ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
209  * Word 7
210  *  ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
211  *
212  */
213 union otx2_cpt_inst_s {
214 	u64 u[8];
215 
216 	struct {
217 		/* Word 0 */
218 		u64 nixtxl:3;
219 		u64 doneint:1;
220 		u64 nixtx_addr:60;
221 		/* Word 1 */
222 		u64 res_addr;
223 		/* Word 2 */
224 		u64 tag:32;
225 		u64 tt:2;
226 		u64 grp:10;
227 		u64 reserved_172_175:4;
228 		u64 rvu_pf_func:16;
229 		/* Word 3 */
230 		u64 qord:1;
231 		u64 reserved_194_193:2;
232 		u64 wq_ptr:61;
233 		/* Word 4 */
234 		u64 ei0;
235 		/* Word 5 */
236 		u64 ei1;
237 		/* Word 6 */
238 		u64 ei2;
239 		/* Word 7 */
240 		u64 ei3;
241 	} s;
242 };
243 
244 /*
245  * Structure otx2_cpt_res_s
246  *
247  * CPT Result Structure
248  * The CPT coprocessor writes the result structure after it completes a
249  * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
250  * each instruction completion produces exactly one result structure.
251  *
252  * This structure is stored in memory as little-endian unless
253  * CPT()_PF_Q()_CTL[INST_BE] is set.
254  * cpt_res_s_s
255  * Word 0
256  *  doneint:1 [16:16] Done interrupt. This bit is copied from the
257  *	corresponding instruction's CPT_INST_S[DONEINT].
258  *  compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
259  *	for the	associated instruction, as enumerated by CPT_COMP_E.
260  *	Core software may write the memory location containing [COMPCODE] to
261  *	0x0 before ringing the doorbell, and then poll for completion by
262  *	checking for a nonzero value.
263  *	Once the core observes a nonzero [COMPCODE] value in this case,the CPT
264  *	coprocessor will have also completed L2/DRAM write operations.
265  * Word 1
266  *  reserved
267  *
268  */
269 union otx2_cpt_res_s {
270 	u64 u[2];
271 
272 	struct {
273 		u64 compcode:8;
274 		u64 uc_compcode:8;
275 		u64 doneint:1;
276 		u64 reserved_17_63:47;
277 		u64 reserved_64_127;
278 	} s;
279 };
280 
281 /*
282  * Register (RVU_PF_BAR0) cpt#_af_constants1
283  *
284  * CPT AF Constants Register
285  * This register contains implementation-related parameters of CPT.
286  */
287 union otx2_cptx_af_constants1 {
288 	u64 u;
289 	struct otx2_cptx_af_constants1_s {
290 		u64 se:16;
291 		u64 ie:16;
292 		u64 ae:16;
293 		u64 reserved_48_63:16;
294 	} s;
295 };
296 
297 /*
298  * RVU_PFVF_BAR2 - cpt_lf_misc_int
299  *
300  * This register contain the per-queue miscellaneous interrupts.
301  *
302  */
303 union otx2_cptx_lf_misc_int {
304 	u64 u;
305 	struct otx2_cptx_lf_misc_int_s {
306 		u64 reserved_0:1;
307 		u64 nqerr:1;
308 		u64 irde:1;
309 		u64 nwrp:1;
310 		u64 reserved_4:1;
311 		u64 hwerr:1;
312 		u64 fault:1;
313 		u64 reserved_7_63:57;
314 	} s;
315 };
316 
317 /*
318  * RVU_PFVF_BAR2 - cpt_lf_misc_int_ena_w1s
319  *
320  * This register sets interrupt enable bits.
321  *
322  */
323 union otx2_cptx_lf_misc_int_ena_w1s {
324 	u64 u;
325 	struct otx2_cptx_lf_misc_int_ena_w1s_s {
326 		u64 reserved_0:1;
327 		u64 nqerr:1;
328 		u64 irde:1;
329 		u64 nwrp:1;
330 		u64 reserved_4:1;
331 		u64 hwerr:1;
332 		u64 fault:1;
333 		u64 reserved_7_63:57;
334 	} s;
335 };
336 
337 /*
338  * RVU_PFVF_BAR2 - cpt_lf_ctl
339  *
340  * This register configures the queue.
341  *
342  * When the queue is not execution-quiescent (see CPT_LF_INPROG[EENA,INFLIGHT]),
343  * software must only write this register with [ENA]=0.
344  */
345 union otx2_cptx_lf_ctl {
346 	u64 u;
347 	struct otx2_cptx_lf_ctl_s {
348 		u64 ena:1;
349 		u64 fc_ena:1;
350 		u64 fc_up_crossing:1;
351 		u64 reserved_3:1;
352 		u64 fc_hyst_bits:4;
353 		u64 reserved_8_63:56;
354 	} s;
355 };
356 
357 /*
358  * RVU_PFVF_BAR2 - cpt_lf_done_wait
359  *
360  * This register specifies the per-queue interrupt coalescing settings.
361  */
362 union otx2_cptx_lf_done_wait {
363 	u64 u;
364 	struct otx2_cptx_lf_done_wait_s {
365 		u64 num_wait:20;
366 		u64 reserved_20_31:12;
367 		u64 time_wait:16;
368 		u64 reserved_48_63:16;
369 	} s;
370 };
371 
372 /*
373  * RVU_PFVF_BAR2 - cpt_lf_done
374  *
375  * This register contain the per-queue instruction done count.
376  */
377 union otx2_cptx_lf_done {
378 	u64 u;
379 	struct otx2_cptx_lf_done_s {
380 		u64 done:20;
381 		u64 reserved_20_63:44;
382 	} s;
383 };
384 
385 /*
386  * RVU_PFVF_BAR2 - cpt_lf_inprog
387  *
388  * These registers contain the per-queue instruction in flight registers.
389  *
390  */
391 union otx2_cptx_lf_inprog {
392 	u64 u;
393 	struct otx2_cptx_lf_inprog_s {
394 		u64 inflight:9;
395 		u64 reserved_9_15:7;
396 		u64 eena:1;
397 		u64 grp_drp:1;
398 		u64 reserved_18_30:13;
399 		u64 grb_partial:1;
400 		u64 grb_cnt:8;
401 		u64 gwb_cnt:8;
402 		u64 reserved_48_63:16;
403 	} s;
404 };
405 
406 /*
407  * RVU_PFVF_BAR2 - cpt_lf_q_base
408  *
409  * CPT initializes these CSR fields to these values on any CPT_LF_Q_BASE write:
410  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
411  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
412  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
413  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
414  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
415  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
416  */
417 union otx2_cptx_lf_q_base {
418 	u64 u;
419 	struct otx2_cptx_lf_q_base_s {
420 		u64 fault:1;
421 		u64 reserved_1_6:6;
422 		u64 addr:46;
423 		u64 reserved_53_63:11;
424 	} s;
425 };
426 
427 /*
428  * RVU_PFVF_BAR2 - cpt_lf_q_size
429  *
430  * CPT initializes these CSR fields to these values on any CPT_LF_Q_SIZE write:
431  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
432  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
433  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
434  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
435  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
436  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
437  */
438 union otx2_cptx_lf_q_size {
439 	u64 u;
440 	struct otx2_cptx_lf_q_size_s {
441 		u64 size_div40:15;
442 		u64 reserved_15_63:49;
443 	} s;
444 };
445 
446 /*
447  * RVU_PF_BAR0 - cpt_af_lf_ctl
448  *
449  * This register configures queues. This register should be written only
450  * when the queue is execution-quiescent (see CPT_LF_INPROG[INFLIGHT]).
451  */
452 union otx2_cptx_af_lf_ctrl {
453 	u64 u;
454 	struct otx2_cptx_af_lf_ctrl_s {
455 		u64 pri:1;
456 		u64 reserved_1_8:8;
457 		u64 pf_func_inst:1;
458 		u64 cont_err:1;
459 		u64 reserved_11_15:5;
460 		u64 nixtx_en:1;
461 		u64 reserved_17_47:31;
462 		u64 grp:8;
463 		u64 reserved_56_63:8;
464 	} s;
465 };
466 
467 #endif /* __OTX2_CPT_HW_TYPES_H */
468