1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (C) 2020 Marvell.
3  */
4 
5 #ifndef __OTX2_CPT_HW_TYPES_H
6 #define __OTX2_CPT_HW_TYPES_H
7 
8 #include <linux/types.h>
9 
10 /* Device IDs */
11 #define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD
12 #define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE
13 
14 /* Mailbox interrupts offset */
15 #define OTX2_CPT_PF_MBOX_INT	6
16 #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
17 
18 /* Maximum supported microcode groups */
19 #define OTX2_CPT_MAX_ENGINE_GROUPS 8
20 
21 /* CPT instruction size in bytes */
22 #define OTX2_CPT_INST_SIZE	64
23 /*
24  * CPT VF MSIX vectors and their offsets
25  */
26 #define OTX2_CPT_VF_MSIX_VECTORS 1
27 #define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)
28 
29 /* CPT LF MSIX vectors */
30 #define OTX2_CPT_LF_MSIX_VECTORS 2
31 
32 /* OcteonTX2 CPT PF registers */
33 #define OTX2_CPT_PF_CONSTANTS           (0x0)
34 #define OTX2_CPT_PF_RESET               (0x100)
35 #define OTX2_CPT_PF_DIAG                (0x120)
36 #define OTX2_CPT_PF_BIST_STATUS         (0x160)
37 #define OTX2_CPT_PF_ECC0_CTL            (0x200)
38 #define OTX2_CPT_PF_ECC0_FLIP           (0x210)
39 #define OTX2_CPT_PF_ECC0_INT            (0x220)
40 #define OTX2_CPT_PF_ECC0_INT_W1S        (0x230)
41 #define OTX2_CPT_PF_ECC0_ENA_W1S        (0x240)
42 #define OTX2_CPT_PF_ECC0_ENA_W1C        (0x250)
43 #define OTX2_CPT_PF_MBOX_INTX(b)        (0x400 | (b) << 3)
44 #define OTX2_CPT_PF_MBOX_INT_W1SX(b)    (0x420 | (b) << 3)
45 #define OTX2_CPT_PF_MBOX_ENA_W1CX(b)    (0x440 | (b) << 3)
46 #define OTX2_CPT_PF_MBOX_ENA_W1SX(b)    (0x460 | (b) << 3)
47 #define OTX2_CPT_PF_EXEC_INT            (0x500)
48 #define OTX2_CPT_PF_EXEC_INT_W1S        (0x520)
49 #define OTX2_CPT_PF_EXEC_ENA_W1C        (0x540)
50 #define OTX2_CPT_PF_EXEC_ENA_W1S        (0x560)
51 #define OTX2_CPT_PF_GX_EN(b)            (0x600 | (b) << 3)
52 #define OTX2_CPT_PF_EXEC_INFO           (0x700)
53 #define OTX2_CPT_PF_EXEC_BUSY           (0x800)
54 #define OTX2_CPT_PF_EXEC_INFO0          (0x900)
55 #define OTX2_CPT_PF_EXEC_INFO1          (0x910)
56 #define OTX2_CPT_PF_INST_REQ_PC         (0x10000)
57 #define OTX2_CPT_PF_INST_LATENCY_PC     (0x10020)
58 #define OTX2_CPT_PF_RD_REQ_PC           (0x10040)
59 #define OTX2_CPT_PF_RD_LATENCY_PC       (0x10060)
60 #define OTX2_CPT_PF_RD_UC_PC            (0x10080)
61 #define OTX2_CPT_PF_ACTIVE_CYCLES_PC    (0x10100)
62 #define OTX2_CPT_PF_EXE_CTL             (0x4000000)
63 #define OTX2_CPT_PF_EXE_STATUS          (0x4000008)
64 #define OTX2_CPT_PF_EXE_CLK             (0x4000010)
65 #define OTX2_CPT_PF_EXE_DBG_CTL         (0x4000018)
66 #define OTX2_CPT_PF_EXE_DBG_DATA        (0x4000020)
67 #define OTX2_CPT_PF_EXE_BIST_STATUS     (0x4000028)
68 #define OTX2_CPT_PF_EXE_REQ_TIMER       (0x4000030)
69 #define OTX2_CPT_PF_EXE_MEM_CTL         (0x4000038)
70 #define OTX2_CPT_PF_EXE_PERF_CTL        (0x4001000)
71 #define OTX2_CPT_PF_EXE_DBG_CNTX(b)     (0x4001100 | (b) << 3)
72 #define OTX2_CPT_PF_EXE_PERF_EVENT_CNT  (0x4001180)
73 #define OTX2_CPT_PF_EXE_EPCI_INBX_CNT(b)  (0x4001200 | (b) << 3)
74 #define OTX2_CPT_PF_EXE_EPCI_OUTBX_CNT(b) (0x4001240 | (b) << 3)
75 #define OTX2_CPT_PF_ENGX_UCODE_BASE(b)  (0x4002000 | (b) << 3)
76 #define OTX2_CPT_PF_QX_CTL(b)           (0x8000000 | (b) << 20)
77 #define OTX2_CPT_PF_QX_GMCTL(b)         (0x8000020 | (b) << 20)
78 #define OTX2_CPT_PF_QX_CTL2(b)          (0x8000100 | (b) << 20)
79 #define OTX2_CPT_PF_VFX_MBOXX(b, c)     (0x8001000 | (b) << 20 | \
80 					 (c) << 8)
81 
82 /* OcteonTX2 CPT LF registers */
83 #define OTX2_CPT_LF_CTL                 (0x10)
84 #define OTX2_CPT_LF_DONE_WAIT           (0x30)
85 #define OTX2_CPT_LF_INPROG              (0x40)
86 #define OTX2_CPT_LF_DONE                (0x50)
87 #define OTX2_CPT_LF_DONE_ACK            (0x60)
88 #define OTX2_CPT_LF_DONE_INT_ENA_W1S    (0x90)
89 #define OTX2_CPT_LF_DONE_INT_ENA_W1C    (0xa0)
90 #define OTX2_CPT_LF_MISC_INT            (0xb0)
91 #define OTX2_CPT_LF_MISC_INT_W1S        (0xc0)
92 #define OTX2_CPT_LF_MISC_INT_ENA_W1S    (0xd0)
93 #define OTX2_CPT_LF_MISC_INT_ENA_W1C    (0xe0)
94 #define OTX2_CPT_LF_Q_BASE              (0xf0)
95 #define OTX2_CPT_LF_Q_SIZE              (0x100)
96 #define OTX2_CPT_LF_Q_INST_PTR          (0x110)
97 #define OTX2_CPT_LF_Q_GRP_PTR           (0x120)
98 #define OTX2_CPT_LF_NQX(a)              (0x400 | (a) << 3)
99 #define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
100 /* LMT LF registers */
101 #define OTX2_CPT_LMT_LFBASE             BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)
102 #define OTX2_CPT_LMT_LF_LMTLINEX(a)     (OTX2_CPT_LMT_LFBASE | 0x000 | \
103 					 (a) << 12)
104 /* RVU VF registers */
105 #define OTX2_RVU_VF_INT                 (0x20)
106 #define OTX2_RVU_VF_INT_W1S             (0x28)
107 #define OTX2_RVU_VF_INT_ENA_W1S         (0x30)
108 #define OTX2_RVU_VF_INT_ENA_W1C         (0x38)
109 
110 /*
111  * Enumeration otx2_cpt_ucode_error_code_e
112  *
113  * Enumerates ucode errors
114  */
115 enum otx2_cpt_ucode_comp_code_e {
116 	OTX2_CPT_UCC_SUCCESS = 0x00,
117 	OTX2_CPT_UCC_INVALID_OPCODE = 0x01,
118 
119 	/* Scatter gather */
120 	OTX2_CPT_UCC_SG_WRITE_LENGTH = 0x02,
121 	OTX2_CPT_UCC_SG_LIST = 0x03,
122 	OTX2_CPT_UCC_SG_NOT_SUPPORTED = 0x04,
123 
124 };
125 
126 /*
127  * Enumeration otx2_cpt_comp_e
128  *
129  * OcteonTX2 CPT Completion Enumeration
130  * Enumerates the values of CPT_RES_S[COMPCODE].
131  */
132 enum otx2_cpt_comp_e {
133 	OTX2_CPT_COMP_E_NOTDONE = 0x00,
134 	OTX2_CPT_COMP_E_GOOD = 0x01,
135 	OTX2_CPT_COMP_E_FAULT = 0x02,
136 	OTX2_CPT_COMP_E_HWERR = 0x04,
137 	OTX2_CPT_COMP_E_INSTERR = 0x05,
138 	OTX2_CPT_COMP_E_LAST_ENTRY = 0x06
139 };
140 
141 /*
142  * Enumeration otx2_cpt_vf_int_vec_e
143  *
144  * OcteonTX2 CPT VF MSI-X Vector Enumeration
145  * Enumerates the MSI-X interrupt vectors.
146  */
147 enum otx2_cpt_vf_int_vec_e {
148 	OTX2_CPT_VF_INT_VEC_E_MBOX = 0x00
149 };
150 
151 /*
152  * Enumeration otx2_cpt_lf_int_vec_e
153  *
154  * OcteonTX2 CPT LF MSI-X Vector Enumeration
155  * Enumerates the MSI-X interrupt vectors.
156  */
157 enum otx2_cpt_lf_int_vec_e {
158 	OTX2_CPT_LF_INT_VEC_E_MISC = 0x00,
159 	OTX2_CPT_LF_INT_VEC_E_DONE = 0x01
160 };
161 
162 /*
163  * Structure otx2_cpt_inst_s
164  *
165  * CPT Instruction Structure
166  * This structure specifies the instruction layout. Instructions are
167  * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
168  * cpt_inst_s_s
169  * Word 0
170  * doneint:1 Done interrupt.
171  *	0 = No interrupts related to this instruction.
172  *	1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
173  *	incremented,and based on the rules described there an interrupt may
174  *	occur.
175  * Word 1
176  * res_addr [127: 64] Result IOVA.
177  *	If nonzero, specifies where to write CPT_RES_S.
178  *	If zero, no result structure will be written.
179  *	Address must be 16-byte aligned.
180  *	Bits <63:49> are ignored by hardware; software should use a
181  *	sign-extended bit <48> for forward compatibility.
182  * Word 2
183  *  grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
184  *	CPT submits work SSO.
185  *	For the SSO to not discard the add-work request, FPA_PF_MAP() must map
186  *	[GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
187  *  tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
188  *	submits work to SSO
189  *  tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
190  *	submits work to SSO.
191  * Word 3
192  *  wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
193  *	work-queue entry that CPT submits work to SSO after all context,
194  *	output data, and result write operations are visible to other
195  *	CNXXXX units and the cores. Bits <2:0> must be zero.
196  *	Bits <63:49> are ignored by hardware; software should
197  *	use a sign-extended bit <48> for forward compatibility.
198  *	Internal:
199  *	Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
200  * Word 4
201  *  ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
202  * Word 5
203  *  ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
204  * Word 6
205  *  ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
206  * Word 7
207  *  ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
208  *
209  */
210 union otx2_cpt_inst_s {
211 	u64 u[8];
212 
213 	struct {
214 		/* Word 0 */
215 		u64 nixtxl:3;
216 		u64 doneint:1;
217 		u64 nixtx_addr:60;
218 		/* Word 1 */
219 		u64 res_addr;
220 		/* Word 2 */
221 		u64 tag:32;
222 		u64 tt:2;
223 		u64 grp:10;
224 		u64 reserved_172_175:4;
225 		u64 rvu_pf_func:16;
226 		/* Word 3 */
227 		u64 qord:1;
228 		u64 reserved_194_193:2;
229 		u64 wq_ptr:61;
230 		/* Word 4 */
231 		u64 ei0;
232 		/* Word 5 */
233 		u64 ei1;
234 		/* Word 6 */
235 		u64 ei2;
236 		/* Word 7 */
237 		u64 ei3;
238 	} s;
239 };
240 
241 /*
242  * Structure otx2_cpt_res_s
243  *
244  * CPT Result Structure
245  * The CPT coprocessor writes the result structure after it completes a
246  * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
247  * each instruction completion produces exactly one result structure.
248  *
249  * This structure is stored in memory as little-endian unless
250  * CPT()_PF_Q()_CTL[INST_BE] is set.
251  * cpt_res_s_s
252  * Word 0
253  *  doneint:1 [16:16] Done interrupt. This bit is copied from the
254  *	corresponding instruction's CPT_INST_S[DONEINT].
255  *  compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
256  *	for the	associated instruction, as enumerated by CPT_COMP_E.
257  *	Core software may write the memory location containing [COMPCODE] to
258  *	0x0 before ringing the doorbell, and then poll for completion by
259  *	checking for a nonzero value.
260  *	Once the core observes a nonzero [COMPCODE] value in this case,the CPT
261  *	coprocessor will have also completed L2/DRAM write operations.
262  * Word 1
263  *  reserved
264  *
265  */
266 union otx2_cpt_res_s {
267 	u64 u[2];
268 
269 	struct {
270 		u64 compcode:8;
271 		u64 uc_compcode:8;
272 		u64 doneint:1;
273 		u64 reserved_17_63:47;
274 		u64 reserved_64_127;
275 	} s;
276 };
277 
278 /*
279  * Register (RVU_PF_BAR0) cpt#_af_constants1
280  *
281  * CPT AF Constants Register
282  * This register contains implementation-related parameters of CPT.
283  */
284 union otx2_cptx_af_constants1 {
285 	u64 u;
286 	struct otx2_cptx_af_constants1_s {
287 		u64 se:16;
288 		u64 ie:16;
289 		u64 ae:16;
290 		u64 reserved_48_63:16;
291 	} s;
292 };
293 
294 /*
295  * RVU_PFVF_BAR2 - cpt_lf_misc_int
296  *
297  * This register contain the per-queue miscellaneous interrupts.
298  *
299  */
300 union otx2_cptx_lf_misc_int {
301 	u64 u;
302 	struct otx2_cptx_lf_misc_int_s {
303 		u64 reserved_0:1;
304 		u64 nqerr:1;
305 		u64 irde:1;
306 		u64 nwrp:1;
307 		u64 reserved_4:1;
308 		u64 hwerr:1;
309 		u64 fault:1;
310 		u64 reserved_7_63:57;
311 	} s;
312 };
313 
314 /*
315  * RVU_PFVF_BAR2 - cpt_lf_misc_int_ena_w1s
316  *
317  * This register sets interrupt enable bits.
318  *
319  */
320 union otx2_cptx_lf_misc_int_ena_w1s {
321 	u64 u;
322 	struct otx2_cptx_lf_misc_int_ena_w1s_s {
323 		u64 reserved_0:1;
324 		u64 nqerr:1;
325 		u64 irde:1;
326 		u64 nwrp:1;
327 		u64 reserved_4:1;
328 		u64 hwerr:1;
329 		u64 fault:1;
330 		u64 reserved_7_63:57;
331 	} s;
332 };
333 
334 /*
335  * RVU_PFVF_BAR2 - cpt_lf_ctl
336  *
337  * This register configures the queue.
338  *
339  * When the queue is not execution-quiescent (see CPT_LF_INPROG[EENA,INFLIGHT]),
340  * software must only write this register with [ENA]=0.
341  */
342 union otx2_cptx_lf_ctl {
343 	u64 u;
344 	struct otx2_cptx_lf_ctl_s {
345 		u64 ena:1;
346 		u64 fc_ena:1;
347 		u64 fc_up_crossing:1;
348 		u64 reserved_3:1;
349 		u64 fc_hyst_bits:4;
350 		u64 reserved_8_63:56;
351 	} s;
352 };
353 
354 /*
355  * RVU_PFVF_BAR2 - cpt_lf_done_wait
356  *
357  * This register specifies the per-queue interrupt coalescing settings.
358  */
359 union otx2_cptx_lf_done_wait {
360 	u64 u;
361 	struct otx2_cptx_lf_done_wait_s {
362 		u64 num_wait:20;
363 		u64 reserved_20_31:12;
364 		u64 time_wait:16;
365 		u64 reserved_48_63:16;
366 	} s;
367 };
368 
369 /*
370  * RVU_PFVF_BAR2 - cpt_lf_done
371  *
372  * This register contain the per-queue instruction done count.
373  */
374 union otx2_cptx_lf_done {
375 	u64 u;
376 	struct otx2_cptx_lf_done_s {
377 		u64 done:20;
378 		u64 reserved_20_63:44;
379 	} s;
380 };
381 
382 /*
383  * RVU_PFVF_BAR2 - cpt_lf_inprog
384  *
385  * These registers contain the per-queue instruction in flight registers.
386  *
387  */
388 union otx2_cptx_lf_inprog {
389 	u64 u;
390 	struct otx2_cptx_lf_inprog_s {
391 		u64 inflight:9;
392 		u64 reserved_9_15:7;
393 		u64 eena:1;
394 		u64 grp_drp:1;
395 		u64 reserved_18_30:13;
396 		u64 grb_partial:1;
397 		u64 grb_cnt:8;
398 		u64 gwb_cnt:8;
399 		u64 reserved_48_63:16;
400 	} s;
401 };
402 
403 /*
404  * RVU_PFVF_BAR2 - cpt_lf_q_base
405  *
406  * CPT initializes these CSR fields to these values on any CPT_LF_Q_BASE write:
407  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
408  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
409  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
410  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
411  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
412  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
413  */
414 union otx2_cptx_lf_q_base {
415 	u64 u;
416 	struct otx2_cptx_lf_q_base_s {
417 		u64 fault:1;
418 		u64 reserved_1_6:6;
419 		u64 addr:46;
420 		u64 reserved_53_63:11;
421 	} s;
422 };
423 
424 /*
425  * RVU_PFVF_BAR2 - cpt_lf_q_size
426  *
427  * CPT initializes these CSR fields to these values on any CPT_LF_Q_SIZE write:
428  * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0.
429  * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2.
430  * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2.
431  * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0.
432  * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1.
433  * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1.
434  */
435 union otx2_cptx_lf_q_size {
436 	u64 u;
437 	struct otx2_cptx_lf_q_size_s {
438 		u64 size_div40:15;
439 		u64 reserved_15_63:49;
440 	} s;
441 };
442 
443 /*
444  * RVU_PF_BAR0 - cpt_af_lf_ctl
445  *
446  * This register configures queues. This register should be written only
447  * when the queue is execution-quiescent (see CPT_LF_INPROG[INFLIGHT]).
448  */
449 union otx2_cptx_af_lf_ctrl {
450 	u64 u;
451 	struct otx2_cptx_af_lf_ctrl_s {
452 		u64 pri:1;
453 		u64 reserved_1_8:8;
454 		u64 pf_func_inst:1;
455 		u64 cont_err:1;
456 		u64 reserved_11_15:5;
457 		u64 nixtx_en:1;
458 		u64 reserved_17_47:31;
459 		u64 grp:8;
460 		u64 reserved_56_63:8;
461 	} s;
462 };
463 
464 #endif /* __OTX2_CPT_HW_TYPES_H */
465