1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (C) 2020 Marvell. 3 */ 4 5 #ifndef __OTX2_CPT_COMMON_H 6 #define __OTX2_CPT_COMMON_H 7 8 #include <linux/pci.h> 9 #include <linux/types.h> 10 #include <linux/module.h> 11 #include <linux/delay.h> 12 #include <linux/crypto.h> 13 #include <net/devlink.h> 14 #include "otx2_cpt_hw_types.h" 15 #include "rvu.h" 16 #include "mbox.h" 17 18 #define OTX2_CPT_MAX_VFS_NUM 128 19 #define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \ 20 (((blk) << 20) | ((slot) << 12) | (offs)) 21 #define OTX2_CPT_RVU_PFFUNC(pf, func) \ 22 ((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \ 23 (((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT)) 24 25 #define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF 26 #define OTX2_CPT_NAME_LENGTH 64 27 #define OTX2_CPT_DMA_MINALIGN 128 28 29 /* HW capability flags */ 30 #define CN10K_MBOX 0 31 #define CN10K_LMTST 1 32 33 #define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES 34 35 enum otx2_cpt_eng_type { 36 OTX2_CPT_AE_TYPES = 1, 37 OTX2_CPT_SE_TYPES = 2, 38 OTX2_CPT_IE_TYPES = 3, 39 OTX2_CPT_MAX_ENG_TYPES, 40 }; 41 42 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */ 43 #define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF 44 #define MBOX_MSG_GET_CAPS 0xBFD 45 #define MBOX_MSG_GET_KVF_LIMITS 0xBFC 46 47 /* 48 * Message request and response to get engine group number 49 * which has attached a given type of engines (SE, AE, IE) 50 * This messages are only used between CPT PF <=> CPT VF 51 */ 52 struct otx2_cpt_egrp_num_msg { 53 struct mbox_msghdr hdr; 54 u8 eng_type; 55 }; 56 57 struct otx2_cpt_egrp_num_rsp { 58 struct mbox_msghdr hdr; 59 u8 eng_type; 60 u8 eng_grp_num; 61 }; 62 63 /* 64 * Message request and response to get kernel crypto limits 65 * This messages are only used between CPT PF <-> CPT VF 66 */ 67 struct otx2_cpt_kvf_limits_msg { 68 struct mbox_msghdr hdr; 69 }; 70 71 struct otx2_cpt_kvf_limits_rsp { 72 struct mbox_msghdr hdr; 73 u8 kvf_limits; 74 }; 75 76 /* CPT HW capabilities */ 77 union otx2_cpt_eng_caps { 78 u64 u; 79 struct { 80 u64 reserved_0_4:5; 81 u64 mul:1; 82 u64 sha1_sha2:1; 83 u64 chacha20:1; 84 u64 zuc_snow3g:1; 85 u64 sha3:1; 86 u64 aes:1; 87 u64 kasumi:1; 88 u64 des:1; 89 u64 crc:1; 90 u64 reserved_14_63:50; 91 }; 92 }; 93 94 /* 95 * Message request and response to get HW capabilities for each 96 * engine type (SE, IE, AE). 97 * This messages are only used between CPT PF <=> CPT VF 98 */ 99 struct otx2_cpt_caps_msg { 100 struct mbox_msghdr hdr; 101 }; 102 103 struct otx2_cpt_caps_rsp { 104 struct mbox_msghdr hdr; 105 u16 cpt_pf_drv_version; 106 u8 cpt_revision; 107 union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES]; 108 }; 109 110 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, 111 u64 offs, u64 val) 112 { 113 writeq_relaxed(val, reg_base + 114 OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs)); 115 } 116 117 static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot, 118 u64 offs) 119 { 120 return readq_relaxed(reg_base + 121 OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs)); 122 } 123 124 static inline bool is_dev_otx2(struct pci_dev *pdev) 125 { 126 if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID || 127 pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID) 128 return true; 129 130 return false; 131 } 132 133 static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev, 134 unsigned long *cap_flag) 135 { 136 if (!is_dev_otx2(pdev)) { 137 __set_bit(CN10K_MBOX, cap_flag); 138 __set_bit(CN10K_LMTST, cap_flag); 139 } 140 } 141 142 143 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); 144 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); 145 146 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, 147 struct pci_dev *pdev); 148 int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 149 u64 reg, u64 *val, int blkaddr); 150 int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 151 u64 reg, u64 val, int blkaddr); 152 int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 153 u64 reg, u64 *val, int blkaddr); 154 int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 155 u64 reg, u64 val, int blkaddr); 156 struct otx2_cptlfs_info; 157 int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs); 158 int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs); 159 int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs); 160 161 #endif /* __OTX2_CPT_COMMON_H */ 162